Eddie Hung [Mon, 6 Jan 2020 23:00:16 +0000 (15:00 -0800)]
Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor
Refactor abc9's DSP48E1 handling
Eddie Hung [Mon, 6 Jan 2020 19:55:56 +0000 (11:55 -0800)]
Wrap arrival functions inside `YOSYS too
Eddie Hung [Mon, 6 Jan 2020 19:39:59 +0000 (11:39 -0800)]
Merge pull request #1616 from nakengelhardt/abc_scratchpad_arg_warn
error if multiple -g options are given for abc
Eddie Hung [Mon, 6 Jan 2020 19:39:08 +0000 (11:39 -0800)]
Fix return value of arrival time functions, fix word
Eddie Hung [Mon, 6 Jan 2020 19:14:05 +0000 (11:14 -0800)]
Bump ABCREV for upstream fix
N. Engelhardt [Mon, 6 Jan 2020 18:10:13 +0000 (19:10 +0100)]
error if multiple -g options are given for abc
Eddie Hung [Mon, 6 Jan 2020 17:42:26 +0000 (09:42 -0800)]
Merge pull request #1582 from nakengelhardt/abc_scratchpad_script
Check scratchpad for abc options
N. Engelhardt [Mon, 6 Jan 2020 09:46:44 +0000 (10:46 +0100)]
check scratchpad for arguments in abc pass too
N. Engelhardt [Mon, 6 Jan 2020 09:46:10 +0000 (10:46 +0100)]
inherit default values when checking scratchpad for arguments
Miodrag Milanović [Sun, 5 Jan 2020 19:21:04 +0000 (20:21 +0100)]
Merge pull request #1611 from YosysHQ/mmicko/wrapcarry_fix
Valid to have attribute starting with SB_CARRY.
Miodrag Milanovic [Sat, 4 Jan 2020 18:00:44 +0000 (19:00 +0100)]
Valid to have attribute starting with SB_CARRY.
N. Engelhardt [Fri, 3 Jan 2020 13:11:41 +0000 (14:11 +0100)]
share codepath for scratchpad argument handling with command arguments
N. Engelhardt [Fri, 3 Jan 2020 11:28:48 +0000 (12:28 +0100)]
Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script
Eddie Hung [Thu, 2 Jan 2020 21:28:37 +0000 (13:28 -0800)]
Drive $[ABCD] explicitly
whitequark [Thu, 2 Jan 2020 21:06:17 +0000 (21:06 +0000)]
Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
Eddie Hung [Thu, 2 Jan 2020 20:48:07 +0000 (12:48 -0800)]
Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
Clifford Wolf [Thu, 2 Jan 2020 18:57:27 +0000 (19:57 +0100)]
Merge pull request #1609 from YosysHQ/clifford/fix1596
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
Clifford Wolf [Thu, 2 Jan 2020 17:58:45 +0000 (18:58 +0100)]
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 2 Jan 2020 16:46:24 +0000 (08:46 -0800)]
Merge pull request #1601 from YosysHQ/eddie/synth_retime
"abc -dff" to no longer retime by default
Eddie Hung [Thu, 2 Jan 2020 16:46:02 +0000 (08:46 -0800)]
Merge pull request #1608 from YosysHQ/eddie/ifndef_YOSYS
ifdef __ICARUS__ -> ifndef YOSYS
Eddie Hung [Thu, 2 Jan 2020 01:33:47 +0000 (17:33 -0800)]
ifndef __ICARUS__ -> ifdef YOSYS
Eddie Hung [Thu, 2 Jan 2020 01:33:10 +0000 (17:33 -0800)]
ifdef __ICARUS__ -> ifndef YOSYS
Eddie Hung [Thu, 2 Jan 2020 01:30:26 +0000 (17:30 -0800)]
Rework abc9's DSP48E1 model
Eddie Hung [Wed, 1 Jan 2020 21:31:46 +0000 (13:31 -0800)]
Merge pull request #1606 from YosysHQ/eddie/improve_tests
Fix a few issues in tests/arch/*
Eddie Hung [Wed, 1 Jan 2020 17:05:46 +0000 (09:05 -0800)]
Revert insertion of 'reg', leave note behind
Miodrag Milanović [Wed, 1 Jan 2020 16:46:45 +0000 (17:46 +0100)]
Merge pull request #1605 from YosysHQ/iopad_fix
iopad mapping should take care of existing io buffers
Eddie Hung [Wed, 1 Jan 2020 16:43:16 +0000 (08:43 -0800)]
Fix anlogic async flop mapping
Miodrag Milanovic [Wed, 1 Jan 2020 15:24:30 +0000 (16:24 +0100)]
Added a test case
Miodrag Milanovic [Wed, 1 Jan 2020 15:13:14 +0000 (16:13 +0100)]
take skip wire bits into account
whitequark [Wed, 1 Jan 2020 12:30:00 +0000 (12:30 +0000)]
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit
698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
Eddie Hung [Wed, 1 Jan 2020 02:40:30 +0000 (18:40 -0800)]
Do not do call equiv_opt when no sim model exists
Eddie Hung [Wed, 1 Jan 2020 02:40:11 +0000 (18:40 -0800)]
Fix warnings
Eddie Hung [Wed, 1 Jan 2020 02:39:32 +0000 (18:39 -0800)]
Call equiv_opt with -multiclock and -assert
Eddie Hung [Mon, 30 Dec 2019 20:26:39 +0000 (12:26 -0800)]
Grammar
Eddie Hung [Fri, 27 Dec 2019 20:15:33 +0000 (12:15 -0800)]
Update timings for Xilinx S7 cells
Eddie Hung [Mon, 30 Dec 2019 20:11:45 +0000 (12:11 -0800)]
Update doc that "-retime" calls abc with "-dff -D 1"
Eddie Hung [Mon, 30 Dec 2019 20:05:52 +0000 (12:05 -0800)]
Disable synth_gowin -abc9 as it offers no advantages yet
Eddie Hung [Mon, 30 Dec 2019 20:09:53 +0000 (12:09 -0800)]
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
This reverts commit
6008bb7002f874e5c748eaa2050e7b6c17b32745.
Eddie Hung [Mon, 30 Dec 2019 19:57:18 +0000 (11:57 -0800)]
Revert "ABC to call retime all the time"
This reverts commit
9aa94370a54c016421740d2ce32ef0aa338d0dbd.
Miodrag Milanović [Mon, 30 Dec 2019 19:34:31 +0000 (20:34 +0100)]
Merge pull request #1589 from YosysHQ/iopad_default
Make iopad option default for all xilinx flows
Eddie Hung [Mon, 30 Dec 2019 18:01:02 +0000 (10:01 -0800)]
Merge pull request #1599 from YosysHQ/eddie/retry_1588
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
Eddie Hung [Mon, 30 Dec 2019 18:00:47 +0000 (10:00 -0800)]
Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5
Nitpick cleanup for ecp5
Miodrag Milanovic [Sat, 28 Dec 2019 15:43:19 +0000 (16:43 +0100)]
Fix new tests
Miodrag Milanovic [Sat, 28 Dec 2019 15:23:31 +0000 (16:23 +0100)]
Merge remote-tracking branch 'origin/master' into iopad_default
Miodrag Milanovic [Sat, 28 Dec 2019 15:22:24 +0000 (16:22 +0100)]
Make test without iopads
Miodrag Milanovic [Sat, 28 Dec 2019 15:12:45 +0000 (16:12 +0100)]
Revert "Fix xilinx tests, when iopads are default"
This reverts commit
477e43d921d204c6bc6403109fea6506802c948c.
Eddie Hung [Sat, 28 Dec 2019 10:15:11 +0000 (02:15 -0800)]
Update resource count
Eddie Hung [Sat, 28 Dec 2019 00:57:08 +0000 (16:57 -0800)]
Nitpick cleanup for ecp5
Eddie Hung [Sat, 28 Dec 2019 00:44:57 +0000 (16:44 -0800)]
Add #1598 testcase
Eddie Hung [Sat, 28 Dec 2019 00:44:18 +0000 (16:44 -0800)]
write_xaiger: inherit port ordering from original module
Eddie Hung [Sat, 28 Dec 2019 00:05:58 +0000 (16:05 -0800)]
Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"
This reverts commit
92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing
changes made to
3e14ff16676884a1f65cf0eeb0ca9cb1958b8804.
Eddie Hung [Fri, 27 Dec 2019 23:37:26 +0000 (15:37 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Fri, 27 Dec 2019 23:35:19 +0000 (15:35 -0800)]
write_xaiger: simplify c{i,o}_bits
David Shah [Fri, 27 Dec 2019 23:31:51 +0000 (23:31 +0000)]
Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup
Revert "write_xaiger: only instantiate each whitebox cell type once"
David Shah [Fri, 27 Dec 2019 23:25:20 +0000 (23:25 +0000)]
Revert "write_xaiger: only instantiate each whitebox cell type once"
Miodrag Milanovic [Wed, 25 Dec 2019 19:38:48 +0000 (20:38 +0100)]
fixed invalid char
Marcin Kościelnicki [Sun, 22 Dec 2019 00:08:56 +0000 (01:08 +0100)]
iopadmap: Emit tristate buffers with const OE for some edge cases.
Marcin Kościelnicki [Wed, 25 Dec 2019 15:18:44 +0000 (16:18 +0100)]
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki [Wed, 25 Dec 2019 14:39:40 +0000 (15:39 +0100)]
Minor nit fixes
Eddie Hung [Mon, 23 Dec 2019 22:58:06 +0000 (14:58 -0800)]
Add DSP cascade tests
Eddie Hung [Mon, 23 Dec 2019 22:40:59 +0000 (14:40 -0800)]
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
Eddie Hung [Mon, 23 Dec 2019 22:22:13 +0000 (14:22 -0800)]
Fix CEA/CEB check
Eddie Hung [Mon, 23 Dec 2019 21:41:26 +0000 (13:41 -0800)]
Fix checking CE[AB] and for direct connections
Eddie Hung [Mon, 23 Dec 2019 20:38:18 +0000 (12:38 -0800)]
Support unregistered cascades for A and B inputs
Eddie Hung [Mon, 23 Dec 2019 19:42:46 +0000 (11:42 -0800)]
Add DSP48A* PCOUT -> PCIN cascade support
Marcin Kościelnicki [Sun, 22 Dec 2019 14:30:04 +0000 (14:30 +0000)]
xilinx: Test our DSP48A/DSP48A1 simulation models.
Marcin Kościelnicki [Sun, 22 Dec 2019 19:43:39 +0000 (20:43 +0100)]
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Miodrag Milanovic [Sat, 21 Dec 2019 19:23:23 +0000 (20:23 +0100)]
Addressed review comments
Miodrag Milanovic [Sat, 21 Dec 2019 12:21:45 +0000 (13:21 +0100)]
iopad no op for compatibility with old scripts
Miodrag Milanovic [Sat, 21 Dec 2019 12:18:44 +0000 (13:18 +0100)]
Fix xilinx tests, when iopads are default
Miodrag Milanovic [Sat, 21 Dec 2019 10:56:41 +0000 (11:56 +0100)]
Make iopad option default for all xilinx flows
Eddie Hung [Fri, 20 Dec 2019 22:56:08 +0000 (14:56 -0800)]
Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
write_xaiger: only instantiate each whitebox cell type once
Eddie Hung [Fri, 20 Dec 2019 22:06:59 +0000 (14:06 -0800)]
Add abc9_arrival times for RAM{32,64}M
Eddie Hung [Thu, 19 Dec 2019 19:24:39 +0000 (11:24 -0800)]
Add RAM{32,64}M to abc9_map.v
Eddie Hung [Fri, 20 Dec 2019 21:38:32 +0000 (13:38 -0800)]
Put specify/endspecify inside ``
Eddie Hung [Fri, 20 Dec 2019 21:09:00 +0000 (13:09 -0800)]
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
Interpret "abc9 -lut" as lut string only if [0-9:]
Eddie Hung [Fri, 20 Dec 2019 21:07:24 +0000 (13:07 -0800)]
write_xaiger: only instantiate each whitebox cell type once
Eddie Hung [Fri, 20 Dec 2019 21:03:48 +0000 (13:03 -0800)]
Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup
Revert "Optimise write_xaiger"
Eddie Hung [Fri, 20 Dec 2019 20:05:45 +0000 (12:05 -0800)]
Revert "Optimise write_xaiger"
Graham Edgecombe [Tue, 19 Nov 2019 19:46:15 +0000 (19:46 +0000)]
Fix linking with Python 3.8
The behaviour of python-config --libs has changed in Python 3.8.
For example, compare the output of it with Python 3.7 and 3.8 on an
ArchLinux system:
$ python3.7-config --libs
-lpython3.7m -lcrypt -lpthread -ldl -lutil -lm
$ python3.8-config --libs
-lcrypt -lpthread -ldl -lutil -lm -lm
$
The lack of -lpython in the latter case causes the linker to fail when
attempting to build Yosys against Python 3.8.
Passing the new --embed flag to python-config adds -lpython, just like
earlier versions of Python:
$ python3.8-config --embed --libs
-lpython3.8 -lcrypt -lpthread -ldl -lutil -lm -lm
$
This commit adds code for automatically detecting support for the
--embed flag. If it is supported, it is passed to all python-config
invocations. This fixes building against Python 3.8.
Graham Edgecombe [Tue, 19 Nov 2019 19:45:59 +0000 (19:45 +0000)]
Add PYTHON_CONFIG variable to the Makefile
Eddie Hung [Thu, 19 Dec 2019 17:24:27 +0000 (12:24 -0500)]
Merge pull request #1581 from YosysHQ/clifford/fix1565
Fix sim for assignments with lhs<rhs size
Eddie Hung [Thu, 19 Dec 2019 17:24:03 +0000 (12:24 -0500)]
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Optimise write_xaiger
Eddie Hung [Thu, 19 Dec 2019 17:21:33 +0000 (12:21 -0500)]
Merge pull request #1569 from YosysHQ/eddie/fix_1531
verilog: preserve size of $genval$-s in for loops
Eddie Hung [Thu, 19 Dec 2019 17:21:22 +0000 (12:21 -0500)]
Merge pull request #1571 from YosysHQ/eddie/fix_1570
mem_arst.v: do not redeclare ANSI port
Marcin Kościelnicki [Wed, 27 Nov 2019 17:13:00 +0000 (18:13 +0100)]
xilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki [Thu, 19 Dec 2019 07:49:21 +0000 (08:49 +0100)]
xilinx_dffopt: Keep order of LUT inputs.
See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
Eddie Hung [Wed, 18 Dec 2019 20:21:12 +0000 (12:21 -0800)]
Interpret "abc9 -lut" as lut string only if [0-9:]
Eddie Hung [Wed, 18 Dec 2019 20:09:11 +0000 (12:09 -0800)]
Add "scratchpad" to CHANGELOG
Eddie Hung [Wed, 18 Dec 2019 20:08:38 +0000 (12:08 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys
David Shah [Wed, 18 Dec 2019 19:42:17 +0000 (19:42 +0000)]
Merge pull request #1563 from YosysHQ/dave/async-prld
ecp5: Add support for mapping PRLD FFs
Eddie Hung [Wed, 18 Dec 2019 18:55:44 +0000 (13:55 -0500)]
Merge pull request #1572 from nakengelhardt/scratchpad_pass
add a command to read/modify scratchpad contents
Eddie Hung [Wed, 18 Dec 2019 17:53:45 +0000 (12:53 -0500)]
Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-test
tests/xilinx: fix flaky mux test
Marcin Kościelnicki [Wed, 18 Dec 2019 14:53:20 +0000 (15:53 +0100)]
tests/xilinx: fix flaky mux test
Marcin Kościelnicki [Wed, 18 Dec 2019 12:42:26 +0000 (13:42 +0100)]
xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki [Thu, 21 Nov 2019 05:30:06 +0000 (06:30 +0100)]
xilinx: Improve flip-flop handling.
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
Clifford Wolf [Wed, 18 Dec 2019 12:06:34 +0000 (13:06 +0100)]
Send people to symbioticeda.com instead of verific.com
Signed-off-by: Clifford Wolf <clifford@clifford.at>
N. Engelhardt [Wed, 18 Dec 2019 11:30:30 +0000 (12:30 +0100)]
use extra_args
N. Engelhardt [Tue, 17 Dec 2019 18:39:55 +0000 (19:39 +0100)]
check scratchpad variable abc9.scriptfile
Clifford Wolf [Tue, 17 Dec 2019 16:32:48 +0000 (17:32 +0100)]
Fix sim for assignments with lhs<rhs size, fixes #1565
Signed-off-by: Clifford Wolf <clifford@clifford.at>