mem: Plumb backdoor requests through the xbar classes.

Change-Id: Ic8f49339ab95c31d2f00edfdf23a46f1271ec3aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17593
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Teach the TLM bridges how to use gem5's new backdoor mechanism.

This change teaches the TLM bridges to translate between TLM's DMI
mechanism and gem5's backdoor mechanism.

Change-Id: I942a6cce4fb87f10e8173f4ee49b6c7b0ffa7e4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17591
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods.

These both perform atomic accesses like their non-backdoor equivalents,
and also request a backdoor corresponding to the access.

The default implementation for recvAtomicBackdoor prints a warning
(once per port instance), calls recvAtomic to do the actual access,
and leaves the backdoor pointer as nullptr. That way if an object
doesn't know how to handle or transfer requests for a back door, it
automatically replies in a safe way that ignores the back door request.

Change-Id: Ia9fbbe9996eb4b71ea62214d203aa039a05f1618
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17590
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Fix MSHR handling of cache clean requests

Previously satisfied clean requests would not snoop in-service
MSHRs. This is a problem when a clean request is also invalidating, in
which case we have to post-invalidate or post-downgrade outstanding
requests. This changes fixes this bug.

Change-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

cpu: O3 switchFreeList checking VecElems instead of FloatRegs

Vector elements should be checked instead of floats since those are the
ones mapped to the vector registers.

Change-Id: I36088ab90e63720d846fcf5b43360da105b6c736
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

learning_gem5,configs: Update ruby_test

Use SimpleMemory instead of DDR3 so we can use the timing results in
tests. By using SimpleMemory, even if the DRAM timing changes the timing
of this test won't change. I expect the timing of SimpleMemory to never
change.

Change-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

learning_gem5: Fix vector port panic in SimpleCache

Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Fix import path error in learning_gem5 part3

Change-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Add full path for learning_gem5 binaries

Change-Id: Ie48429d65e322136109a223ed404937989aae494
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Removed redudant exec-style import

garnet_synth_traffic.py imports common.Options on line 40, so exec'ing
the Options.py file again seems redundant.

It also runs Options.py as a script rather than a module, which throws
ValueError: Attempted relative import in non-package due to the recent
change to python3 imports.

Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Add a MemBackdoor type to track memory backdoors.

These are similar to the structures TLM's DMI mechanism uses. Instead
of having an invalidation broadcast which propogates backwards up the
port hierarchy, this mechanism tracks a set of callbacks which are
triggered when a back door is invalidated to let other holders clean
up their bookkeeping.

Change-Id: If24489258dcaee14d7b6e5b996dfb1c2636f26ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17589
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Correctly account for executed instructions in simple cpus

Change-Id: I53f34b2d9db6e4d2e03dde42a970764bb2a5e701
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17730
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: ambiguous use of abs function

std::abs doesn't accept unsigned long long, generating the error:

error: call to 'abs' is ambiguous

Use instead a compare-and-subtract idiom.

Also, Changed return type of distanceFromTrigger from unsigned int to Addr to
prevent overflow problems.

Change-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Reverse order of write/read mem queue check

For atomic RMW instructions that go directly to memory, we want to put
them on the write queue instead of the read queue. Swap the if/else
condition to accomplish this.

Note: This is ignoring the read latency of the RMW, but these
instructions should usually be handled in caches anyway.

Change-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

tests: Add Jenkins presubmit and continuous test scripts

Note that continuous currently isn't used.

Change-Id: Ifcff88c8c4c75a9f630b97eaca22edd1681529c3
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17456
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: AMPM Prefetcher fails when restoring from a checkpoint

The preriodic event triggers an assertion due to an incorrect tick value to
schedule when restoring from a checkpoint.

Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Removed inconsistency in O3* debug msgs

Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines

Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-mips: added missing override specifier (o3)

Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix PIF prefetcher compilation error with NULL ISA

Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.

Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: ISB prefetcher was triggering an assertion

An assertion ignored the case when an entry of the SP table had been invalidated.

Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix panic in Indirect Memory prefetcher

Memory requests with a size non-power-of-two and less than 8 values were causing
a panic, but there these should be allowed and ignored by the prefetcher.

Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt

Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Proactive Instruction Fetch Implementation

Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December).
Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM
International Symposium on Microarchitecture (pp. 152-162). ACM.

Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

dev-arm: Correct cast of template parameter

Clang with -Wconstant-conversion is _very_ restrictive on casting.
The shift operator results in an incorrect promotion.

This patch add a compile-time static cast that remove the error
when clang is used.

Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Templatize the gem5/TLM bridge SimObjects.

The C++ side is templated, and there are python versions for each
(currently two) width of bridge supported.

Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Delete extra code from src/systemc/tlm_bridge.

Much of the code in src/systemc/tlm_bridge has been absorbed into the
TLM/gem5 bridge SimObjects and is no longer needed and redundant with
the original version in util/.

Change-Id: I0fa7af67649987cf9f6fc5cd4783002dde2242ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17233
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Create unified gem5/TLM bridge SimObjects.

These objects expose a standard TLM initiator or target socket with
width 64, and a gem5 slave or master port. What goes in one type of
port comes out the other with the appropriate conversion applied.

Change-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17232
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

tlm: Initial import of tlm/gem5 bridge code.

This is a slightly mangled version of the existing bridge code in
util/tlm/src/. The changes fix some small style issues, change to gem5
specific include paths, and removes the Gem5SimControl code. That code
coordinates gem5 with the external systemc kernel, and in this usage
there's no external kernel.

The code imported here compiles, but it isn't yet expected to work.

Change-Id: I9c593a52e2554534720d21cd31a03e543ad897ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17231
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Provide a utility Port TLM socket wrapper class.

This class should make it easy to attach TLM sockets into the gem5
python Port config mechanism.

Change-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17230
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Added a probe to notify the address of retired instructions

A probe is added to notify the address of each retired instruction.

Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Remove extra cache header from AMAP

The cache header was being included in the AMAP, although not
used, which resulted in slightly longer compilation time.

Change-Id: I3654bc719c6b5f558af116addae159301602a3cf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Fix use of bitwise operators on booleans

Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix index generation for VecElem operands

Current operand generation is not providing VecElems with the right
vector index and element index.
The bug was covered when registers were 128 bit wide, but with SVE we
have augmented the vector register size and the bug has been exposed.

E.g. With dest = 2,

FpDestP2 = (vec_index = 0, elem_index = 4)

whereas it should be

FpDestP2 = (vec_index = 1, elem_index = 0)

Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710

dev-arm: Rename GIC maintenance interrupt from ppint to maint_int

ppint is a generic name which only reflects Arm recommendation of
assigning the maintanance interrupt to a PPI (numbered 25)

Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Fix GICv3 overflow for INTID > 256

SPIs can get to a maximum number of 1023, so that an uint8_t is not capable
of representing all of them.

Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)

For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.

Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: Use the corresponding HPI Caches when using the HPI cpu

The HPI cpu comes with specific cache definitions, but they
are ignored when using this cpu. This patch solves this in the same
way it is done for the O3_ARM_v7a cpu.

Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fixed the indirect branch predictor GHR handling

The internal indirect predictor global history was not being updated
properly, resulting in higher than expected miss rates

Also added a parameter to set the size of the indirect predictor GHR

Change-Id: Ibc797816974cba6719da65122801e8919559a003
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reported-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16928
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Deleting this init() method was accidentally dropped during rebase.

Deleting this init() method was part of a change just committed, but
was accidentally dropped during a rebase.

Change-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Clean up the xbars a little.

Get rid of comments which just restate the code, get rid of redundant
"virtual" keywords, add "override"s, fix style, and get rid of
xbar::init which was empty and hiding the parent class init.

Change-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Make AddrRangeMap able to return non-const iterators.

The erase() method only accepts regular iterators which is consistent
with the normal STL map, but the existing find() only returns const
iterators. The STL container can return either depending on if "this"
is const.

Unfortunately there isn't a great way to have only one find
implementation which returns the right type of iterator under the right
conditions. Also, it's not possible to turn a const_iterator into an
iterator, but it is possible to go the other way. This change
duplicates very short functions which return iterators, and for find
does the only thing I could find which avoids having to copy that
whole large function.

Change-Id: I2f789b5d0881feb9adff9978bd40e31731c6a688
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17588
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: fix class reference in CacheConfigs

One reference was not properly updated when changing to absolute import paths

Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Set/Unset dma coherent mode from python

With this patch it will be possible to automatically enable/disable the
dma-coherent property for the GenericArmPciHost autogenerated DTB.  This
has been done by adding the _dma_coherent param.

Change-Id: I1759fced74e42410462637ca77997a351314a90a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base,python: Fix to allow multiple --debug-ignore values.

When adding multiple SimObjects to --debug-ignore, either separating the values with
a colon or adding multiple --debug-ignore flags, the previous code only ignored the
last SimObject in the list.  This changeset adds and uses new `ObjectMatch::add` and
`Logger::addIgnore` methods to make the functionality of the flag consistent with
its description.

Change-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

configs: Remove default kernel value from system creation

Kernel was being set using a placeholder and then assigned the
correct value. This would generate the following error if the
placeholder file did not exist:
'IOError: Can't find file <placeholder> on path'

This patch follows the same directions of commit
12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default
values, forcing the user to properly configure the kernel.

Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add missing fall-through defaults

Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-power: Rename program counter registers

The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.

Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-power: Simplify doubleword operand types

Currently, 'sq' and 'uq' are used to represent signed and
unsigned doublewords respectively. Since all recent Power
ISA specifications list 128-bit quadwords as a valid data
type, it may be misleading to use the current terminology
in case support for such operands are added in the future.
So, to simplify this, 'sd' and 'ud' are used to represent
signed and unsigned doublewords respectively.

Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

misc: missing override specifier

Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim-se: Fixed initialization array size

Doubled the size of the zeroed auxiliary vector since 2 * intSize on
aarch64 > sizeof(uint64).

Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

base: Fix CircularQueue's operator-= when negative subtraction

Using operator-= when the rhs is a negative value is equivalent
to using += on -rhs. This is fixing rounding in that scenario.

Change-Id: Ia22e51f81a6805d27fd6b2115d288bb23421d00f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17528
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Fix CircularQueue when diffing iterators

This patch is fixing CircularQueue iterators' subtraction, in particular
the behaviour when head and tail round multiple times.

Change-Id: Ie79ac8accd30a10cf039cf4def87675b01375d6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17188
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: ambiguous use of getPort()

The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.

This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)

Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Add ignore for stdin not terminal

Change-Id: I496a9f3a0156557415d455dd2ca54c92577ca5f5
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17455
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Use full path for DownloadedProgram

Change-Id: I1dceca80a425293d64f81b06ddff499363f18bc0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17454
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

tests: Fix race condition in download fixture

Change-Id: Idace0e9e71a484080fc581e232ce217b449085c1
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17453
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

ext,tests: Add back failing exceptions

Change-Id: Idf4ba8a2a3888787abf33d1a4ac52fcf146ce732
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17452
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

tests,ext: Add skip_cleanup implementation for TempdirFixture

Change-Id: Idc5ec9309a4ef3c0ad0c7e8b2df47294acc97ec4
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17451
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

ext,tests: Make return code based on test results

This patch also fixes a spelling mistake.

Change-Id: I8635216e512c10913a9cda54541d7e31e0d22a40
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17450
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

ext,test: Provide default terminal size

When creating the separator for printing things to the terminal (=.*) we
use an ioctl that isn't supported in some sandboxed environments. When
running on the Google jenkins server (kokoro) it errors with an IOError.

Change-Id: I148dd87cffe6e93d6723a386aecf9a9ea6c5b455
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17449
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-kvm: Added informative error message

PerfKvmCounter::attach fails if the user doesn't have privileges to make
the perf_event_open syscall. This is the default privilege setting since
kernel 4.6. I've seen some users in the mailing list resort to running
as root; changing the perf_event_paranoid setting is an alternative.

Change-Id: I2bc6f76abb6e97bf34b408a611f64b1910f50a43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17508
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Added the STeMS prefetcher

Reference:
    Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
    Babak Falsafi. 2009. Spatio-temporal memory streaming.
    In Proceedings of the 36th annual international symposium on
    Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.

Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

systemc: Hook up gem5_getPort to the gem5 getPort mechanism.

Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Switch to the new getPort mechanism to connect ports.

This retrieves ports using the getPort method, and connects them using
the bind method on the ports themselves. Any smarts as far as what type
of peers are allowed to connect or how they connect is left up to the
individual bind methods.

Change-Id: Ic640d1fce8af1bed411116e5830edc4a8a0f9d66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17039
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Move bind() and unbind() into the Port class.

These are now pure virtual methods which more specialized port
subclasses will need to implement. The SlavePort class implements them
by ignoring them and then providing parallel functions for the
MasterPort to call. The MasterPort's methods do basically what they
did before, except now bind() uses dynamic cast to check if its peer
is of the appropriate type and also to convert it into that type before
connecting to it.

Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Add a getPort function to SimObject.

This will retrieve a Port object from a given SimObject (which might
not be a MemObject) no matter what flavor of Port it is.

Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Build m5 with -no-pie flag

Added -no-pie flag to link /util/m5 to support newer versions of GCC
that enable PIE by default. Tested for backwards compatibility with GCC
4.3, which, only warns for the unrecognized flag.

Change-Id: I4b6df593936346b9d3e2fe29a5d85dde78b7cc5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17429
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Change || to && for MessageBuffers in connectPorts.

The connectPorts function currently checks if *either* of the peers in
a port connection are a MessageBuffer, and if so will ignore the
connection. This CL changes that || into a && so that *both* of the
peers need to be a Ruby types (either a MessageBuffer or Network) for
the connection to be ignored. That makes it easier to contain that
abnormal behavior to those types instead of having it apply even when
other types of port owners are involved.

Unfortunately the number of interesting Ruby types is unbounded, but
these are the types with ports as of today. This mechanism will
hopefully be replacedall together so this should be a temporary issue.

Change-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17031
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Improve how templated SimObject classes are handled.

When setting up a SimObject's Param structure, gem5 will autogenerate
a header file which attempts to declare the SimObject's C++ type. It
has had at least some level of sophistication there where it would
pull off the namespaces ahead of the class name and handle them
properly, but it didn't know how to handle templates.

This change improves that handling in two ways. First, it adds a new
magical SimObject attribute called 'cxx_template_params' which is used
to specify what the template parameters are as a list. For instance, if
your SimObject was a template which took an integer constant as its
first parameter and a type as its second, this attribute could look
like the following:

cxx_template_params = [ 'int FOO', 'class Bar' ]

Importantly, if there are any default values for these template
parameters, they should *not* be included here, they should be
specified where the class is later defined.

The second new mechanism is to add an internal CxxClass in the
SimObject.cxx_param_decl method. This class accepts the class signature
in the cxx_class attribute and the cxx_template_params and does two
things. First, it strips off namespaces like in the old implementation.
Second, it extracts and processes any template arguments attached to
the class. If these are constants (as determined by the contents of
cxx_template_params), then they are stored verbatim. If they're types,
then they're recursively expanded into a CxxClass and stored that way.
Note that these are the *values* of the template arguments, where as
cxx_template_params lists the *types* and *names* of those arguments.
In our earlier example, if cxx_class was:

cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>'

Then CxxClass would extract the namespace 'CoolClasses', the class
name 'ClassName', the argument '12', and the argument 'Fruit::Apple'.
That second argument would be expanded into a CxxClass with the
namespace 'Fruit' and the class name 'Apple'.

Importantly here, because there were no default arguments given in
cxx_template_params, all "hidden" arguments which would fall through
to their defaults need to be fully specified in cxx_class.

The CxxClass has a method called declare() which uses the information
extracted earlier to output all of the "stuff" necessary for declaring
the given class, including opening any containing namespaces and
putting template<...> ahead of the actual class declaration with the
template parameters specified.

If any of the template arguments are themselves CxxClass instances,
then they'll be recursively declared immediately before the current
class is.

An alternative solution to this problem might be to include the header
file which actually defines the cxx_class type to avoid having to
come up with a declaration. Unfortunately this doesn't work since it
can set up include loops where the SimObject C++ header file includes
the param header to get access to the Param type, but that includes
the C++ header to get access to the SimObject type.

This also makes it harder for SimObjects to refer to each other, since
they rely on the declaration in the params header files when declaring
a member pointer to that type in their own Param structures.

Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

scons: fix disable_partial logic for fast binary

Partial linking should be disabled on darwin; however, the script
fails to do so when force_lto is set, which results in gem5 building
with fast option fails on macOS. This fix changes disable_partial
logic, which should be True once it's True.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I77d2a4cc4a9bf5c92c800c004eb744bb7081c42e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16888
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: changed shebang on gem5img.py to python2.7

Change-Id: Id1a2112ce940bf6721609e2637d925d35e5ded8a
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: tautological comparison of byteOrder

Error:
build/X86/mem/cache/prefetch/indirect_memory.cc:56:24:
error: result of comparison of constant -1 with expression
of type 'const ByteOrder' is always false
[-Werror,-Wtautological-constant-out-of-range-compare]
    fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n");
             ~~~~~~~~~ ^  ~~
build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if'
        if ((cond)) {                                           \
             ^~~~
1 error generated.

Fix:
cast of constant (-1) used in comparison

Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Use absolute import paths

Use absoluate import paths to be Python 3 compatible. This also
imports absolute_import from __future__ to ensure that Python 2.7
behaves the same way as Python 3.

Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Removed circular include ref

If BasicLink.hh is modified, the style checker forces a reordering of
the includes, which results in build errors because it ends up including
Topology.hh before including its xxxParams.hh files, which include
forward declarations of the BasicLink family of classes, and so
Topology.hh throws errors that BasicLink etc. are not declared.

Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added the Indirect Memory Prefetcher

Reference:
    Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas.
    2015. IMP: indirect memory prefetcher. In Proceedings of the 48th
    International Symposium on Microarchitecture (MICRO-48). ACM,
    New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807

Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Move the Port base class into sim.

The Port class is going to be officially used for more than just memory
system connections.

Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Make EtherInt inherit from Port.

This way a common function can return EtherInt (and master and slave
ports).

Change-Id: I1215baaad918ef0352b228877241b2b6dd2503fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Track the MemObject owner in MasterPort and SlavePort.

These types are much more tied to MemObjects and the gem5 memory
protocol than the Port or BaseMasterPort and BaseSlavePort classes.

Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

python: Simplify connectPorts() around EtherObject/EtherDevice.

EtherDevice now inherits EtherObject and shares the same getEthPort
virtual function, so there's no need to treat them separately any more.

Change-Id: Ia6c147fd97fece4a281c296521a7b095f793d32e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17030
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Make the EtherDevice class inherit EtherObject.

This avoids having to define two parallel versions of the getEthPort
function, and the complex dynamic_cast macrame in connectPorts().

Change-Id: I24c09864005ff39a049e50d7245ff17e9480edea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17029
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Turn EtherObject into an interface class.

This class used to drive from SimObject so that it could be derived
from to get both the interface and SimObject while still using single
inheritance.

With this change, EtherObject is now just an interface class with only
one pure virtual function which can be inherited alongside SimObject.
This makes it more flexible so that it can be used in places where you
might want a different inheritance hierarchy, for instance to inherit
from MemObject.

Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17028
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Fix write hit latency calculation order

Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order
at which the access latency is calculated for hits. This order
is incorrect, since the calculations must use the blk's whenReady
value before the access is satisfied.

Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Teach cxxMethod how to set return_value_policy.

This is passed through to the underlying call to PyBindMethod.

Change-Id: Ib46c55664ba0707464bb84e137a0fad817aea1bb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17034
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Teach PyBindMethod how to set return_value_policy.

Change-Id: Ia208e43672672556b36f905e8f71dce44b978d22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17033
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Refactor of Physical Register implementation

The implementation of the PhyRegId class is shared between multiple
cpu models. The o3/misc.hh should only be included in o3 models.

This patch removes the dependencies between different model
implementations, allowing to add new O3-like CPU model.

Change-Id: Ibb812517043befe75c48fab3ce9605a0d272870b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16908
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Fix unknown params and proxy multiplication

One of the recent changes made params not visible anymore:
    NameError: global name 'params' is not defined
This is fixed by adding the proper import statement.

However, the second error makes the multiplication values be assigned
to other proxies (that are not even used on the multiplication). A
workaround is added to prevent this from happening by extending "*=".

Change-Id: I3ad276a456efff62058672d16caac2b3ad1b326b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17048
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: cleanup of gicv3 CPU interface code and fixes

Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Don't use isdir in AddLocalRPATH.

isdir isn't a nice way to check if an FS.Base is a File or a Dir as was
initially assumed, it literally checks if a path can be stat-ed and is
reported as a directory by stat. This means that if a directory is
going to be created as part of the build, the result of that test will
change depending on whether that part of the build has happened
successfully before.

A better check which behaves as originally intended is to check whether
the Node is an instance of the SCons.Node.FS.Dir class.

Change-Id: Id041917d50b768a8205769c0a05320f92b09993c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17128
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add size to array unserialization error message

Add both acquired and expected size information to array
unserialization error message.

Change-Id: Ic0a493c5a7860066eb992e9e91e7a4746b197579
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16542
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-arm: cleanup of gicv3 code

Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Removed default arg from get() in prefetch/base.hh

commit b0d1643 caused building against NULL to break due to
NULLIsa::GuestByteOrder not being defined.

Removal of default argument in src/mem/cache/prefetch/base.hh fixes
this.

Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0
Signed-off-by: Ryan Gambord
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-hsail: changed gen.py shebang from python(3) to python2.7

gen.py includes code_formatter from m5.util. code_formatter uses the
python2 __metaclass__ attribute, which is ignored by python3, causing
the code_formatter.pattern attribute to be unset.

This prevented scons from building against HSAIL_X86

Signed-off-by: Ryan Gambord
<gambordr@oregonstate.edu>

Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17008
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-arm: Fixing implicit fallthrough build errors

2c242d6 introduced implicit-fallthrough errors when building against
ARM.

Added "default: return new Unknown(machInst);" to offending switch
statements; please verify this is the corret behavior

Signed-off-by: Ryan Gambord
Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"

Reverting patch due to polymorphism limitations.

This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb.

Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added extra information to PrefetchInfo

Added additional information to the PrefetchInfo data structure
- Whether the event is triggered by a cache miss
- Whether the event is a write or a read
- Size of the data accessed
- Data accessed by the request

Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add header delay to handleFill whenReady

A prefetch response will have a header delay, which was not being
taken into account.

Change-Id: I66a071bc81ef41b8c0de37aa2df75171d1979a6f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Allow tag-only accesses on latency calculation

Some accesses only need to search for a tag in the tag array, with
no need to touch the data array. This is the case for CleanEvicts,
evicts that don't find a corresponding block entry (since a write
cannot be done in parallel with tag lookup), and maintenance
operations.

Change-Id: I7365a915500b5d7ab636d49a9acc627072a7f58e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14878
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add lookup latency to access' whenReady

When dealing with writebacks, as soon as the packet metadata arrives
there will be a tag lookup, done sequentially because a write can't
be done in parallel. While the tag lookup is being done, the payload
will arrive. When both the payload are present and the tag is correct
block entry is determined the fill happens.

Change-Id: If1a0085d742458b675bfc012b6d908d9d9a25e32
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14877
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>