Clifford Wolf [Sun, 4 Nov 2018 09:08:33 +0000 (10:08 +0100)]
Merge pull request #687 from trcwm/master
Liberty file: error when it contains pin references to non-existing pins
Clifford Wolf [Sun, 4 Nov 2018 09:04:48 +0000 (10:04 +0100)]
Merge pull request #688 from ZipCPU/rosenfell
Make rose and fell dependent upon LSB only
ZipCPU [Sat, 3 Nov 2018 17:39:32 +0000 (13:39 -0400)]
Make and dependent upon LSB only
Niels Moseley [Sat, 3 Nov 2018 17:38:49 +0000 (18:38 +0100)]
Liberty file newline handling is more relaxed. More descriptive error message
Niels Moseley [Sat, 3 Nov 2018 17:07:51 +0000 (18:07 +0100)]
Report an error when a liberty file contains pin references that reference non-existing pins
Clifford Wolf [Thu, 1 Nov 2018 14:25:24 +0000 (15:25 +0100)]
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 1 Nov 2018 10:40:58 +0000 (11:40 +0100)]
Add support for signed $shift/$shiftx in smt2 back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 31 Oct 2018 14:37:39 +0000 (15:37 +0100)]
Merge branch 'igloo2'
Clifford Wolf [Wed, 31 Oct 2018 14:36:53 +0000 (15:36 +0100)]
Fix sf2 LUT interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 31 Oct 2018 14:28:57 +0000 (15:28 +0100)]
Basic SmartFusion2 and IGLOO2 synthesis support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Oct 2018 10:25:07 +0000 (11:25 +0100)]
Merge pull request #680 from jburgess777/fix-empty-string-back-assert
Avoid assert when label is an empty string
Jon Burgess [Sun, 28 Oct 2018 14:49:09 +0000 (14:49 +0000)]
Avoid assert when label is an empty string
Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:
$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.
802 if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
Clifford Wolf [Thu, 25 Oct 2018 11:23:26 +0000 (13:23 +0200)]
Merge pull request #678 from whentze/master
Fix unhandled std::out_of_range in run_frontend() due to integer underflow
Clifford Wolf [Thu, 25 Oct 2018 11:20:00 +0000 (13:20 +0200)]
Fix minor typo in error message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 25 Oct 2018 11:18:59 +0000 (13:18 +0200)]
Merge pull request #679 from udif/pr_syntax_error
More meaningful SystemVerilog/Verilog parser error messages
Udi Finkelstein [Wed, 24 Oct 2018 23:37:56 +0000 (02:37 +0300)]
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
Clifford Wolf [Tue, 23 Oct 2018 17:18:45 +0000 (19:18 +0200)]
Merge pull request #677 from daveshah1/ecp5_dsp
ecp5: Add blackboxes for MULT18X18D and ALU54B
whentze [Mon, 22 Oct 2018 17:40:22 +0000 (19:40 +0200)]
fix unhandled std::out_of_range when calling yosys with 3-character argument
David Shah [Mon, 22 Oct 2018 15:20:38 +0000 (16:20 +0100)]
ecp5: Remove DSP parameters that don't work
Signed-off-by: David Shah <davey1576@gmail.com>
David Shah [Sun, 21 Oct 2018 18:27:02 +0000 (19:27 +0100)]
ecp5: Add DSP blackboxes
Signed-off-by: David Shah <davey1576@gmail.com>
Clifford Wolf [Sat, 20 Oct 2018 21:48:53 +0000 (23:48 +0200)]
Improve read_verilog range out of bounds warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Oct 2018 21:28:09 +0000 (23:28 +0200)]
Merge pull request #674 from rubund/feature/svinterface_at_top
Support for SystemVerilog interfaces as ports in the top level module + test case
Ruben Undheim [Sat, 20 Oct 2018 10:45:51 +0000 (12:45 +0200)]
Refactor code to avoid code duplication + added comments
Ruben Undheim [Sat, 20 Oct 2018 09:58:25 +0000 (11:58 +0200)]
Support for SystemVerilog interfaces as a port in the top level module + test case
Ruben Undheim [Sat, 20 Oct 2018 09:57:39 +0000 (11:57 +0200)]
Fixed memory leak
Clifford Wolf [Fri, 19 Oct 2018 15:32:42 +0000 (17:32 +0200)]
Merge pull request #673 from daveshah1/ecp5_improve
Small ECP5 improvements
David Shah [Thu, 18 Oct 2018 18:40:02 +0000 (19:40 +0100)]
ecp5: Sim model fixes
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 18 Oct 2018 18:39:48 +0000 (19:39 +0100)]
ecp5: Add latch inference
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 19 Oct 2018 14:09:11 +0000 (16:09 +0200)]
Merge pull request #672 from daveshah1/fix_bram
memory_bram: Reset make_outreg when growing read ports
David Shah [Fri, 19 Oct 2018 13:45:45 +0000 (14:45 +0100)]
memory_bram: Reset make_outreg when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 19 Oct 2018 11:05:51 +0000 (13:05 +0200)]
Merge pull request #671 from rafaeltp/master
adding offset info to memories on verilog output
Clifford Wolf [Fri, 19 Oct 2018 11:03:38 +0000 (13:03 +0200)]
Merge pull request #670 from rubund/feature/basic_svinterface_test
Basic test for checking correct synthesis of SystemVerilog interfaces
rafaeltp [Thu, 18 Oct 2018 23:22:33 +0000 (16:22 -0700)]
adding offset info to memories
rafaeltp [Thu, 18 Oct 2018 23:20:21 +0000 (16:20 -0700)]
adding offset info to memories
Ruben Undheim [Thu, 18 Oct 2018 19:27:04 +0000 (21:27 +0200)]
Basic test for checking correct synthesis of SystemVerilog interfaces
Clifford Wolf [Thu, 18 Oct 2018 10:26:53 +0000 (12:26 +0200)]
Update ABC to git rev
14d985a
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 18 Oct 2018 08:58:47 +0000 (10:58 +0200)]
Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
Clifford Wolf [Thu, 18 Oct 2018 08:54:03 +0000 (10:54 +0200)]
Merge pull request #657 from mithro/xilinx-vpr
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
Clifford Wolf [Thu, 18 Oct 2018 08:52:07 +0000 (10:52 +0200)]
Merge pull request #664 from tklam/ignore-verilog-protect
Ignore protect endprotect
Clifford Wolf [Wed, 17 Oct 2018 10:23:50 +0000 (12:23 +0200)]
Update ABC to git rev
c5b48bb
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 17 Oct 2018 10:23:36 +0000 (12:23 +0200)]
Minor code cleanups in liberty front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 17 Oct 2018 10:21:17 +0000 (12:21 +0200)]
Merge pull request #660 from tklam/parse-liberty-detect-ff-latch
Handling ff/latch in liberty files
Clifford Wolf [Wed, 17 Oct 2018 10:18:57 +0000 (12:18 +0200)]
Merge pull request #663 from aman-goel/master
Update to .smv backend
Clifford Wolf [Wed, 17 Oct 2018 10:16:23 +0000 (12:16 +0200)]
Merge pull request #658 from daveshah1/ecp5_bram
ECP5 BRAM inference
Clifford Wolf [Wed, 17 Oct 2018 10:15:14 +0000 (12:15 +0200)]
Merge pull request #641 from tklam/master
Fix issue #639
Clifford Wolf [Wed, 17 Oct 2018 10:13:18 +0000 (12:13 +0200)]
Merge pull request #638 from udif/pr_reg_wire_error
Fix issue #630
Clifford Wolf [Tue, 16 Oct 2018 14:51:58 +0000 (16:51 +0200)]
We have 2018 now
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 16 Oct 2018 14:44:58 +0000 (16:44 +0200)]
After release is before release
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 16 Oct 2018 14:40:10 +0000 (16:40 +0200)]
Merge branch 'yosys-0.8-rc'
Clifford Wolf [Tue, 16 Oct 2018 14:22:16 +0000 (16:22 +0200)]
Yosys 0.8
Signed-off-by: Clifford Wolf <clifford@clifford.at>
argama [Tue, 16 Oct 2018 13:33:37 +0000 (21:33 +0800)]
ignore protect endprotect
Clifford Wolf [Tue, 16 Oct 2018 13:28:37 +0000 (15:28 +0200)]
Update command reference manual
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Tue, 16 Oct 2018 11:48:39 +0000 (12:48 +0100)]
ecp5: Disable LSR inversion
Signed-off-by: David Shah <dave@ds0.me>
Aman Goel [Mon, 15 Oct 2018 17:54:12 +0000 (13:54 -0400)]
Minor update
Ruben Undheim [Sat, 13 Oct 2018 18:48:55 +0000 (20:48 +0200)]
Handle FIXME for modport members without type directly in front
Ruben Undheim [Sat, 13 Oct 2018 18:34:44 +0000 (20:34 +0200)]
Documentation improvements etc.
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
argama [Sat, 13 Oct 2018 17:42:48 +0000 (01:42 +0800)]
detect ff/latch before processing other nodes
tklam [Sat, 13 Oct 2018 15:24:24 +0000 (23:24 +0800)]
stop check_signal_in_fanout from traversing FFs
tklam [Sat, 13 Oct 2018 15:11:19 +0000 (23:11 +0800)]
stop check_signal_in_fanout from traversing FFs
tklam [Sat, 13 Oct 2018 14:52:31 +0000 (22:52 +0800)]
Merge branch 'master' of https://github.com/YosysHQ/yosys
Ruben Undheim [Fri, 12 Oct 2018 20:02:29 +0000 (22:02 +0200)]
Fix build error with clang
Ruben Undheim [Fri, 12 Oct 2018 18:58:37 +0000 (20:58 +0200)]
Support for 'modports' for System Verilog interfaces
Ruben Undheim [Thu, 11 Oct 2018 21:33:31 +0000 (23:33 +0200)]
Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
David Shah [Fri, 12 Oct 2018 13:22:21 +0000 (14:22 +0100)]
BRAM improvements
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 10 Oct 2018 16:18:17 +0000 (17:18 +0100)]
ecp5: Adding BRAM maps for all size options
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 10 Oct 2018 15:35:19 +0000 (16:35 +0100)]
ecp5: First BRAM type maps successfully
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 10 Oct 2018 15:11:00 +0000 (16:11 +0100)]
ecp5: Script for BRAM IO connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Tue, 9 Oct 2018 13:19:04 +0000 (14:19 +0100)]
ecp5: Adding BRAM initialisation and config
Signed-off-by: David Shah <dave@ds0.me>
Tim 'mithro' Ansell [Mon, 8 Oct 2018 23:52:12 +0000 (16:52 -0700)]
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
Clifford Wolf [Sun, 7 Oct 2018 17:48:42 +0000 (19:48 +0200)]
Improve Verific importer blackbox handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Fri, 5 Oct 2018 10:35:59 +0000 (11:35 +0100)]
ecp5: Add blackbox for DP16KD
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 5 Oct 2018 07:59:57 +0000 (09:59 +0200)]
Merge pull request #651 from ARandomOWL/stdcells_fix
Fix IdString M in setup_stdcells()
Clifford Wolf [Fri, 5 Oct 2018 07:41:18 +0000 (09:41 +0200)]
Add "write_edif -attrprop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 5 Oct 2018 07:29:26 +0000 (09:29 +0200)]
Merge pull request #654 from mithro/patch-1
Fix misspelling in issue_template.md
Clifford Wolf [Fri, 5 Oct 2018 07:26:10 +0000 (09:26 +0200)]
Fix compiler warning in verific.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Tim Ansell [Fri, 5 Oct 2018 00:15:30 +0000 (17:15 -0700)]
Fix misspelling in issue_template.md
It's been bugging me :-P
Adrian Wheeldon [Thu, 4 Oct 2018 14:36:26 +0000 (15:36 +0100)]
Fix IdString M in setup_stdcells()
Clifford Wolf [Thu, 4 Oct 2018 09:30:55 +0000 (11:30 +0200)]
Add inout ports to cells_xtra.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 4 Oct 2018 09:30:00 +0000 (11:30 +0200)]
Merge pull request #650 from mithro/patch-1
xilinx: Adding missing inout IO port to IOBUF
Tim Ansell [Wed, 3 Oct 2018 23:38:32 +0000 (16:38 -0700)]
xilinx: Adding missing inout IO port to IOBUF
tklam [Wed, 3 Oct 2018 13:17:03 +0000 (21:17 +0800)]
Merge branch 'master' of https://github.com/YosysHQ/yosys
Clifford Wolf [Tue, 2 Oct 2018 08:00:10 +0000 (10:00 +0200)]
Merge pull request #645 from daveshah1/ecp5_dram_fix
ecp5: Don't map ROMs to DRAM
Clifford Wolf [Tue, 2 Oct 2018 07:51:44 +0000 (09:51 +0200)]
Merge pull request #646 from tomverbeure/issue594
Fix for issue 594.
Tom Verbeure [Tue, 2 Oct 2018 07:44:23 +0000 (07:44 +0000)]
Fix for issue 594.
Aman Goel [Mon, 1 Oct 2018 23:03:10 +0000 (19:03 -0400)]
Update to .smv backend
Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
Dan Gisselquist [Mon, 1 Oct 2018 17:41:35 +0000 (19:41 +0200)]
Add read_verilog $changed support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Mon, 1 Oct 2018 17:34:41 +0000 (18:34 +0100)]
ecp5: Don't map ROMs to DRAM
Signed-off-by: David Shah <davey1576@gmail.com>
Aman Goel [Mon, 1 Oct 2018 13:09:40 +0000 (09:09 -0400)]
Merge pull request #4 from YosysHQ/master
Merge with official repo
Clifford Wolf [Sun, 30 Sep 2018 16:44:07 +0000 (18:44 +0200)]
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
Clifford Wolf [Sun, 30 Sep 2018 16:43:35 +0000 (18:43 +0200)]
Fix handling of $past 2nd argument in read_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 28 Sep 2018 15:20:43 +0000 (17:20 +0200)]
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
Clifford Wolf [Fri, 28 Sep 2018 15:20:16 +0000 (17:20 +0200)]
Update to v2 YosysVS template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
tklam [Wed, 26 Sep 2018 09:57:39 +0000 (17:57 +0800)]
fix bug: pass by reference
TK Lam [Wed, 26 Sep 2018 08:11:45 +0000 (16:11 +0800)]
Fix issue #639
Udi Finkelstein [Mon, 24 Sep 2018 21:32:57 +0000 (00:32 +0300)]
Fixed issue #630 by fixing a minor typo in the previous commit
(as well as a non critical minor code optimization)
Clifford Wolf [Mon, 24 Sep 2018 18:51:16 +0000 (20:51 +0200)]
Add "read_verilog -noassert -noassume -assert-assumes"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 23 Sep 2018 08:32:54 +0000 (10:32 +0200)]
Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 23 Sep 2018 08:04:37 +0000 (10:04 +0200)]
Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc
Clifford Wolf [Sun, 23 Sep 2018 07:25:40 +0000 (09:25 +0200)]
Update CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Miodrag Milanovic [Fri, 21 Sep 2018 18:43:49 +0000 (20:43 +0200)]
added prefix to FDirection constants, fixing windows build