libreriscv.git
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2 years agoadd more links
Luke Kenneth Casson Leighton [Tue, 24 May 2022 16:18:31 +0000 (17:18 +0100)]
add more links

2 years agowhitespace, add links
Luke Kenneth Casson Leighton [Tue, 24 May 2022 15:51:48 +0000 (16:51 +0100)]
whitespace, add links

2 years agoadd transcript of silicon salon 2022 talk
Luke Kenneth Casson Leighton [Tue, 24 May 2022 15:39:16 +0000 (16:39 +0100)]
add transcript of silicon salon 2022 talk

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lkcl [Tue, 24 May 2022 14:09:03 +0000 (15:09 +0100)]

2 years agoadd silicon salon 2022 latex source
Luke Kenneth Casson Leighton [Tue, 24 May 2022 12:37:43 +0000 (13:37 +0100)]
add silicon salon 2022 latex source

2 years agoadd ss2022 conference page
Luke Kenneth Casson Leighton [Tue, 24 May 2022 12:05:02 +0000 (13:05 +0100)]
add ss2022 conference page

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2 years agobit-level packing descriptions for crweird family of instructions
Luke Kenneth Casson Leighton [Wed, 18 May 2022 12:18:07 +0000 (13:18 +0100)]
bit-level packing descriptions for crweird family of instructions

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lkcl [Wed, 18 May 2022 12:01:12 +0000 (13:01 +0100)]

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lkcl [Wed, 18 May 2022 11:56:12 +0000 (12:56 +0100)]

2 years agoexplore alternative grevlut in a bit more depth
Luke Kenneth Casson Leighton [Wed, 18 May 2022 11:02:49 +0000 (12:02 +0100)]
explore alternative grevlut in a bit more depth

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lkcl [Wed, 18 May 2022 10:31:07 +0000 (11:31 +0100)]

2 years agoadd bugzilla RFP image
Luke Kenneth Casson Leighton [Wed, 18 May 2022 10:30:33 +0000 (11:30 +0100)]
add bugzilla RFP image

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lkcl [Wed, 18 May 2022 10:30:12 +0000 (11:30 +0100)]

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lkcl [Wed, 18 May 2022 10:07:56 +0000 (11:07 +0100)]

2 years agoHDL_workflow: add task management guidelines
Dmitry Selyutin [Wed, 18 May 2022 09:51:55 +0000 (09:51 +0000)]
HDL_workflow: add task management guidelines

2 years agoghostmansd: update status
Dmitry Selyutin [Wed, 18 May 2022 09:41:02 +0000 (09:41 +0000)]
ghostmansd: update status

2 years agoadd another grevlut form based on what I proposed
Jacob Lifshay [Wed, 18 May 2022 05:25:45 +0000 (22:25 -0700)]
add another grevlut form based on what I proposed
adds xor gates at input/output and has the immediate luts go to
alternating halves -- still is built on just a layer of aoi, no
extra muxes needed in grev matrix.

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lkcl [Tue, 17 May 2022 17:17:41 +0000 (18:17 +0100)]

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lkcl [Tue, 17 May 2022 16:23:17 +0000 (17:23 +0100)]

2 years agoadd first exploration of 4-wide AOI
Luke Kenneth Casson Leighton [Tue, 17 May 2022 11:56:52 +0000 (12:56 +0100)]
add first exploration of 4-wide AOI