Clifford Wolf [Tue, 4 Feb 2014 21:01:53 +0000 (22:01 +0100)]
Added support for inline commands to abc -script
Clifford Wolf [Tue, 4 Feb 2014 15:51:12 +0000 (16:51 +0100)]
presentation progress
Clifford Wolf [Tue, 4 Feb 2014 15:50:13 +0000 (16:50 +0100)]
Added hierarchy -purge_lib option
Clifford Wolf [Tue, 4 Feb 2014 12:43:34 +0000 (13:43 +0100)]
Added test cases for sat command
Clifford Wolf [Tue, 4 Feb 2014 12:34:37 +0000 (13:34 +0100)]
added sat -falsify
Clifford Wolf [Tue, 4 Feb 2014 11:46:16 +0000 (12:46 +0100)]
Fixed bug in sequential sat proofs and improved handling of asserts
Clifford Wolf [Tue, 4 Feb 2014 11:02:47 +0000 (12:02 +0100)]
Improved handling of reg init in opt_share and opt_rmdff
Clifford Wolf [Mon, 3 Feb 2014 23:57:11 +0000 (00:57 +0100)]
presentation progress
Clifford Wolf [Mon, 3 Feb 2014 15:26:27 +0000 (16:26 +0100)]
presentation progress
Clifford Wolf [Mon, 3 Feb 2014 15:26:10 +0000 (16:26 +0100)]
Addred sat option -ignore_unknown_cells
Clifford Wolf [Mon, 3 Feb 2014 12:01:45 +0000 (13:01 +0100)]
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf [Mon, 3 Feb 2014 12:00:55 +0000 (13:00 +0100)]
Replaced isim with xsim in tests/tools/autotest.sh, removed xst support
Clifford Wolf [Sun, 2 Feb 2014 21:41:24 +0000 (22:41 +0100)]
More opt_const -mux_bool features
Clifford Wolf [Sun, 2 Feb 2014 21:26:26 +0000 (22:26 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 21:11:08 +0000 (22:11 +0100)]
Added opt_const -mux_bool
Clifford Wolf [Sun, 2 Feb 2014 20:46:42 +0000 (21:46 +0100)]
Added support for inverter chains to opt_const
Clifford Wolf [Sun, 2 Feb 2014 20:35:26 +0000 (21:35 +0100)]
Added RTLIL::SigSpec::to_single_sigbit()
Clifford Wolf [Sun, 2 Feb 2014 20:27:26 +0000 (21:27 +0100)]
Only generate write-enable $and if WE is not constant 1 in memory_map
Clifford Wolf [Sun, 2 Feb 2014 20:09:08 +0000 (21:09 +0100)]
Added constant-clock case to opt_rmdff
Clifford Wolf [Sun, 2 Feb 2014 16:57:14 +0000 (17:57 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 16:55:32 +0000 (17:55 +0100)]
Added show -notitle option
Clifford Wolf [Sun, 2 Feb 2014 16:11:19 +0000 (17:11 +0100)]
Added delete command
Clifford Wolf [Sun, 2 Feb 2014 15:47:17 +0000 (16:47 +0100)]
Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax
Clifford Wolf [Sun, 2 Feb 2014 12:30:49 +0000 (13:30 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 12:06:28 +0000 (13:06 +0100)]
presentation progress
Clifford Wolf [Sun, 2 Feb 2014 12:06:21 +0000 (13:06 +0100)]
Added support for blanks after -I and -D in read_verilog
Clifford Wolf [Sat, 1 Feb 2014 21:53:27 +0000 (22:53 +0100)]
Fixed a bug in miter command
Clifford Wolf [Sat, 1 Feb 2014 21:52:44 +0000 (22:52 +0100)]
Added sat -show-inputs and -show-outputs
Clifford Wolf [Sat, 1 Feb 2014 17:23:32 +0000 (18:23 +0100)]
Added show -color support for cells and finished show -label implementation
Clifford Wolf [Sat, 1 Feb 2014 16:28:02 +0000 (17:28 +0100)]
Fixed comment/eol parsing in ilang frontend
Clifford Wolf [Sat, 1 Feb 2014 12:50:23 +0000 (13:50 +0100)]
Added constant size expression support of sized constants
Clifford Wolf [Sat, 1 Feb 2014 12:04:49 +0000 (13:04 +0100)]
Added note about SystemVerilog assert statement to README
Clifford Wolf [Sat, 1 Feb 2014 09:35:56 +0000 (10:35 +0100)]
Added miter command
Clifford Wolf [Fri, 31 Jan 2014 11:48:31 +0000 (12:48 +0100)]
Progress on presentation
Clifford Wolf [Fri, 31 Jan 2014 10:21:29 +0000 (11:21 +0100)]
More changes to techlibs/common/simlib.v for LEC
Clifford Wolf [Thu, 30 Jan 2014 14:25:09 +0000 (15:25 +0100)]
presentation progress
Clifford Wolf [Thu, 30 Jan 2014 13:52:46 +0000 (14:52 +0100)]
Bugfix in name resolution with generate blocks
Clifford Wolf [Thu, 30 Jan 2014 11:32:59 +0000 (12:32 +0100)]
Added yosys -H for command list
Clifford Wolf [Wed, 29 Jan 2014 14:56:58 +0000 (15:56 +0100)]
presentation progress
Clifford Wolf [Wed, 29 Jan 2014 11:15:38 +0000 (12:15 +0100)]
presentation progress
Clifford Wolf [Wed, 29 Jan 2014 10:11:10 +0000 (11:11 +0100)]
Tiny change in example script in README
Clifford Wolf [Wed, 29 Jan 2014 10:10:39 +0000 (11:10 +0100)]
Added -h command line option
Clifford Wolf [Wed, 29 Jan 2014 09:51:02 +0000 (10:51 +0100)]
Added test comments to techlibs/cmos/cmos_cells.lib
Clifford Wolf [Wed, 29 Jan 2014 09:50:15 +0000 (10:50 +0100)]
Updated ABC to hg rev
e6b09e1
Clifford Wolf [Tue, 28 Jan 2014 23:59:28 +0000 (00:59 +0100)]
Added read_verilog -icells option
Clifford Wolf [Tue, 28 Jan 2014 23:36:03 +0000 (00:36 +0100)]
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
Clifford Wolf [Tue, 28 Jan 2014 19:28:22 +0000 (20:28 +0100)]
presentation progress
Clifford Wolf [Tue, 28 Jan 2014 05:55:47 +0000 (06:55 +0100)]
Renamed manual/FILES_* directories
Clifford Wolf [Tue, 28 Jan 2014 05:51:50 +0000 (06:51 +0100)]
Progress on presentation
Clifford Wolf [Mon, 27 Jan 2014 19:42:35 +0000 (20:42 +0100)]
Progress on presentation
Clifford Wolf [Mon, 27 Jan 2014 16:08:19 +0000 (17:08 +0100)]
Added first presentation slides
Clifford Wolf [Sun, 26 Jan 2014 01:29:19 +0000 (02:29 +0100)]
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys
Clifford Wolf [Sun, 26 Jan 2014 01:28:17 +0000 (17:28 -0800)]
Merge pull request #21 from hansiglaser/master
beautified write_intersynth, enabled multiple "-map" for the extract pass
Johann Glaser [Sat, 25 Jan 2014 20:11:34 +0000 (21:11 +0100)]
enabled multiple "-map" for the extract pass
Johann Glaser [Sat, 25 Jan 2014 19:16:38 +0000 (20:16 +0100)]
beautified write_intersynth
Ahmed Irfan [Sat, 25 Jan 2014 18:33:24 +0000 (19:33 +0100)]
root bug corrected
Clifford Wolf [Sat, 25 Jan 2014 05:32:16 +0000 (06:32 +0100)]
Added support for // comments in liberty parser
Clifford Wolf [Fri, 24 Jan 2014 22:44:46 +0000 (23:44 +0100)]
Merge branch 'btor'
Ahmed Irfan [Fri, 24 Jan 2014 17:04:37 +0000 (18:04 +0100)]
removed regex include
Ahmed Irfan [Fri, 24 Jan 2014 16:35:42 +0000 (17:35 +0100)]
merged clifford changes + removed regex
Clifford Wolf [Fri, 24 Jan 2014 14:52:16 +0000 (15:52 +0100)]
Use techmap -share_map in btor scripts
Clifford Wolf [Fri, 24 Jan 2014 14:48:07 +0000 (15:48 +0100)]
Moved btor scripts to backends/btor/
Clifford Wolf [Fri, 24 Jan 2014 14:47:09 +0000 (15:47 +0100)]
Restored Makefile
Clifford Wolf [Fri, 24 Jan 2014 14:46:41 +0000 (15:46 +0100)]
Restored IdString::check()
Clifford Wolf [Fri, 24 Jan 2014 14:43:42 +0000 (15:43 +0100)]
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor
Clifford Wolf [Fri, 24 Jan 2014 14:05:24 +0000 (15:05 +0100)]
Fixed handling of unsized constants in verilog frontend
Ahmed Irfan [Fri, 24 Jan 2014 14:00:43 +0000 (15:00 +0100)]
minor change in script
Ahmed Irfan [Wed, 22 Jan 2014 09:45:21 +0000 (10:45 +0100)]
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Clifford Wolf [Mon, 20 Jan 2014 19:25:20 +0000 (20:25 +0100)]
Fixed algorithmic complexity of AST simplification of long expressions
Ahmed Irfan [Mon, 20 Jan 2014 17:35:52 +0000 (18:35 +0100)]
slice bug corrected
Ahmed Irfan [Mon, 20 Jan 2014 09:45:02 +0000 (10:45 +0100)]
assert feature
Ahmed Irfan [Mon, 20 Jan 2014 08:58:04 +0000 (09:58 +0100)]
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Clifford Wolf [Sun, 19 Jan 2014 20:58:58 +0000 (21:58 +0100)]
Added hilomap command
Clifford Wolf [Sun, 19 Jan 2014 14:38:23 +0000 (15:38 +0100)]
Added sat -tempinduc and sat -prove-asserts
Clifford Wolf [Sun, 19 Jan 2014 14:37:56 +0000 (15:37 +0100)]
Added $assert support to satgen
Clifford Wolf [Sun, 19 Jan 2014 13:03:40 +0000 (14:03 +0100)]
Added $assert cell
Clifford Wolf [Sun, 19 Jan 2014 03:18:22 +0000 (04:18 +0100)]
Added Verilog parser support for asserts
Ahmed Irfan [Sat, 18 Jan 2014 20:54:52 +0000 (21:54 +0100)]
script added
Ahmed Irfan [Sat, 18 Jan 2014 18:45:16 +0000 (19:45 +0100)]
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Clifford Wolf [Sat, 18 Jan 2014 18:27:16 +0000 (19:27 +0100)]
Fixed $lut simlib model for a wider range of tools
Clifford Wolf [Sat, 18 Jan 2014 18:22:20 +0000 (19:22 +0100)]
Fixed parsing of verilog macros at end of line
Clifford Wolf [Sat, 18 Jan 2014 18:13:43 +0000 (19:13 +0100)]
More changes to simlib to make it friendlier to a wider range of tools
Clifford Wolf [Sat, 18 Jan 2014 17:54:50 +0000 (18:54 +0100)]
Fixed a type in $mem model in simlib.v
Ahmed Irfan [Sat, 18 Jan 2014 17:11:26 +0000 (18:11 +0100)]
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys
Ahmed Irfan [Sat, 18 Jan 2014 17:10:31 +0000 (18:10 +0100)]
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Ahmed Irfan [Sat, 18 Jan 2014 16:29:55 +0000 (17:29 +0100)]
pmux2mux
Clifford Wolf [Sat, 18 Jan 2014 14:36:17 +0000 (15:36 +0100)]
Removed cases of trailing comma in stdcells.v
Clifford Wolf [Sat, 18 Jan 2014 14:35:15 +0000 (15:35 +0100)]
Added $bu0 cell to simlib.v
Clifford Wolf [Sat, 18 Jan 2014 01:56:36 +0000 (02:56 +0100)]
Improved setundef random number generator
Clifford Wolf [Fri, 17 Jan 2014 22:14:36 +0000 (23:14 +0100)]
Added setundef command
Clifford Wolf [Fri, 17 Jan 2014 22:14:17 +0000 (23:14 +0100)]
Some improvements in log_dump_val_worker() templates
Clifford Wolf [Fri, 17 Jan 2014 19:06:15 +0000 (20:06 +0100)]
Added techlibs/common/pmux2mux.v
Ahmed Irfan [Fri, 17 Jan 2014 18:32:35 +0000 (19:32 +0100)]
verilog default options pull
shift operator width issues
Ahmed Irfan [Fri, 17 Jan 2014 18:07:41 +0000 (19:07 +0100)]
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan [Fri, 17 Jan 2014 18:07:05 +0000 (10:07 -0800)]
Merge pull request #4 from cliffordwolf/master
verilog defaults
Clifford Wolf [Fri, 17 Jan 2014 16:22:29 +0000 (17:22 +0100)]
Added verilog_defaults command
Clifford Wolf [Fri, 17 Jan 2014 15:42:40 +0000 (16:42 +0100)]
Added support for $adff with undef data inputs to opt_rmdff
Clifford Wolf [Fri, 17 Jan 2014 15:34:50 +0000 (16:34 +0100)]
Added select -assert-none and -assert-any
Ahmed Irfan [Fri, 17 Jan 2014 09:50:59 +0000 (10:50 +0100)]
Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan [Fri, 17 Jan 2014 09:48:55 +0000 (01:48 -0800)]
Merge pull request #3 from cliffordwolf/master
memory_unpack
projects / yosys.git / log