yosys.git
5 years agoSafe side: all flops have different mergeability class
Eddie Hung [Tue, 2 Jul 2019 19:21:03 +0000 (12:21 -0700)]
Safe side: all flops have different mergeability class

5 years agoRefactor and cope with new abc_flop format
Eddie Hung [Mon, 1 Jul 2019 18:50:34 +0000 (11:50 -0700)]
Refactor and cope with new abc_flop format

5 years agoCapture all data in one "abc_flop" attribute
Eddie Hung [Mon, 1 Jul 2019 18:50:14 +0000 (11:50 -0700)]
Capture all data in one "abc_flop" attribute

5 years agoFix spacing
Eddie Hung [Mon, 1 Jul 2019 18:10:44 +0000 (11:10 -0700)]
Fix spacing

5 years agoAlso remove $__ABC_FF_
Eddie Hung [Mon, 1 Jul 2019 17:55:24 +0000 (10:55 -0700)]
Also remove $__ABC_FF_

5 years agoUpdate abc_box_id numbering
Eddie Hung [Mon, 1 Jul 2019 17:47:14 +0000 (10:47 -0700)]
Update abc_box_id numbering

5 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Mon, 1 Jul 2019 17:44:42 +0000 (10:44 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_dff

5 years agoMove abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG
Eddie Hung [Mon, 1 Jul 2019 16:44:53 +0000 (09:44 -0700)]
Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG

5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Mon, 1 Jul 2019 16:43:33 +0000 (09:43 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoinstall *_nowide.lut files
Eddie Hung [Sun, 30 Jun 2019 02:37:04 +0000 (19:37 -0700)]
install *_nowide.lut files

5 years agoMerge pull request #1149 from gsomlo/gls-1098-abcext-fixup
Eddie Hung [Fri, 28 Jun 2019 22:02:50 +0000 (15:02 -0700)]
Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup

Make abc9 pass aware of optional ABCEXTERNAL override

5 years agoautotest.sh to define _AUTOTB when test_autotb
Eddie Hung [Fri, 28 Jun 2019 21:18:56 +0000 (14:18 -0700)]
autotest.sh to define _AUTOTB when test_autotb

5 years agoReplace log_assert() with meaningful log_error()
Eddie Hung [Fri, 28 Jun 2019 18:28:29 +0000 (11:28 -0700)]
Replace log_assert() with meaningful log_error()

5 years agoRemove peepopt call in synth_xilinx since already in synth -run coarse
Eddie Hung [Fri, 28 Jun 2019 19:53:38 +0000 (12:53 -0700)]
Remove peepopt call in synth_xilinx since already in synth -run coarse

5 years agoMake abc9 pass aware of optional ABCEXTERNAL override
Gabriel L. Somlo [Fri, 28 Jun 2019 18:54:58 +0000 (14:54 -0400)]
Make abc9 pass aware of optional ABCEXTERNAL override

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agoAdd missing CHANGELOG entries
Eddie Hung [Fri, 28 Jun 2019 18:16:15 +0000 (11:16 -0700)]
Add missing CHANGELOG entries

5 years agoFix spacing
Eddie Hung [Fri, 28 Jun 2019 18:10:36 +0000 (11:10 -0700)]
Fix spacing

5 years agoMerge pull request #1098 from YosysHQ/xaig
Eddie Hung [Fri, 28 Jun 2019 17:59:03 +0000 (10:59 -0700)]
Merge pull request #1098 from YosysHQ/xaig

"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)

5 years agoAdd generic __builtin_bswap32 function
Eddie Hung [Fri, 28 Jun 2019 16:59:47 +0000 (09:59 -0700)]
Add generic __builtin_bswap32 function

5 years agoAlso fix write_aiger for UB
Eddie Hung [Fri, 28 Jun 2019 16:55:07 +0000 (09:55 -0700)]
Also fix write_aiger for UB

5 years agoFix more potential for undefined behaviour due to container invalidation
Eddie Hung [Fri, 28 Jun 2019 16:51:43 +0000 (09:51 -0700)]
Fix more potential for undefined behaviour due to container invalidation

5 years agoUpdate synth_ice40 -device doc to be relevant for -abc9 only
Eddie Hung [Fri, 28 Jun 2019 16:49:01 +0000 (09:49 -0700)]
Update synth_ice40 -device doc to be relevant for -abc9 only

5 years agoDisable boxing of ECP5 dist RAM due to regression
Eddie Hung [Fri, 28 Jun 2019 16:46:36 +0000 (09:46 -0700)]
Disable boxing of ECP5 dist RAM due to regression

5 years agoAdd write address to abc_scc_break of ECP5 dist RAM
Eddie Hung [Fri, 28 Jun 2019 16:45:48 +0000 (09:45 -0700)]
Add write address to abc_scc_break of ECP5 dist RAM

5 years agoFix DO4 typo
Eddie Hung [Fri, 28 Jun 2019 16:45:40 +0000 (09:45 -0700)]
Fix DO4 typo

5 years agoMerge pull request #1146 from gsomlo/gls-test-abc-ext
Clifford Wolf [Fri, 28 Jun 2019 08:30:31 +0000 (10:30 +0200)]
Merge pull request #1146 from gsomlo/gls-test-abc-ext

tests: use optional ABCEXTERNAL when specified

5 years agoMerge pull request #1046 from bogdanvuk/master
Clifford Wolf [Fri, 28 Jun 2019 06:30:18 +0000 (08:30 +0200)]
Merge pull request #1046 from bogdanvuk/master

Optimizing DFFs whose initial value prevents their value from changing

5 years agotests: use optional ABCEXTERNAL when specified
Gabriel L. Somlo [Fri, 28 Jun 2019 02:54:09 +0000 (22:54 -0400)]
tests: use optional ABCEXTERNAL when specified

Commits 65924fd1abc40924, and ebe29b66 hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agoReduce diff with upstream
Eddie Hung [Thu, 27 Jun 2019 23:13:22 +0000 (16:13 -0700)]
Reduce diff with upstream

5 years agoExtraneous newline
Eddie Hung [Thu, 27 Jun 2019 23:12:20 +0000 (16:12 -0700)]
Extraneous newline

5 years agoRemove noise from ice40/cells_sim.v
Eddie Hung [Thu, 27 Jun 2019 23:11:39 +0000 (16:11 -0700)]
Remove noise from ice40/cells_sim.v

5 years agoRefactor for one "abc_carry" attribute on module
Eddie Hung [Thu, 27 Jun 2019 23:07:14 +0000 (16:07 -0700)]
Refactor for one "abc_carry" attribute on module

5 years agoMerge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Thu, 27 Jun 2019 22:30:00 +0000 (15:30 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig

5 years agoDo not use Module::remove() iterator version
Eddie Hung [Thu, 27 Jun 2019 22:29:20 +0000 (15:29 -0700)]
Do not use Module::remove() iterator version

5 years agoRemove redundant doc
Eddie Hung [Thu, 27 Jun 2019 22:28:55 +0000 (15:28 -0700)]
Remove redundant doc

5 years agoRemove &retime when abc9 -fast
Eddie Hung [Thu, 27 Jun 2019 22:17:39 +0000 (15:17 -0700)]
Remove &retime when abc9 -fast

5 years agoCleanup abc9.cc
Eddie Hung [Thu, 27 Jun 2019 22:15:56 +0000 (15:15 -0700)]
Cleanup abc9.cc

5 years agoUndo iterator based Module::remove() for cells, as containers will not
Eddie Hung [Thu, 27 Jun 2019 22:03:21 +0000 (15:03 -0700)]
Undo iterator based Module::remove() for cells, as containers will not
invalidate

5 years agoAdd help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too
Bogdan Vukobratovic [Thu, 27 Jun 2019 20:06:23 +0000 (22:06 +0200)]
Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too

5 years agoFix memory leak when one of multiple DFF cells is removed in opt_rmdff
Bogdan Vukobratovic [Thu, 27 Jun 2019 20:02:12 +0000 (22:02 +0200)]
Fix memory leak when one of multiple DFF cells is removed in opt_rmdff

When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Thu, 27 Jun 2019 19:53:23 +0000 (12:53 -0700)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agoMerge pull request #1139 from YosysHQ/dave/check-sim-iverilog
Eddie Hung [Thu, 27 Jun 2019 19:31:15 +0000 (12:31 -0700)]
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog

tests: Check that Icarus can parse arch sim models

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Thu, 27 Jun 2019 18:54:34 +0000 (11:54 -0700)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agoGrr
Eddie Hung [Thu, 27 Jun 2019 18:53:42 +0000 (11:53 -0700)]
Grr

5 years agoCapitalisation
Eddie Hung [Thu, 27 Jun 2019 18:26:44 +0000 (11:26 -0700)]
Capitalisation

5 years agoMake CHANGELOG clearer
Eddie Hung [Thu, 27 Jun 2019 18:25:57 +0000 (11:25 -0700)]
Make CHANGELOG clearer

5 years agoMerge pull request #1143 from YosysHQ/clifford/fix1135
Eddie Hung [Thu, 27 Jun 2019 18:48:48 +0000 (11:48 -0700)]
Merge pull request #1143 from YosysHQ/clifford/fix1135

Add "pmux2shiftx -norange"

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Thu, 27 Jun 2019 18:31:19 +0000 (11:31 -0700)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agoAdd warning if synth_xilinx -abc9 with family != xc7
Eddie Hung [Thu, 27 Jun 2019 18:22:49 +0000 (11:22 -0700)]
Add warning if synth_xilinx -abc9 with family != xc7

5 years agoRemove unneeded include
Eddie Hung [Thu, 27 Jun 2019 18:20:40 +0000 (11:20 -0700)]
Remove unneeded include

5 years agoMerge origin/master
Eddie Hung [Thu, 27 Jun 2019 18:20:15 +0000 (11:20 -0700)]
Merge origin/master

5 years agoAdd simcells.v, simlib.v, and some output
Eddie Hung [Thu, 27 Jun 2019 18:13:49 +0000 (11:13 -0700)]
Add simcells.v, simlib.v, and some output

5 years agoAdd #1135 testcase
Eddie Hung [Thu, 27 Jun 2019 18:02:52 +0000 (11:02 -0700)]
Add #1135 testcase

5 years agosynth_xilinx -arch -> -family, consistent with older synth_intel
Eddie Hung [Thu, 27 Jun 2019 14:24:47 +0000 (07:24 -0700)]
synth_xilinx -arch -> -family, consistent with older synth_intel

5 years agoMerge pull request #1142 from YosysHQ/clifford/fix1132
Eddie Hung [Thu, 27 Jun 2019 14:21:31 +0000 (07:21 -0700)]
Merge pull request #1142 from YosysHQ/clifford/fix1132

Fix handling of partial covers in muxcover

5 years agoMerge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux
Eddie Hung [Thu, 27 Jun 2019 13:04:56 +0000 (06:04 -0700)]
Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux

synth_xilinx: Add -nocarry and -nowidelut options

5 years agoCopy tests from eddie/fix1132
Eddie Hung [Thu, 27 Jun 2019 13:01:50 +0000 (06:01 -0700)]
Copy tests from eddie/fix1132

5 years agoMerge remote-tracking branch 'upstream/master'
Bogdan Vukobratovic [Thu, 27 Jun 2019 10:11:47 +0000 (12:11 +0200)]
Merge remote-tracking branch 'upstream/master'

5 years agoAdd "pmux2shiftx -norange", fixes #1135
Clifford Wolf [Thu, 27 Jun 2019 08:59:12 +0000 (10:59 +0200)]
Add "pmux2shiftx -norange", fixes #1135

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix handling of partial covers in muxcover, fixes #1132
Clifford Wolf [Thu, 27 Jun 2019 07:42:49 +0000 (09:42 +0200)]
Fix handling of partial covers in muxcover, fixes #1132

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix spacing
Eddie Hung [Thu, 27 Jun 2019 03:03:34 +0000 (20:03 -0700)]
Fix spacing

5 years agoImprove debugging message for comb loops
Eddie Hung [Thu, 27 Jun 2019 03:02:38 +0000 (20:02 -0700)]
Improve debugging message for comb loops

5 years agoAdd WE to ECP5 dist RAM's abc_scc_break too
Eddie Hung [Thu, 27 Jun 2019 03:02:19 +0000 (20:02 -0700)]
Add WE to ECP5 dist RAM's abc_scc_break too

5 years agoUpdate comment on boxes
Eddie Hung [Thu, 27 Jun 2019 03:00:15 +0000 (20:00 -0700)]
Update comment on boxes

5 years agoAdd "WE" to dist RAM's abc_scc_break
Eddie Hung [Thu, 27 Jun 2019 02:58:09 +0000 (19:58 -0700)]
Add "WE" to dist RAM's abc_scc_break

5 years agoSupport more than one port in the abc_scc_break attr
Eddie Hung [Thu, 27 Jun 2019 02:57:54 +0000 (19:57 -0700)]
Support more than one port in the abc_scc_break attr

5 years agoAdd write_xaiger into CHANGELOG
Eddie Hung [Thu, 27 Jun 2019 02:17:11 +0000 (19:17 -0700)]
Add write_xaiger into CHANGELOG

5 years agoMerge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung [Wed, 26 Jun 2019 17:47:53 +0000 (10:47 -0700)]
Merge branch 'koriakin/xc7nocarrymux' into xaig

5 years agoGrrr
Eddie Hung [Wed, 26 Jun 2019 17:47:03 +0000 (10:47 -0700)]
Grrr

5 years agotests: Check that Icarus can parse arch sim models
David Shah [Wed, 26 Jun 2019 17:17:52 +0000 (18:17 +0100)]
tests: Check that Icarus can parse arch sim models

Signed-off-by: David Shah <dave@ds0.me>
5 years agoRemove unused var
Eddie Hung [Wed, 26 Jun 2019 17:33:07 +0000 (10:33 -0700)]
Remove unused var

5 years agoAdd _nowide variants of LUT libraries in -nowidelut flows
Eddie Hung [Wed, 26 Jun 2019 17:23:29 +0000 (10:23 -0700)]
Add _nowide variants of LUT libraries in -nowidelut flows

5 years agoMerge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Wed, 26 Jun 2019 17:10:16 +0000 (10:10 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig

5 years agoMerge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung [Wed, 26 Jun 2019 17:09:59 +0000 (10:09 -0700)]
Merge branch 'koriakin/xc7nocarrymux' into xaig

5 years agoFix spacing
Eddie Hung [Wed, 26 Jun 2019 17:09:18 +0000 (10:09 -0700)]
Fix spacing

5 years agoMerge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung [Wed, 26 Jun 2019 17:08:40 +0000 (10:08 -0700)]
Merge branch 'koriakin/xc7nocarrymux' into xaig

5 years agoOops. Actually use nocarry flag as spotted by @koriakin
Eddie Hung [Wed, 26 Jun 2019 17:06:33 +0000 (10:06 -0700)]
Oops. Actually use nocarry flag as spotted by @koriakin

5 years agoMerge pull request #1137 from mmicko/cell_sim_fix
Clifford Wolf [Wed, 26 Jun 2019 17:06:10 +0000 (19:06 +0200)]
Merge pull request #1137 from mmicko/cell_sim_fix

Simulation model verilog fix

5 years agoMerge branch 'koriakin/xc7nocarrymux' into xaig
Eddie Hung [Wed, 26 Jun 2019 17:04:01 +0000 (10:04 -0700)]
Merge branch 'koriakin/xc7nocarrymux' into xaig

5 years agoSimulation model verilog fix
Miodrag Milanovic [Wed, 26 Jun 2019 16:34:34 +0000 (18:34 +0200)]
Simulation model verilog fix

5 years agosynth_ecp5 rename -nomux to -nowidelut, but preserve former
Eddie Hung [Wed, 26 Jun 2019 16:33:48 +0000 (09:33 -0700)]
synth_ecp5 rename -nomux to -nowidelut, but preserve former

5 years agoMerge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7no...
Eddie Hung [Wed, 26 Jun 2019 16:33:38 +0000 (09:33 -0700)]
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux

5 years agoImprove opt_clean handling of unused public wires
Clifford Wolf [Wed, 26 Jun 2019 15:54:17 +0000 (17:54 +0200)]
Improve opt_clean handling of unused public wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1136 from YosysHQ/xaig_ice40_wire_del
Eddie Hung [Wed, 26 Jun 2019 15:51:11 +0000 (08:51 -0700)]
Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del

abc9: Add wire delays to synth_ice40

5 years agoImprove BTOR2 handling of undriven wires
Clifford Wolf [Wed, 26 Jun 2019 15:42:00 +0000 (17:42 +0200)]
Improve BTOR2 handling of undriven wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoabc9: Add wire delays to synth_ice40
David Shah [Wed, 26 Jun 2019 10:39:44 +0000 (11:39 +0100)]
abc9: Add wire delays to synth_ice40

Signed-off-by: David Shah <dave@ds0.me>
5 years agoFix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
Clifford Wolf [Wed, 26 Jun 2019 09:09:43 +0000 (11:09 +0200)]
Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoDo not clean up buffer cells with "keep" attribute, closes #1128
Clifford Wolf [Wed, 26 Jun 2019 09:00:44 +0000 (11:00 +0200)]
Do not clean up buffer cells with "keep" attribute, closes #1128

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoEscape scope names starting with dollar sign in smtio.py
Clifford Wolf [Wed, 26 Jun 2019 08:58:39 +0000 (10:58 +0200)]
Escape scope names starting with dollar sign in smtio.py

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd more ECP5 Diamond flip-flops.
whitequark [Tue, 25 Jun 2019 16:37:36 +0000 (16:37 +0000)]
Add more ECP5 Diamond flip-flops.

This includes all I/O registers, and a few more regular FFs where it
was convenient.

5 years agoMissing muxpack.o in Makefile
Eddie Hung [Tue, 25 Jun 2019 17:38:42 +0000 (10:38 -0700)]
Missing muxpack.o in Makefile

5 years agoRealistic delays for RAM32X1D too
Eddie Hung [Tue, 25 Jun 2019 06:05:28 +0000 (23:05 -0700)]
Realistic delays for RAM32X1D too

5 years agoAdd RAM32X1D box info
Eddie Hung [Tue, 25 Jun 2019 05:54:35 +0000 (22:54 -0700)]
Add RAM32X1D box info

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Tue, 25 Jun 2019 16:33:11 +0000 (09:33 -0700)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agoAdd testcase from #335, fixed by #1130
Eddie Hung [Tue, 25 Jun 2019 15:43:58 +0000 (08:43 -0700)]
Add testcase from #335, fixed by #1130

5 years agoMerge pull request #1130 from YosysHQ/eddie/fix710
Clifford Wolf [Tue, 25 Jun 2019 15:34:44 +0000 (17:34 +0200)]
Merge pull request #1130 from YosysHQ/eddie/fix710

memory_dff: walk through more than one mux for computing read enable

5 years agoFix spacing
Eddie Hung [Tue, 25 Jun 2019 15:33:17 +0000 (08:33 -0700)]
Fix spacing

5 years agoMove only one consumer check outside of while loop
Eddie Hung [Tue, 25 Jun 2019 15:29:55 +0000 (08:29 -0700)]
Move only one consumer check outside of while loop

5 years agoMerge pull request #1129 from YosysHQ/eddie/ram32x1d
Eddie Hung [Tue, 25 Jun 2019 15:22:57 +0000 (08:22 -0700)]
Merge pull request #1129 from YosysHQ/eddie/ram32x1d

Add RAM32X1D support

5 years agoMerge pull request #1075 from YosysHQ/eddie/muxpack
Clifford Wolf [Tue, 25 Jun 2019 15:21:59 +0000 (17:21 +0200)]
Merge pull request #1075 from YosysHQ/eddie/muxpack

Add new "muxpack" command for packing chains of $mux cells