yosys.git
5 years agowrite_verilog: write RTLIL::Sa aka - as Verilog ?.
whitequark [Tue, 9 Jul 2019 18:30:24 +0000 (18:30 +0000)]
write_verilog: write RTLIL::Sa aka - as Verilog ?.

Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.

5 years agoMerge pull request #1168 from whitequark/bugpoint-processes
Clifford Wolf [Tue, 9 Jul 2019 14:59:43 +0000 (16:59 +0200)]
Merge pull request #1168 from whitequark/bugpoint-processes

Add support for processes in bugpoint

5 years agoMerge pull request #1169 from whitequark/more-proc-cleanups
Clifford Wolf [Tue, 9 Jul 2019 14:59:18 +0000 (16:59 +0200)]
Merge pull request #1169 from whitequark/more-proc-cleanups

A new proc_prune pass

5 years agoMerge pull request #1163 from whitequark/more-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:57:16 +0000 (16:57 +0200)]
Merge pull request #1163 from whitequark/more-case-attrs

More support for case rule attributes

5 years agoMerge pull request #1162 from whitequark/rtlil-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:56:29 +0000 (16:56 +0200)]
Merge pull request #1162 from whitequark/rtlil-case-attrs

Allow attributes on individual switch cases in RTLIL

5 years agoMerge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
Clifford Wolf [Tue, 9 Jul 2019 14:49:08 +0000 (16:49 +0200)]
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup

Cleanup synth_xilinx SRL inference, make more consistent

5 years agoproc_prune: promote assigns to module connections when legal.
whitequark [Tue, 9 Jul 2019 08:14:52 +0000 (08:14 +0000)]
proc_prune: promote assigns to module connections when legal.

This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)

5 years agoproc_prune: new pass.
whitequark [Mon, 8 Jul 2019 15:19:01 +0000 (15:19 +0000)]
proc_prune: new pass.

The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.

5 years agobugpoint: add -assigns and -updates options.
whitequark [Tue, 9 Jul 2019 09:08:38 +0000 (09:08 +0000)]
bugpoint: add -assigns and -updates options.

5 years agoproc_clean: add -quiet option.
whitequark [Tue, 9 Jul 2019 08:57:57 +0000 (08:57 +0000)]
proc_clean: add -quiet option.

This is useful for other passes that call it often, like bugpoint.

5 years agoMerge pull request #1166 from YosysHQ/eddie/synth_keepdc
Eddie Hung [Tue, 9 Jul 2019 04:43:16 +0000 (21:43 -0700)]
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc

Add "synth -keepdc" option

5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Tue, 9 Jul 2019 02:26:43 +0000 (19:26 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoClarify script -scriptwire doc
Eddie Hung [Tue, 9 Jul 2019 02:21:21 +0000 (19:21 -0700)]
Clarify script -scriptwire doc

5 years agoAdd synth -keepdc to CHANGELOG
Eddie Hung [Tue, 9 Jul 2019 02:15:37 +0000 (19:15 -0700)]
Add synth -keepdc to CHANGELOG

5 years agoClarify 'wreduce -keepdc' doc
Eddie Hung [Tue, 9 Jul 2019 02:15:07 +0000 (19:15 -0700)]
Clarify 'wreduce -keepdc' doc

5 years agoAdd synth -keepdc option
Eddie Hung [Tue, 9 Jul 2019 02:14:54 +0000 (19:14 -0700)]
Add synth -keepdc option

5 years agoMerge pull request #1164 from YosysHQ/eddie/muxcover_mux2
Eddie Hung [Mon, 8 Jul 2019 21:34:37 +0000 (14:34 -0700)]
Merge pull request #1164 from YosysHQ/eddie/muxcover_mux2

Add muxcover -mux2=cost option

5 years agoMerge pull request #1160 from ZirconiumX/cyclone_v
David Shah [Mon, 8 Jul 2019 20:04:33 +0000 (21:04 +0100)]
Merge pull request #1160 from ZirconiumX/cyclone_v

synth_intel: Warn about untested Quartus backend

5 years agoUpdate muxcover doc as per @ZirconiumX
Eddie Hung [Mon, 8 Jul 2019 19:50:59 +0000 (12:50 -0700)]
Update muxcover doc as per @ZirconiumX

5 years agoatoi -> stoi
Eddie Hung [Mon, 8 Jul 2019 18:00:06 +0000 (11:00 -0700)]
atoi -> stoi

5 years agoAdd muxcover -mux2=cost option
Eddie Hung [Mon, 8 Jul 2019 17:59:12 +0000 (10:59 -0700)]
Add muxcover -mux2=cost option

5 years agoverilog_backend: dump attributes on SwitchRule.
whitequark [Mon, 8 Jul 2019 15:11:29 +0000 (15:11 +0000)]
verilog_backend: dump attributes on SwitchRule.

This appears to be an omission.

5 years agoproc_mux: consider \src attribute on CaseRule.
whitequark [Mon, 8 Jul 2019 13:18:18 +0000 (13:18 +0000)]
proc_mux: consider \src attribute on CaseRule.

5 years agoverilog_backend: dump attributes on CaseRule, as comments.
whitequark [Mon, 8 Jul 2019 12:48:50 +0000 (12:48 +0000)]
verilog_backend: dump attributes on CaseRule, as comments.

Attributes are not permitted in that position by Verilog grammar.

5 years agogenrtlil: emit \src attribute on CaseRule.
whitequark [Mon, 8 Jul 2019 12:29:08 +0000 (12:29 +0000)]
genrtlil: emit \src attribute on CaseRule.

5 years agoAllow attributes on individual switch cases in RTLIL.
whitequark [Mon, 8 Jul 2019 11:34:58 +0000 (11:34 +0000)]
Allow attributes on individual switch cases in RTLIL.

The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.

5 years agosynth_intel: Warn about untested Quartus backend
Dan Ravensloft [Sun, 7 Jul 2019 15:00:38 +0000 (16:00 +0100)]
synth_intel: Warn about untested Quartus backend

5 years agoMerge pull request #1159 from btut/fix/1090_segfault_cell_and_wire
Clifford Wolf [Fri, 5 Jul 2019 09:57:41 +0000 (11:57 +0200)]
Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire

Throw runtime exception when trying to convert inexistend C++ object to Python

5 years agoThrow runtime exception when trying to convert a c++-pointer to a
Benedikt Tutzer [Thu, 4 Jul 2019 12:20:13 +0000 (14:20 +0200)]
Throw runtime exception when trying to convert a c++-pointer to a
python-object in case the pointer is a nullptr to avoid a segfault.

Fixes #1090

5 years agoMerge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
Eddie Hung [Wed, 3 Jul 2019 16:43:00 +0000 (09:43 -0700)]
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell

 write_xaiger to treat unknown cell connections as keep-s

5 years agoMerge pull request #1147 from YosysHQ/clifford/fix1144
Clifford Wolf [Wed, 3 Jul 2019 10:30:37 +0000 (12:30 +0200)]
Merge pull request #1147 from YosysHQ/clifford/fix1144

Improve specify dummy parser

5 years agoFix tests/various/specify.v
Clifford Wolf [Wed, 3 Jul 2019 09:25:05 +0000 (11:25 +0200)]
Fix tests/various/specify.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoSome cleanups in "ignore specify parser"
Clifford Wolf [Wed, 3 Jul 2019 09:22:10 +0000 (11:22 +0200)]
Some cleanups in "ignore specify parser"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1154 from whitequark/manual-sync-always
Clifford Wolf [Wed, 3 Jul 2019 08:45:29 +0000 (10:45 +0200)]
Merge pull request #1154 from whitequark/manual-sync-always

manual: explain the purpose of `sync always`

5 years agowrite_xaiger to treat unknown cell connections as keep-s
Eddie Hung [Wed, 3 Jul 2019 02:14:30 +0000 (19:14 -0700)]
write_xaiger to treat unknown cell connections as keep-s

5 years agoAdd test
Eddie Hung [Wed, 3 Jul 2019 02:13:40 +0000 (19:13 -0700)]
Add test

5 years agoMerge pull request #1150 from YosysHQ/eddie/script_from_wire
Eddie Hung [Tue, 2 Jul 2019 17:20:42 +0000 (10:20 -0700)]
Merge pull request #1150 from YosysHQ/eddie/script_from_wire

Add "script -select [selection]" to allow commands to be taken from wires

5 years agomanual: explain the purpose of `sync always`.
whitequark [Tue, 2 Jul 2019 17:10:13 +0000 (17:10 +0000)]
manual: explain the purpose of `sync always`.

5 years agoMerge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup
Eddie Hung [Tue, 2 Jul 2019 16:21:02 +0000 (09:21 -0700)]
Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup

5 years agoMerge pull request #1153 from YosysHQ/dave/fix_multi_mux
David Shah [Tue, 2 Jul 2019 15:47:54 +0000 (16:47 +0100)]
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux

memory_dff: Fix checking of feedback mux input when more than one mux

5 years agoUpdate test for Pass::call_on_module()
Eddie Hung [Tue, 2 Jul 2019 15:22:31 +0000 (08:22 -0700)]
Update test for Pass::call_on_module()

5 years agoUse Pass::call_on_module() as per @cliffordwolf comments
Eddie Hung [Tue, 2 Jul 2019 15:20:37 +0000 (08:20 -0700)]
Use Pass::call_on_module() as per @cliffordwolf comments

5 years agoUpdate test too
Eddie Hung [Tue, 2 Jul 2019 15:19:23 +0000 (08:19 -0700)]
Update test too

5 years agoscript -select -> script -scriptwire
Eddie Hung [Tue, 2 Jul 2019 15:17:26 +0000 (08:17 -0700)]
script -select -> script -scriptwire

5 years agomemory_dff: Fix checking of feedback mux input when more than one mux
David Shah [Tue, 2 Jul 2019 12:27:37 +0000 (13:27 +0100)]
memory_dff: Fix checking of feedback mux input when more than one mux

Signed-off-by: David Shah <dave@ds0.me>
5 years agoFix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
Clifford Wolf [Tue, 2 Jul 2019 09:36:26 +0000 (11:36 +0200)]
Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoSpace
Eddie Hung [Mon, 1 Jul 2019 18:59:10 +0000 (11:59 -0700)]
Space

5 years agoMove CHANGELOG entry from yosys-0.8 to 0.9
Eddie Hung [Mon, 1 Jul 2019 16:46:56 +0000 (09:46 -0700)]
Move CHANGELOG entry from yosys-0.8 to 0.9

5 years agoMerge branch 'master' into eddie/script_from_wire
Eddie Hung [Mon, 1 Jul 2019 16:46:32 +0000 (09:46 -0700)]
Merge branch 'master' into eddie/script_from_wire

5 years agoMove abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG
Eddie Hung [Mon, 1 Jul 2019 16:44:53 +0000 (09:44 -0700)]
Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG

5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Mon, 1 Jul 2019 16:43:33 +0000 (09:43 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoComment out invalid syntax
Eddie Hung [Sun, 30 Jun 2019 18:48:01 +0000 (11:48 -0700)]
Comment out invalid syntax

5 years agoCleanup SRL inference/make more consistent
Eddie Hung [Sun, 30 Jun 2019 04:42:20 +0000 (21:42 -0700)]
Cleanup SRL inference/make more consistent

5 years agoinstall *_nowide.lut files
Eddie Hung [Sun, 30 Jun 2019 02:37:04 +0000 (19:37 -0700)]
install *_nowide.lut files

5 years agoMerge pull request #1149 from gsomlo/gls-1098-abcext-fixup
Eddie Hung [Fri, 28 Jun 2019 22:02:50 +0000 (15:02 -0700)]
Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup

Make abc9 pass aware of optional ABCEXTERNAL override

5 years agoMerge branch 'master' into eddie/script_from_wire
Eddie Hung [Fri, 28 Jun 2019 21:56:34 +0000 (14:56 -0700)]
Merge branch 'master' into eddie/script_from_wire

5 years agoautotest.sh to define _AUTOTB when test_autotb
Eddie Hung [Fri, 28 Jun 2019 21:18:56 +0000 (14:18 -0700)]
autotest.sh to define _AUTOTB when test_autotb

5 years agoTry command in another module
Eddie Hung [Fri, 28 Jun 2019 20:41:32 +0000 (13:41 -0700)]
Try command in another module

5 years agoAdd to CHANGELOG
Eddie Hung [Fri, 28 Jun 2019 20:39:06 +0000 (13:39 -0700)]
Add to CHANGELOG

5 years agoSupport ability for "script -select" to take commands from wires
Eddie Hung [Fri, 28 Jun 2019 20:36:33 +0000 (13:36 -0700)]
Support ability for "script -select" to take commands from wires

5 years agoAdd test
Eddie Hung [Fri, 28 Jun 2019 20:32:09 +0000 (13:32 -0700)]
Add test

5 years agoReplace log_assert() with meaningful log_error()
Eddie Hung [Fri, 28 Jun 2019 18:28:29 +0000 (11:28 -0700)]
Replace log_assert() with meaningful log_error()

5 years agoRemove peepopt call in synth_xilinx since already in synth -run coarse
Eddie Hung [Fri, 28 Jun 2019 19:53:38 +0000 (12:53 -0700)]
Remove peepopt call in synth_xilinx since already in synth -run coarse

5 years agoMake abc9 pass aware of optional ABCEXTERNAL override
Gabriel L. Somlo [Fri, 28 Jun 2019 18:54:58 +0000 (14:54 -0400)]
Make abc9 pass aware of optional ABCEXTERNAL override

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agoAdd missing CHANGELOG entries
Eddie Hung [Fri, 28 Jun 2019 18:16:15 +0000 (11:16 -0700)]
Add missing CHANGELOG entries

5 years agoFix spacing
Eddie Hung [Fri, 28 Jun 2019 18:10:36 +0000 (11:10 -0700)]
Fix spacing

5 years agoMerge pull request #1098 from YosysHQ/xaig
Eddie Hung [Fri, 28 Jun 2019 17:59:03 +0000 (10:59 -0700)]
Merge pull request #1098 from YosysHQ/xaig

"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)

5 years agoAdd test from #1144, and try reading without '-specify' flag
Eddie Hung [Fri, 28 Jun 2019 17:12:48 +0000 (10:12 -0700)]
Add test from #1144, and try reading without '-specify' flag

5 years agoAdd generic __builtin_bswap32 function
Eddie Hung [Fri, 28 Jun 2019 16:59:47 +0000 (09:59 -0700)]
Add generic __builtin_bswap32 function

5 years agoAlso fix write_aiger for UB
Eddie Hung [Fri, 28 Jun 2019 16:55:07 +0000 (09:55 -0700)]
Also fix write_aiger for UB

5 years agoFix more potential for undefined behaviour due to container invalidation
Eddie Hung [Fri, 28 Jun 2019 16:51:43 +0000 (09:51 -0700)]
Fix more potential for undefined behaviour due to container invalidation

5 years agoUpdate synth_ice40 -device doc to be relevant for -abc9 only
Eddie Hung [Fri, 28 Jun 2019 16:49:01 +0000 (09:49 -0700)]
Update synth_ice40 -device doc to be relevant for -abc9 only

5 years agoDisable boxing of ECP5 dist RAM due to regression
Eddie Hung [Fri, 28 Jun 2019 16:46:36 +0000 (09:46 -0700)]
Disable boxing of ECP5 dist RAM due to regression

5 years agoAdd write address to abc_scc_break of ECP5 dist RAM
Eddie Hung [Fri, 28 Jun 2019 16:45:48 +0000 (09:45 -0700)]
Add write address to abc_scc_break of ECP5 dist RAM

5 years agoFix DO4 typo
Eddie Hung [Fri, 28 Jun 2019 16:45:40 +0000 (09:45 -0700)]
Fix DO4 typo

5 years agoMerge pull request #1146 from gsomlo/gls-test-abc-ext
Clifford Wolf [Fri, 28 Jun 2019 08:30:31 +0000 (10:30 +0200)]
Merge pull request #1146 from gsomlo/gls-test-abc-ext

tests: use optional ABCEXTERNAL when specified

5 years agoImprove specify dummy parser, fixes #1144
Clifford Wolf [Fri, 28 Jun 2019 08:21:16 +0000 (10:21 +0200)]
Improve specify dummy parser, fixes #1144

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1046 from bogdanvuk/master
Clifford Wolf [Fri, 28 Jun 2019 06:30:18 +0000 (08:30 +0200)]
Merge pull request #1046 from bogdanvuk/master

Optimizing DFFs whose initial value prevents their value from changing

5 years agotests: use optional ABCEXTERNAL when specified
Gabriel L. Somlo [Fri, 28 Jun 2019 02:54:09 +0000 (22:54 -0400)]
tests: use optional ABCEXTERNAL when specified

Commits 65924fd1abc40924, and ebe29b66 hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agoReduce diff with upstream
Eddie Hung [Thu, 27 Jun 2019 23:13:22 +0000 (16:13 -0700)]
Reduce diff with upstream

5 years agoExtraneous newline
Eddie Hung [Thu, 27 Jun 2019 23:12:20 +0000 (16:12 -0700)]
Extraneous newline

5 years agoRemove noise from ice40/cells_sim.v
Eddie Hung [Thu, 27 Jun 2019 23:11:39 +0000 (16:11 -0700)]
Remove noise from ice40/cells_sim.v

5 years agoRefactor for one "abc_carry" attribute on module
Eddie Hung [Thu, 27 Jun 2019 23:07:14 +0000 (16:07 -0700)]
Refactor for one "abc_carry" attribute on module

5 years agoMerge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Thu, 27 Jun 2019 22:30:00 +0000 (15:30 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig

5 years agoDo not use Module::remove() iterator version
Eddie Hung [Thu, 27 Jun 2019 22:29:20 +0000 (15:29 -0700)]
Do not use Module::remove() iterator version

5 years agoRemove redundant doc
Eddie Hung [Thu, 27 Jun 2019 22:28:55 +0000 (15:28 -0700)]
Remove redundant doc

5 years agoRemove &retime when abc9 -fast
Eddie Hung [Thu, 27 Jun 2019 22:17:39 +0000 (15:17 -0700)]
Remove &retime when abc9 -fast

5 years agoCleanup abc9.cc
Eddie Hung [Thu, 27 Jun 2019 22:15:56 +0000 (15:15 -0700)]
Cleanup abc9.cc

5 years agoUndo iterator based Module::remove() for cells, as containers will not
Eddie Hung [Thu, 27 Jun 2019 22:03:21 +0000 (15:03 -0700)]
Undo iterator based Module::remove() for cells, as containers will not
invalidate

5 years agoAdd help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too
Bogdan Vukobratovic [Thu, 27 Jun 2019 20:06:23 +0000 (22:06 +0200)]
Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too

5 years agoFix memory leak when one of multiple DFF cells is removed in opt_rmdff
Bogdan Vukobratovic [Thu, 27 Jun 2019 20:02:12 +0000 (22:02 +0200)]
Fix memory leak when one of multiple DFF cells is removed in opt_rmdff

When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Thu, 27 Jun 2019 19:53:23 +0000 (12:53 -0700)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agoMerge pull request #1139 from YosysHQ/dave/check-sim-iverilog
Eddie Hung [Thu, 27 Jun 2019 19:31:15 +0000 (12:31 -0700)]
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog

tests: Check that Icarus can parse arch sim models

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Thu, 27 Jun 2019 18:54:34 +0000 (11:54 -0700)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agoGrr
Eddie Hung [Thu, 27 Jun 2019 18:53:42 +0000 (11:53 -0700)]
Grr

5 years agoCapitalisation
Eddie Hung [Thu, 27 Jun 2019 18:26:44 +0000 (11:26 -0700)]
Capitalisation

5 years agoMake CHANGELOG clearer
Eddie Hung [Thu, 27 Jun 2019 18:25:57 +0000 (11:25 -0700)]
Make CHANGELOG clearer

5 years agoMerge pull request #1143 from YosysHQ/clifford/fix1135
Eddie Hung [Thu, 27 Jun 2019 18:48:48 +0000 (11:48 -0700)]
Merge pull request #1143 from YosysHQ/clifford/fix1135

Add "pmux2shiftx -norange"

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Thu, 27 Jun 2019 18:31:19 +0000 (11:31 -0700)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agoAdd warning if synth_xilinx -abc9 with family != xc7
Eddie Hung [Thu, 27 Jun 2019 18:22:49 +0000 (11:22 -0700)]
Add warning if synth_xilinx -abc9 with family != xc7