re PR target/81348 (PowerPC64: Code built with -mcpu=power9 hits SEGV in RTL split2)

[gcc]
2017-07-07  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/81348
* config/rs6000/rs6000.md (HI sign_extend splitter): Use the
correct operand in doing the split.

[gcc/testsuite]
2017-07-07  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/81348
* gcc.target/powerpc/pr81348.c: New test.

From-SVN: r250054

Fix pr60510.f test on arm-linux-gnueabihf

Only run the test if the target supports double precision vectorization.

gcc/testsuite/ChangeLog:

2017-07-07  Szabolcs Nagy  <szabolcs.nagy@arm.com>

* gfortran.dg/vect/pr60510.f: Require vect_double support.

From-SVN: r250053

builtins-1-p9-runnable.c: Forgot to add new file before doing commit 250051.

gcc/testsuite/ChangeLog:

2017-07-07  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-1-p9-runnable.c: Forgot to add new
file before doing commit 250051.

From-SVN: r250052

rs6000-c: Add support for built-in function vector unsigned short vec_pack_to_short_fp32...

gcc/ChangeLog:

2017-07-07 Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000-c: Add support for built-in function
vector unsigned short vec_pack_to_short_fp32 (vector float,
      vector float).
* config/rs6000/rs6000-builtin.def (CONVERT_4F32_8I16): Add
BU_P9V_AV_2 and BU_P9V_OVERLOAD_2 definitions.
* config/rs6000/altivec.h (vec_pack_to_short_fp32): Add define.
* config/rs6000/altivec.md(UNSPEC_CONVERT_4F32_8I16): Add UNSPEC.
(convert_4f32_8i16): Add define_expand.
* doc/extend.texi: Update the built-in documentation file for the
new built-in function.

gcc/testsuite/ChangeLog:

2017-07-07  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-1-p9-runnable.c: Add new test
file for built-ins.

From-SVN: r250051

Support for the SPARC M8 cpu.

This patch serie adds support for the SPARC M8 processor to GCC.
The SPARC M8 processor implements the Oracle SPARC Architecture 2017.

- bmask* instructions are put in their own instruction type.  It makes
  little sense to have them in the same category than array
  instructions.

- Similarly, VIS compare instructions are put in their own instruction
  type.  This is to better accommodate subtypes, which are not quite
  the same than the subtypes of `visl' instructions.

- The introduction of a new `subtype' insn attribute in sparc.md
  avoids the need for adjusting the instruction scheduler DFAs for
  previous cpu models every time a new cpu is introduced.

- The full set of SPARC instructions used in sparc.md, and their
  position in the type/subtype hierarchy, is documented in a comment.
  This eases the modification of the DFA schedulers, and the addition
  of new cpus.

- The M7 DFA scheduler is reworked:

  + To use the new type/subtype hierarchy.
  + The v3pipe insn attribute is no longer needed.
  + More accurate latencies for instructions.
  + The C4 core pipeline is documented in a comment in niagara7.md.

- Support for -mcpu=m8 (we are thus suggesting to abandon the niagaraN
  denomination for M8 and later processors.)

- Support for a new VIS level, VIS4B, covering the new VIS
  instructions introduced in OSA2017 and implemented in the M8.  Also
  built-ins.

- A M8 DFA scheduler:

  + Also based on the new type/subtype hierarchy.
  + The functional units in the C5 core are explicitly documented in a
    comment in m8.md.

gcc/ChangeLog:

* config/sparc/m8.md: New file.
* config/sparc/sparc.md: Include m8.md.

* config/sparc/sparc.opt: New option -mvis4b.
* config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B.
(sparc_option_override): Handle VIS4B.
(enum sparc_builtins): Define
SPARC_BUILTIN_DICTUNPACK{8,16,32},
SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and
SPARC_BUILTIN_FPCMPUR{8,16,32}SHL.
(check_constant_argument): New function.
(sparc_vis_init_builtins): Define builtins
__builtin_vis_dictunpack{8,16,32},
__builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl,
__builtin_vis_fpcmpu{le,gt}{8,16,32}shl,
__builtin_vis_fpcmpde{8,16,32}shl and
__builtin_vis_fpcmpur{8,16,32}shl.
(sparc_expand_builtin): Check that the constant operands to
__builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed
constant and in range.
* config/sparc/sparc-c.c (sparc_target_macros): Handle
TARGET_VIS4B.
* config/sparc/sparc.h (SPARC_IMM2_P): Define.
(SPARC_IMM5_P): Likewise.
* config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b".
(enabled): Handle vis4b.
(UNSPEC_DICTUNPACK): New unspec.
(UNSPEC_FPCMPSHL): Likewise.
(UNSPEC_FPUCMPSHL): Likewise.
(UNSPEC_FPCMPDESHL): Likewise.
(UNSPEC_FPCMPURSHL): Likewise.
(cpu_feature): New CPU feature `vis4b'.
(dictunpack{8,16,32}): New insns.
(FPCSMODE): New mode iterator.
(fpcscond): New code iterator.
(fpcsucond): Likewise.
(fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns.
(fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise.
(fpcmpde{8,16,32}{si,di}shl): Likewise.
(fpcmpur{8,16,32}{si,di}shl): Likewise.
* config/sparc/constraints.md: Define constraints `q' for unsigned
2-bit integer constants and `t' for unsigned 5-bit integer
constants.
* config/sparc/predicates.md (imm5_operand_dictunpack8): New
predicate.
(imm5_operand_dictunpack16): Likewise.
(imm5_operand_dictunpack32): Likewise.
(imm2_operand): Likewise.
* doc/invoke.texi (SPARC Options): Document -mvis4b.
* doc/extend.texi (SPARC VIS Built-in Functions): Document the
ditunpack* and fpcmp*shl builtins.

* config.gcc: Handle m8 in --with-{cpu,tune} options.
* config.in: Add HAVE_AS_SPARC6 define.
* config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC
M8.
* config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for
TARGET_CPU_m8.
(ASM_CPU32_DEFAUILT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle m8.
(ASM_CPU_SPEC): Likewise.
* config/sparc/sparc-opts.h (enum processor_type): Add
PROCESSOR_M8.
* config/sparc/sparc.c (m8_costs): New struct.
(sparc_option_override): Handle TARGET_CPU_m8.
(sparc32_initialize_trampoline): Likewise.
(sparc64_initialize_trampoline): Likewise.
(sparc_issue_rate): Likewise.
(sparc_register_move_cost): Likewise.
* config/sparc/sparc.h (TARGET_CPU_m8): Define.
(CPP_CPU64_DEFAULT_SPEC): Define for M8.
(ASM_CPU64_DEFAULT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle M8.
(ASM_CPU_SPEC): Likewise.
(AS_M8_FLAG): Define.
* config/sparc/sparc.md: Add m8 to the cpu attribute.
* config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets.
* configure.ac (HAVE_AS_SPARC6): Check for assembler support for
M8 instructions.
* configure: Regenerate.
* doc/invoke.texi (SPARC Options): Document -mcpu=m8 and
-mtune=m8.

* config/sparc/niagara7.md: Rework the DFA scheduler to use insn
subtypes.
* config/sparc/sparc.md: Remove the `v3pipe' insn attribute.
("*movdi_insn_sp32"): Do not set v3pipe.
("*movsi_insn"): Likewise.
("*movdi_insn_sp64"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("*sign_extendsidi2_insn"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("<vlop:code><VL:mode>3"): Likewise.
("*not_<vlop:code><VL:mode>3"): Likewise.
("*nand<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise.
("one_cmpl<VL:mode>2"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likweise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
("bmaskdi_vis"): Likewise.
("bmasksi_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("pdistn<P:mode>_vis"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.

* config/sparc/sparc.md ("subtype"): New insn attribute.
("*wrgsr_sp64"): Set insn subtype.
("*rdgsr_sp64"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likewise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("fexpand_vis"): Likewise.
("fpmerge_vis"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("fchksm16_vis"): Likewise.
("v<vis3_shift_patname><GCM:mode>3"): Likewise.
("fmean16_vis"): Likewise.
("fp<plusminus_insn>64_vis"): Likewise.
("<plusminus_insn>v8qi3"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
("<vis4_minmax_patname><VMMAX:mode>3"): Likewise.
("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise.
("<vis3_addsub_ss_patname>v8qi3"): Likewise.
("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise.
("*movqi_insn"): Likewise.
("*movhi_insn"): Likewise.
("*movsi_insn"): Likewise.
("movsi_pic_gotdata_op"): Likewise.
("*movdi_insn_sp32"): Likewise.
("*movdi_insn_sp64"): Likewise.
("movdi_pic_gotdata_op"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendhisi2_insn"): Likewise.
("*zero_extendqihi2_insn"): Likewise.
("*zero_extendqisi2_insn"): Likewise.
("*zero_extendqidi2_insn"): Likewise.
("*zero_extendhidi2_insn"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("ldfsr"): Likewise.
("prefetch_64"): Likewise.
("prefetch_32"): Likewise.
("tie_ld32"): Likewise.
("tie_ld64"): Likewise.
("*tldo_ldub_sp32"): Likewise.
("*tldo_ldub1_sp32"): Likewise.
("*tldo_ldub2_sp32"): Likewise.
("*tldo_ldub_sp64"): Likewise.
("*tldo_ldub1_sp64"): Likewise.
("*tldo_ldub2_sp64"): Likewise.
("*tldo_ldub3_sp64"): Likewise.
("*tldo_lduh_sp32"): Likewise.
("*tldo_lduh1_sp32"): Likewise.
("*tldo_lduh_sp64"): Likewise.
("*tldo_lduh1_sp64"): Likewise.
("*tldo_lduh2_sp64"): Likewise.
("*tldo_lduw_sp32"): Likewise.
("*tldo_lduw_sp64"): Likewise.
("*tldo_lduw1_sp64"): Likewise.
("*tldo_ldx_sp64"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.

* config/sparc/sparc.md ("type"): New insn type viscmp.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to
viscmp.
("fpcmp<gcond:code>8<P:mode>_vis"): Likewise.
("fucmp<gcond:code>8<P:mode>_vis"): Likewise.
("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
* config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle
viscmp.
("n7_vis_logical_11cycle"): Likewise.
* config/sparc/niagara4.md ("n4_vis_logical"): Likewise.
* config/sparc/niagara2.md ("niag3_vis": Likewise.
* config/sparc/niagara.md ("niag_vis"): Likewise.
* config/sparc/ultra3.md ("us3_fga"): Likewise.
* config/sparc/ultra1_2.md ("us1_fga_double"): Likewise.

* config/sparc/sparc.md: New instruction type `bmask'.
(bmaskdi_vis): Use the `bmask' type.
(bmasksi_vis): Likewise.
* config/sparc/ultra3.md (us3_array): Likewise.
* config/sparc/niagara7.md (n7_array): Likewise.
* config/sparc/niagara4.md (n4_array): Likewise.
* config/sparc/niagara2.md (niag2_vis): Likewise.
(niag3_vis): Likewise.
* config/sparc/niagara.md (niag_vis): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/sparc/dictunpack.c: New file.
* gcc.target/sparc/fpcmpdeshl.c: Likewise.
* gcc.target/sparc/fpcmpshl.c: Likewise.
* gcc.target/sparc/fpcmpurshl.c: Likewise.
* gcc.target/sparc/fpcmpushl.c: Likewise.

From-SVN: r250049

ipa-comdats.c: Remove optimize check from gate.

* ipa-comdats.c: Remove optimize check from gate.
* ipa-fnsummary.c (ipa_fn_summary_generate): do not generate summary
for functions not optimized.
(ipa_fn_summary_read): Skip optimize check.
(ipa_fn_summary_write): Likewise.
* ipa-inline-analysis.c (do_estimate_growth_1): Check that caller
is optimized.
* ipa-inline.c (can_inline_edge_p): Not optimized functions are
uninlinable.
(can_inline_edge_p): Check flag_pcc_struct_return for match.
(check_callers): Give up on caller which is not optimized.
(inline_small_functions): Likewise.
(ipa_inline): Do not give up when not optimizing.
* ipa-visbility.c (function_and_variable_visibility): Do not optimize
away unoptimizes cdtors.
(whole_program_function_and_variable_visibility): Do
ipa_discover_readonly_nonaddressable_vars in LTO mode.
* ipa.c (process_references): Do not check optimize.
(symbol_table::remove_unreachable_nodes): Update optimize check.
(set_writeonly_bit): Update optimize check.
(pass_ipa_cdtor_merge::gate): Do not check optimize.
(pass_ipa_single_use::gate): Remove.

From-SVN: r250048

Daily bump.

From-SVN: r250047

rs6000.c (union_defs, [...]): Move all code related to p8 swap optimizations to file rs6000-p8swap.c.

2017-07-06  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

* config/rs6000/rs6000.c (union_defs, union_uses, insn_is_load_p,
insn_is_store_p, insn_is_swap_p, const_load_sequence_p, v2df_reduction_p,
rtx_is_swappable_p, insn_is_swappable_p, chain_contains_only_swaps,
mark_swaps_for_removal, swap_const_vector_halves, adjust_subreg_index,
permute_load, permute_store, adjust_extract, adjust_splat,
adjust_xxpermdi, adjust_concat, adjust_vperm, handle_special_swappables,
replace_swap_with_copy, dump_swap_insn_table,
alignment_with_canonical_addr, alignment_mask, find_alignment_op,
recombine_lvx_pattern, recombine_stvx_pattern,
recombine_lvx_stvx_patterns, rs6000_analyze_swaps,
make_pass_analyze_swaps): Move all code related to p8 swap optimizations
to file rs6000-p8swap.c.
* config/rs6000/rs6000-p8swap.c: New file.
* config/rs6000/t-rs6000: Add rule to build rs6000-p8swap.o.
* config.gcc: Add rs6000-p8swap.o to extra_objs for powerpc*-*-*
and rs6000*-*-* targets.

From-SVN: r250040

re PR fortran/70071 (ICE on wrong usage of a subscript triplet)

2017-07-06  Harald Anlauf  <anlauf@gmx.de>

PR fortran/70071
* array.c (gfc_ref_dimen_size): Handle bad subscript triplets.

2017-07-06  Harald Anlauf  <anlauf@gmx.de>

PR fortran/70071
* gfortran.dg/coarray_44.f90: New testcase.

From-SVN: r250039

PR c++/81204 - parse error with dependent template-name

PR c++/81204 - parse error with dependent template-name
* parser.c (cp_parser_lookup_name): Revert previous change.

From-SVN: r250037

Remove selftest dependency on C++ frontend

gcc/ChangeLog
* Makefile.in (selftest): Remove dependency on s-selftest-c++.

From-SVN: r250036

lto-wrapper.c (merge_and_complain): Do not merge fexceptions...

* lto-wrapper.c (merge_and_complain): Do not merge
fexceptions, fnon_call_exceptions, ftrapv, ffp_contract_, fmath_errno,
fsigned_zeros, ftrapping_math, fwrapv.
(append_compiler_options): Do not track these options.
(append_linker_options): Likewie

From-SVN: r250035

cgraphunit.c (cgraph_node::finalize_function): When !flag_toplevel_reorde set no_reorder flag.

* cgraphunit.c (cgraph_node::finalize_function): When
!flag_toplevel_reorde set no_reorder flag.
(varpool_node::finalize_decl): Likewise.
(symbol_table::compile): Drop no toplevel reorder path.

* lto-partition.c (lto_balanced_map): Do not check
flag_toplevel_reorder.

From-SVN: r250034

bb-reorder.c (better_edge_p): Do not build traces across abnormal/eh edges...

* bb-reorder.c (better_edge_p): Do not build traces across abnormal/eh
edges; zero probability is not better than uninitialized.

From-SVN: r250033

asan.h (asan_sanitize_allocas_p): Declare.

gcc/
* asan.h (asan_sanitize_allocas_p): Declare.
* asan.c (asan_sanitize_allocas_p): New function.
(handle_builtin_stack_restore): Bail out if !asan_sanitize_allocas_p.
(handle_builtin_alloca): Likewise.
* cfgexpand.c (expand_used_vars): Do not add allocas unpoisoning stuff
if !asan_sanitize_allocas_p.
* params.def (asan-instrument-allocas): Add new option.
* params.h (ASAN_PROTECT_ALLOCAS): Define.
* opts.c (common_handle_option): Disable allocas sanitization for
KASan by default.

gcc/testsuite/
* c-c++-common/asan/kasan-alloca-1.c: New test.
* c-c++-common/asan/kasan-alloca-2.c: Likewise.

From-SVN: r250032

ASAN: Implement dynamic allocas/VLAs sanitization.

gcc/
* asan.c: Include gimple-fold.h.
(get_last_alloca_addr): New function.
(handle_builtin_stackrestore): Likewise.
(handle_builtin_alloca): Likewise.
(asan_emit_allocas_unpoison): Likewise.
(get_mem_refs_of_builtin_call): Add new parameter, remove const
quallifier from first paramerer. Handle BUILT_IN_ALLOCA,
BUILT_IN_ALLOCA_WITH_ALIGN and BUILT_IN_STACK_RESTORE builtins.
(instrument_builtin_call): Pass gimple iterator to
get_mem_refs_of_builtin_call.
(last_alloca_addr): New global.
* asan.h (asan_emit_allocas_unpoison): Declare.
* builtins.c (expand_asan_emit_allocas_unpoison): New function.
(expand_builtin): Handle BUILT_IN_ASAN_ALLOCAS_UNPOISON.
* cfgexpand.c (expand_used_vars): Call asan_emit_allocas_unpoison
if function calls alloca.
* gimple-fold.c (replace_call_with_value): Remove static keyword.
* gimple-fold.h (replace_call_with_value): Declare.
* internal-fn.c: Include asan.h.
* sanitizer.def (BUILT_IN_ASAN_ALLOCA_POISON,
BUILT_IN_ASAN_ALLOCAS_UNPOISON): New builtins.

gcc/testsuite/
* c-c++-common/asan/alloca_big_alignment.c: New test.
* c-c++-common/asan/alloca_detect_custom_size.c: Likewise.
* c-c++-common/asan/alloca_instruments_all_paddings.c: Likewise.
* c-c++-common/asan/alloca_loop_unpoisoning.c: Likewise.
* c-c++-common/asan/alloca_overflow_partial.c: Likewise.
* c-c++-common/asan/alloca_overflow_right.c: Likewise.
* c-c++-common/asan/alloca_safe_access.c: Likewise.
* c-c++-common/asan/alloca_underflow_left.c: Likewise.

From-SVN: r250031

Support C++-specific selftests

gcc/ChangeLog:
* Makefile.in (SELFTEST_FLAGS): Drop "-x c", moving it to...
(C_SELFTEST_FLAGS): New.
(CPP_SELFTEST_FLAGS): New.
(SELFTEST_DEPS): New, from deps of s-selftest.
(C_SELFTEST_DEPS): New, from deps of s-selftest.
(CPP_SELFTEST_DEPS): New.
(selftest): Add dependency on s-selftest-c++.
(s-selftest): Rename to...
(s-selftest-c): ...this, moving deps to SELFTEST_DEPS
and C_SELFTEST_DEPS, and using C_SELFTEST_FLAGS rather
than SELFTEST_FLAGS.
(selftest-gdb): Rename to...
(selftest-c-gdb): ...this, using C_SELFTEST_DEPS and
C_SELFTEST_FLAGS.
(selftest-gdb): Reintroduce as an alias for selftest-c-gdb.
(selftest-valgrind): Rename to...
(selftest-c-valgrind): ...this, using C_SELFTEST_DEPS and
C_SELFTEST_FLAGS.
(selftest-valgrind): Reintroduce as an alias for
selftest-c-valgrind.
(s-selftest-c++): New.
(selftest-c++-gdb): New.
(selftest-c++-valgrind): New.

gcc/c-family/ChangeLog:
* c-common.c (selftest::c_family_tests): New.
* c-common.h (selftest::run_c_tests): Move decl to c/c-lang.h.
(selftest::c_family_tests): New decl.

gcc/c/ChangeLog:
* c-lang.c (selftest::run_c_tests): Move body to c_family_tests,
and call that instead.
* c-tree.h (selftest::run_c_tests): New decl.

gcc/cp/ChangeLog:
* cp-lang.c (LANG_HOOKS_RUN_LANG_SELFTESTS): Define as
selftest::run_cp_tests.
(selftest::run_cp_tests): New function.
* cp-tree.h (selftest::run_cp_tests): New decl.

From-SVN: r250030

re PR target/81305 ([avr] avrtiny uses LDS for SREG in ISR routines which is out of range of LDS.)

PR target/81305
* gcc.target/avr/isr-test.h: Fix warnings.

From-SVN: r250029

Fix previous ChangeLog entry, taken from the original
patch instead of the update.

From-SVN: r250028

gcc.c (spec_undefvar_allowed): New global.

2017-07-06  Olivier Hainque  <hainque@adacore.com>

        * gcc.c (spec_undefvar_allowed): New global.
        (process_command): Set to true when running for --version or --help
        alone, or together.
        (getenv_spec_function): When the variable is not defined, use the
        variable name as the variable value if we're allowed not to issue
        a fatal error.

From-SVN: r250027

auto-profile.c (afdo_set_bb_count, [...]): Set counts/probabilities as determined by afdo.

* auto-profile.c (afdo_set_bb_count, afdo_propagate_edge,
afdo_annotate_cfg): Set counts/probabilities as determined by afdo.

From-SVN: r250026

Add support for ARMv8-R architecture

2017-07-06  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-cpus.in (armv8-r): Add new entry.
    * config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
    * config/arm/arm-tables.opt: Regenerate.
    * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
    enumerator.
    * doc/invoke.texi: Mention -march=armv8-r and its extensions.

    gcc/testsuite/
    * lib/target-supports.exp: Generate
    check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
    and check_effective_target_arm_arch_v8r_multilib.

    libgcc/
    * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.

From-SVN: r250025

ChangeLog: Clean up from mid air collision

gcc/ChangeLog:

2017-07-06  Carl Love  <cel@us.ibm.com>

  * ChangeLog: Clean up from mid air collision

gcc/testsuite/ChangeLog:

2017-07-06  Carl Love  <cel@us.ibm.com>

  * ChangeLog: Clean up from mid air collision

From-SVN: r250024

rs6000-c.c: Add support for built-in functions vector signed int vec_subc (vector signed int...

gcc/ChangeLog:

2017-07-06  Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000-c.c: Add support for built-in functions
vector signed int vec_subc (vector signed int, vector signed int);
vector signed __int128 vec_subc (vector signed __int128,
 vector signed __int128);
vector unsigned __int128 vec_subc (vector unsigned __int128,
   vector unsigned __int128);
vector signed int vec_sube (vector signed int, vector signed int,
    vector signed int);
vector unsigned int vec_sube (vector unsigned int,
      vector unsigned int,
      vector unsigned int);
vector signed __int128 vec_sube (vector signed __int128,
 vector signed __int128,
 vector signed__int128);
vector unsigned __int128 vec_sube (vector unsigned __int128,
   vector unsigned __int128,
   vector unsigned __int128);
vector signed int vec_subec (vector signed int, vector signed int,
     vector signed int);
vector unsigned int vec_subec (vector unsigned int,
       vector unsigned int,
       vector unsigned int);
vector signed __int128 vec_subec (vector signed __int128,
  vector signed __int128,
  vector signed__int128);
vector unsigned __int128 vec_subec (vector unsigned __int128,
    vector unsigned __int128,
    vector unsigned __int128);
* config/rs6000/rs6000.c (ALTIVEC_BUILTIN_VEC_SUBE,
ALTIVEC_BUILTIN_VEC_SUBEC): Add ef_builtins.
* config/rs6000/rs6000-builtin.def (SUBE, SUBEC): Add
BU_ALTIVEC_OVERLOAD_X definitions.
* config/rs6000/altivec.h (vec_sube, vec_subec): Add builtin defines.
* doc/extend.texi: Update the built-in documentation file for the new
built-in functions.

gcc/testsuite/ChangeLog:

2017-07-06  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/p8vector-builtin-8.c (foo): Add test cases for
the new vec_subc, vec_sube, vec_subec built-ins.  Add the missing test
cases for vec_addc, adde and addec builtins.

From-SVN: r250023

diagnostics: fix end-points of ranges within macros (PR c++/79300)

gcc/ChangeLog:
PR c++/79300
* diagnostic-show-locus.c (layout::layout): Use start and finish
spelling location for the start and finish of each range.
* genmatch.c (linemap_client_expand_location_to_spelling_point):
Add unused aspect param.
* input.c (expand_location_1): Add "aspect" param, and use it
to access the correct part of the location.
(expand_location): Pass LOCATION_ASPECT_CARET to new param of
expand_location_1.
(expand_location_to_spelling_point): Likewise.
(linemap_client_expand_location_to_spelling_point): Add "aspect"
param, and pass it to expand_location_1.

gcc/testsuite/ChangeLog:
PR c++/79300
* c-c++-common/Wmisleading-indentation-3.c (fn_14): Update
expected underlining within macro expansion.
* c-c++-common/pr70264.c: Likewise.
* g++.dg/plugin/diagnostic-test-expressions-1.C
(test_within_macro_1): New test.
(test_within_macro_2): Likewise.
(test_within_macro_3): Likewise.
(test_within_macro_4): Likewise.
* gcc.dg/format/diagnostic-ranges.c (test_macro_3): Update
expected underlining within macro expansion.
(test_macro_4): Likewise.
* gcc.dg/plugin/diagnostic-test-expressions-1.c
(test_within_macro_1): New test.
(test_within_macro_2): Likewise.
(test_within_macro_3): Likewise.
(test_within_macro_4): Likewise.
* gcc.dg/spellcheck-fields-2.c (test_macro): Update expected
underlining within macro expansion.

libcpp/ChangeLog:
PR c++/79300
* include/line-map.h (enum location_aspect): New enum.
(linemap_client_expand_location_to_spelling_point): Add
enum location_aspect param.
* line-map.c (rich_location::get_expanded_location): Update for
new param of linemap_client_expand_location_to_spelling_point.
(rich_location::maybe_add_fixit): Likewise.
(fixit_hint::affects_line_p): Likewise.

From-SVN: r250022

Fix memory leaks in libstdc++ tests

* testsuite/20_util/specialized_algorithms/memory_management_tools/
1.cc: Free memory.
* testsuite/22_locale/locale/cons/5.cc: Remove redundant restoration
of original environment and free memory.

From-SVN: r250021

Fix memory leaks in libstdc++ ABI tests

* testsuite/abi/pr42230.cc: Free memory.
* testsuite/util/testsuite_abi.cc (demangle): Return std::string
instead of pointer that might need freeing.
* testsuite/util/testsuite_abi.h (demangle): Likewise.
* testsuite/util/testsuite_hooks.cc (verify_demangle): Free memory.

From-SVN: r250020

Prevent __uses_alloc from holding dangling references

* include/bits/uses_allocator.h (__use_alloc(const _Alloc&&)): Add
deleted overload to prevent dangling references to rvalues.
* include/experimental/memory_resource
(polymorphic_allocator::construct): Do not call __use_alloc with
rvalue arguments.

From-SVN: r250019

Add missing intrinsics for VGETMANT[SD,SS] and VGETEXP[SD,SS]

gcc/
* config/i386/avx512fintrin.h (_mm_mask_getexp_round_ss,
_mm_maskz_getexp_round_ss, _mm_mask_getexp_round_sd,
_mm_maskz_getexp_round_sd, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss, _mm_mask_getexp_ss, _mm_maskz_getexp_ss,
_mm_mask_getexp_sd, _mm_maskz_getexp_sd, _mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_mask_getmant_ss,
_mm_maskz_getmant_ss): New intrinsics.
(__builtin_ia32_getexpss128_mask): Changed to ...
__builtin_ia32_getexpss128_round ... this.
(__builtin_ia32_getexpsd128_mask): Changed to ...
__builtin_ia32_getexpsd128_round ... this.
* config/i386/i386-builtin-types.def
((V2DF, V2DF, V2DF, INT, V2DF, UQI, INT),
(V4SF, V4SF, V4SF, INT, V4SF, UQI, INT)): New function type aliases.
* config/i386/i386-builtin.def (__builtin_ia32_getexpsd_mask_round,
__builtin_ia32_getexpss_mask_round, __builtin_ia32_getmantsd_mask_round,
__builtin_ia32_getmantss_mask_round): New builtins.
* config/i386/i386.c (V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI_INT,
V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI_INT): Handle new types.
(CODE_FOR_avx512f_vgetmantv2df_mask_round,
CODE_FOR_avx512f_vgetmantv4sf_mask_round): New cases.
* config/i386/sse.md
(avx512f_sgetexp<mode><round_saeonly_name>): Changed to ...
avx512f_sgetexp<mode><mask_scalar_name>
<round_saeonly_scalar_name> ... this.
(vgetexp<ssescalarmodesuffix>\t{<round_saeonly_op3>%2, %1, %0|
%0, %1, %2<round_saeonly_op3>}): Changed to ...
vgetexp<ssescalarmodesuffix>
\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %2<round_saeonly_scalar_mask_op3>} ... this.
(avx512f_vgetmant<mode><round_saeonly_name>): Changed to ...
avx512f_vgetmant<mode><mask_scalar_name>
<round_saeonly_scalar_name> ... this.
(vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|
%0, %1, %2<round_saeonly_op4>, %3}): Changed to ...
vgetmant<ssescalarmodesuffix>
\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|
%0<mask_scalar_operand4>, %1, %2
<round_saeonly_scalar_mask_op4>, %3} ... this.
* config/i386/subst.md (mask_scalar_operand4,
round_saeonly_scalar_mask_operand4, round_saeonly_scalar_mask_op4,
round_saeonly_scalar_nimm_predicate): New subst attributes.

gcc/testsuite/
* gcc.target/i386/avx512f-vgetexpsd-1.c (_mm_mask_getexp_sd,
_mm_maskz_getexp_sd, _mm_mask_getexp_round_sd,
_mm_maskz_getexp_round_sd): Test new intrinsics.
* gcc.target/i386/avx512f-vgetexpss-1.c (_mm_mask_getexp_ss,
_mm_maskz_getexp_ss, _mm_mask_getexp_round_ss,
_mm_maskz_getexp_round_ss): Ditto.
* gcc.target/i386/avx512f-vgetmantsd-1.c (_mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd): Ditto.
* gcc.target/i386/avx512f-vgetmantss-1.c (_mm_mask_getmant_ss,
_mm_maskz_getmant_ss, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss): Ditto.
* gcc.target/i386/avx512f-vgetexpsd-2.c (_mm_mask_getexp_sd,
_mm_maskz_getexp_sd, _mm_getexp_round_sd, _mm_mask_getexp_round_sd,
_mm_maskz_getexp_round_sd): New runtime tests.
* gcc.target/i386/avx512f-vgetexpss-2.c (_mm_mask_getexp_ss,
_mm_maskz_getexp_ss, _mm_getexp_round_ss, _mm_mask_getexp_round_ss,
_mm_maskz_getexp_round_ss): Ditto.
* gcc.target/i386/avx512f-vgetmantsd-2.c (_mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_getmant_round_sd, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd): Ditto.
* gcc.target/i386/avx512f-vgetmantss-2.c (_mm_mask_getmant_ss,
_mm_maskz_getmant_ss, _mm_getmant_round_ss, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss): Ditto.
* gcc.target/i386/avx-1.c (__builtin_ia32_getexpsd_mask_round,
__builtin_ia32_getexpss_mask_round, __builtin_ia32_getmantsd_mask_round,
__builtin_ia32_getmantss_mask_round): Test new builtins.
* gcc.target/i386/sse-13.c : Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c (_mm_maskz_getexp_round_sd,
_mm_maskz_getexp_round_ss, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss, _mm_mask_getexp_round_sd,
_mm_mask_getexp_round_ss): Test new intrinsics.
* gcc.target/i386/testround-1.c: Ditto.
* gcc.target/i386/sse-22.c (_mm_maskz_getmant_round_sd,
_mm_maskz_getmant_round_ss, _mm_mask_getmant_round_sd,
_mm_mask_getmant_round_ss): Test new intrinsics
* gcc.target/i386/testimm-10.c (_mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_mask_getmant_ss,
_mm_maskz_getmant_ss): Test new intrinsics.

From-SVN: r250018

Remove old rounding code

gcc/
* gcc/config/i386/i386.c (ix86_erase_embedded_rounding):
Remove code for old rounding pattern.

From-SVN: r250017

[arm] Fix warning in parsecpu.awk

In awk, single quotes within a quoted string do not need escaping.
The existing code causes awk to grumble in the build logs.

* config/arm/parsecpu.awk (gen_comm_data): Do not escape single quotes
in quoted strings.

From-SVN: r250016

[arm] Fix cross-native builds

The patch I committed yesterday to remove some generated headers from
the source tree unfortunately has a dependency missing that is only
revealed when doing a cross-native or full Canadian cross build.  The
gen* programs were missing a dependency on one of the generated
headers.

Fixed by adding an explicit dependency rule for GTM_H in the same way
as we do for TM_H.

* config/arm/t-arm (GTM_H): Add arm-cpu.h.

Checked that this restores cross-native building.

From-SVN: r250015

[testsuite] Add dg-require-stack-check

2017-07-06  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* doc/sourcebuild.texi (Test Directives, Variants of
dg-require-support): Add documentation for dg-require-stack-check.

gcc/testsuite/
* lib/target-supports-dg.exp (dg-require-stack-check): New.
* lib/target-supports.exp (check_stack_check_available): New.
* g++.dg/other/i386-9.C: Add dg-require-stack-check.
* gcc.c-torture/compile/stack-check-1.c: Likewise.
* gcc.dg/graphite/run-id-pr47653.c: Likewise.
* gcc.dg/pr47443.c: Likewise.
* gcc.dg/pr48134.c: Likewise.
* gcc.dg/pr70017.c: Likewise.
* gcc.target/aarch64/stack-checking.c: Likewise.
* gcc.target/arm/stack-checking.c: Likewise.
* gcc.target/i386/pr48723.c: Likewise.
* gcc.target/i386/pr55672.c: Likewise.
* gcc.target/i386/pr67265-2.c: Likewise.
* gcc.target/i386/pr67265.c: Likewise.
* gnat.dg/opt49.adb: Likewise.
* gnat.dg/stack_check1.adb: Likewise.
* gnat.dg/stack_check2.adb: Likewise.
* gnat.dg/stack_check3.adb: Likewise.

From-SVN: r250013

Daily bump.

From-SVN: r250012

re PR target/80103 (ICE in output_1144, at config/rs6000/vsx.md:2298)

gcc/testsuite/ChangeLog:

2017-07-05  Kelvin Nilsen  <kelvin@gcc.gnu.org>

PR target/80103
* gcc.target/powerpc/pr80103-1.c (void b): Correct spelling of
__attribute__.

From-SVN: r250008

Scalar mask and round RTL templates

gcc/
* config/i386/subst.md (mask_scalar, round_scalar,
round_saeonly_scalar): New meta-templates.
(mask_scalar_name, mask_scalar_operand3, round_scalar_name,
round_scalar_mask_operand3, round_scalar_mask_op3,
round_scalar_constraint, round_scalar_prefix, round_saeonly_scalar_name,
round_saeonly_scalar_mask_operand3, round_saeonly_scalar_mask_op3,
round_saeonly_scalar_constraint,
round_saeonly_scalar_prefix): New subst attribute.
* config/i386/sse.md
(<sse>_vm<plusminus_insn><mode>3<mask_name><round_name>): Renamed to ...
<sse>_vm<plusminus_insn><mode>3<mask_scalar_name>
<round_scalar_name> ... this.
(<sse>_vm<multdiv_mnemonic><mode>3<mask_name><round_name>): Renamed to ...
<sse>_vm<multdiv_mnemonic><mode>3<mask_scalar_name>
<round_scalar_name> ... this.
(<sse>_vm<code><mode>3<mask_name><round_saeonly_name>): Renamed to ...
<sse>_vm<code><mode>3<mask_scalar_name>
<round_saeonly_scalar_name> ... this.
(v<plusminus_mnemonic><ssescalarmodesuffix>
\t{<round_mask_op3>%2, %1, %0<mask_operand3>|
%0<mask_operand3>, %1, %<iptr>2<round_mask_op3>}): Changed to ...
v<plusminus_mnemonic><ssescalarmodesuffix>
\t{<round_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %<iptr>2<round_scalar_mask_op3>} ... this.
(v<multdiv_mnemonic><ssescalarmodesuffix>
\t{<round_mask_op3>%2, %1, %0<mask_operand3>|
%0<mask_operand3>, %1, %<iptr>2<round_mask_op3>}): Changed to ...
v<multdiv_mnemonic><ssescalarmodesuffix>
\t{<round_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %<iptr>2<round_scalar_mask_op3>} ... this.
(v<maxmin_float><ssescalarmodesuffix>
\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|
%0<mask_operand3>, %1, %<iptr>2<round_saeonly_mask_op3>}): Changed to ...
v<maxmin_float><ssescalarmodesuffix>
\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %<iptr>2
<round_saeonly_scalar_mask_op3>} ... this.

gcc/testsuite/
* gcc.target/i386/avx512f-vaddsd-3.c: New test for mask 0 verification.
* gcc.target/i386/avx512f-vaddss-3.c: Ditto.
* gcc.target/i386/avx512f-vdivsd-3.c: Ditto.
* gcc.target/i386/avx512f-vdivss-3.c: Ditto.
* gcc.target/i386/avx512f-vmaxsd-3.c: Ditto.
* gcc.target/i386/avx512f-vmaxss-3.c: Ditto.
* gcc.target/i386/avx512f-vminsd-3.c: Ditto.
* gcc.target/i386/avx512f-vminss-3.c: Ditto.
* gcc.target/i386/avx512f-vmulsd-3.c: Ditto.
* gcc.target/i386/avx512f-vmulss-3.c: Ditto.
* gcc.target/i386/avx512f-vsubsd-3.c: Ditto.
* gcc.target/i386/avx512f-vsubss-3.c: Ditto.

From-SVN: r250006

[ARM] Implement TARGET_FIXED_CONDITION_CODE_REGS

This patch implements TARGET_FIXED_CONDITION_CODE_REGS on ARM.

We have two main cases to consider: in Thumb1 code there are no
condition code registers, so we simply return false.  For other
cases we set the the first pointer to CC_REGNUM and the second to
VFPCC_REGNUM iff generating hard-float code.

Running the CSiBE benchmark I see a couple of cases (both in the same
file) where this feature kicks in, so it's not a major change.

* config/arm/arm.c (arm_fixed_condition_code_regs): New function.
(TARGET_FIXED_CONDITION_CODE_REGS): Redefine.

From-SVN: r250005

Use SET_DECL_MODE in libcc1

2017-07-05  Richard Sandiford  <richard.sandiford@linaro.org>

libcc1/
* libcp1plugin.cc (plugin_build_field): Use SET_DECL_MODE.

From-SVN: r250004

Remove enum before machine_mode

r216834 did a mass removal of "enum" before "machine_mode".  This patch
removes some new uses that have been added since then.

2017-07-05  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* combine.c (simplify_if_then_else): Remove "enum" before
"machine_mode".
* compare-elim.c (can_eliminate_compare): Likewise.
* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type):
Likewise.
(aarch64_lookup_simd_builtin_type): Likewise.
(aarch64_simd_builtin_type): Likewise.
(aarch64_init_simd_builtin_types): Likewise.
(aarch64_simd_expand_args): Likewise.
* config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist):
Likewise.
(aarch64_reverse_mask): Likewise.
(aarch64_simd_emit_reg_reg_move): Likewise.
(aarch64_gen_adjusted_ldpstp): Likewise.
(aarch64_ccmp_mode_to_code): Likewise.
(aarch64_operands_ok_for_ldpstp): Likewise.
(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
* config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class):
Likewise.
(aarch64_min_divisions_for_recip_mul): Likewise.
(aarch64_reassociation_width): Likewise.
(aarch64_get_condition_code_1): Likewise.
(aarch64_simd_emit_reg_reg_move): Likewise.
(aarch64_simd_attr_length_rglist): Likewise.
(aarch64_reverse_mask): Likewise.
(aarch64_operands_ok_for_ldpstp): Likewise.
(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
(aarch64_gen_adjusted_ldpstp): Likewise.
* config/aarch64/cortex-a57-fma-steering.c (fma_node::rename):
Likewise.
* config/arc/arc.c (legitimate_offset_address_p): Likewise.
* config/arm/arm-builtins.c (arm_simd_builtin_std_type): Likewise.
(arm_lookup_simd_builtin_type): Likewise.
(arm_simd_builtin_type): Likewise.
(arm_init_simd_builtin_types): Likewise.
(arm_expand_builtin_args): Likewise.
* config/arm/arm-protos.h (arm_expand_builtin): Likewise.
* config/ft32/ft32.c (ft32_libcall_value): Likewise.
(ft32_setup_incoming_varargs): Likewise.
(ft32_function_arg): Likewise.
(ft32_function_arg_advance): Likewise.
(ft32_pass_by_reference): Likewise.
(ft32_arg_partial_bytes): Likewise.
(ft32_valid_pointer_mode): Likewise.
(ft32_addr_space_pointer_mode): Likewise.
(ft32_addr_space_legitimate_address_p): Likewise.
* config/i386/i386-protos.h (ix86_operands_ok_for_move_multiple):
Likewise.
* config/i386/i386.c (ix86_setup_incoming_vararg_bounds): Likewise.
(ix86_emit_outlined_ms2sysv_restore): Likewise.
(iamcu_alignment): Likewise.
(canonicalize_vector_int_perm): Likewise.
(ix86_noce_conversion_profitable_p): Likewise.
(ix86_mpx_bound_mode): Likewise.
(ix86_operands_ok_for_move_multiple): Likewise.
* config/microblaze/microblaze-protos.h
(microblaze_expand_conditional_branch_reg): Likewise.
* config/microblaze/microblaze.c
(microblaze_expand_conditional_branch_reg): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok):
Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_invalid_binary_op): Likewise.
(fusion_p9_p): Likewise.
(emit_fusion_p9_load): Likewise.
(emit_fusion_p9_store): Likewise.
* config/riscv/riscv-protos.h (riscv_regno_mode_ok_for_base_p):
Likewise.
(riscv_hard_regno_mode_ok_p): Likewise.
(riscv_address_insns): Likewise.
(riscv_split_symbol): Likewise.
(riscv_legitimize_move): Likewise.
(riscv_function_value): Likewise.
(riscv_hard_regno_nregs): Likewise.
(riscv_expand_builtin): Likewise.
* config/riscv/riscv.c (riscv_build_integer_1): Likewise.
(riscv_build_integer): Likewise.
(riscv_split_integer): Likewise.
(riscv_legitimate_constant_p): Likewise.
(riscv_cannot_force_const_mem): Likewise.
(riscv_regno_mode_ok_for_base_p): Likewise.
(riscv_valid_base_register_p): Likewise.
(riscv_valid_offset_p): Likewise.
(riscv_valid_lo_sum_p): Likewise.
(riscv_classify_address): Likewise.
(riscv_legitimate_address_p): Likewise.
(riscv_address_insns): Likewise.
(riscv_load_store_insns): Likewise.
(riscv_force_binary): Likewise.
(riscv_split_symbol): Likewise.
(riscv_force_address): Likewise.
(riscv_legitimize_address): Likewise.
(riscv_move_integer): Likewise.
(riscv_legitimize_const_move): Likewise.
(riscv_legitimize_move): Likewise.
(riscv_address_cost): Likewise.
(riscv_subword): Likewise.
(riscv_output_move): Likewise.
(riscv_canonicalize_int_order_test): Likewise.
(riscv_emit_int_order_test): Likewise.
(riscv_function_arg_boundary): Likewise.
(riscv_pass_mode_in_fpr_p): Likewise.
(riscv_pass_fpr_single): Likewise.
(riscv_pass_fpr_pair): Likewise.
(riscv_get_arg_info): Likewise.
(riscv_function_arg): Likewise.
(riscv_function_arg_advance): Likewise.
(riscv_arg_partial_bytes): Likewise.
(riscv_function_value): Likewise.
(riscv_pass_by_reference): Likewise.
(riscv_setup_incoming_varargs): Likewise.
(riscv_print_operand): Likewise.
(riscv_elf_select_rtx_section): Likewise.
(riscv_save_restore_reg): Likewise.
(riscv_for_each_saved_reg): Likewise.
(riscv_register_move_cost): Likewise.
(riscv_hard_regno_mode_ok_p): Likewise.
(riscv_hard_regno_nregs): Likewise.
(riscv_class_max_nregs): Likewise.
(riscv_memory_move_cost): Likewise.
* config/rl78/rl78-protos.h (rl78_split_movsi): Likewise.
* config/rl78/rl78.c (rl78_split_movsi): Likewise.
(rl78_addr_space_address_mode): Likewise.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_invalid_binary_op): Likewise.
(fusion_p9_p): Likewise.
(emit_fusion_p9_load): Likewise.
(emit_fusion_p9_store): Likewise.
* config/visium/visium-protos.h (prepare_move_operands): Likewise.
(ok_for_simple_move_operands): Likewise.
(ok_for_simple_move_strict_operands): Likewise.
(ok_for_simple_arith_logic_operands): Likewise.
(visium_legitimize_reload_address): Likewise.
(visium_select_cc_mode): Likewise.
(output_cbranch): Likewise.
(visium_split_double_move): Likewise.
(visium_expand_copysign): Likewise.
(visium_expand_int_cstore): Likewise.
(visium_expand_fp_cstore): Likewise.
* config/visium/visium.c (visium_pass_by_reference): Likewise.
(visium_function_arg): Likewise.
(visium_function_arg_advance): Likewise.
(visium_libcall_value): Likewise.
(visium_setup_incoming_varargs): Likewise.
(visium_legitimate_constant_p): Likewise.
(visium_legitimate_address_p): Likewise.
(visium_legitimize_address): Likewise.
(visium_secondary_reload): Likewise.
(visium_register_move_cost): Likewise.
(visium_memory_move_cost): Likewise.
(prepare_move_operands): Likewise.
(ok_for_simple_move_operands): Likewise.
(ok_for_simple_move_strict_operands): Likewise.
(ok_for_simple_arith_logic_operands): Likewise.
(visium_function_value_1): Likewise.
(rtx_ok_for_offset_p): Likewise.
(visium_legitimize_reload_address): Likewise.
(visium_split_double_move): Likewise.
(visium_expand_copysign): Likewise.
(visium_expand_int_cstore): Likewise.
(visium_expand_fp_cstore): Likewise.
(visium_split_cstore): Likewise.
(visium_select_cc_mode): Likewise.
(visium_split_cbranch): Likewise.
(output_cbranch): Likewise.
(visium_print_operand_address): Likewise.
* expmed.c (flip_storage_order): Likewise.
* expmed.h (emit_cstore): Likewise.
(flip_storage_order): Likewise.
* genrecog.c (validate_pattern): Likewise.
* hsa-gen.c (gen_hsa_addr): Likewise.
* internal-fn.c (expand_arith_overflow): Likewise.
* ira-color.c (allocno_copy_cost_saving): Likewise.
* lra-assigns.c (find_hard_regno_for_1): Likewise.
* lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise.
(process_invariant_for_inheritance): Likewise.
* lra-eliminations.c (move_plus_up): Likewise.
* omp-low.c (lower_oacc_reductions): Likewise.
* simplify-rtx.c (simplify_subreg): Likewise.
* target.def (TARGET_SETUP_INCOMING_VARARG_BOUNDS): Likewise.
(TARGET_CHKP_BOUND_MODE): Likewise..
* targhooks.c (default_chkp_bound_mode): Likewise.
(default_setup_incoming_vararg_bounds): Likewise.
* targhooks.h (default_chkp_bound_mode): Likewise.
(default_setup_incoming_vararg_bounds): Likewise.
* tree-ssa-math-opts.c (divmod_candidate_p): Likewise.
* tree-vect-loop.c (calc_vec_perm_mask_for_shift): Likewise.
(have_whole_vector_shift): Likewise.
* tree-vect-stmts.c (vectorizable_load): Likewise.
* doc/tm.texi: Regenerate.

gcc/brig/
* brig-c.h (brig_type_for_mode): Remove "enum" before "machine_mode".
* brig-lang.c (brig_langhook_type_for_mode): Likewise.

gcc/jit/
* dummy-frontend.c (jit_langhook_type_for_mode): Remove "enum" before
"machine_mode".

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r250003

Graceful degrade if Binutils PR21472 is not available.

gcc/
Graceful degrade if Binutils PR21472 is not available.
PR target/81072
* configure.ac [target=avr]: WARN instead of ERROR if avrxmega3
.rodata in flash test fails.
(HAVE_LD_AVR_AVRXMEGA3_RODATA_IN_FLASH): Define it if test passes.
* confgure: Regenerate.
* config.in: Regenerate.
* config/avr/avr.c (avr_asm_named_section)
[HAVE_LD_AVR_AVRXMEGA3_RODATA_IN_FLASH]: Only trigger
__do_copy_data for stuff in .rodata if flash_pm_offset = 0.
(avr_asm_init_sections): Same.

From-SVN: r250000

[Patch ARM] Remove %? string from some Advanced SIMD patterns.

Advanced SIMD patterns are not predicable, thus they should not have
%? in their output templates. Found when auditing the code for
something else. This has been in my tree for sometime , bootstrapped
and regression tested on armhf for armv7ve+simd as the architectural
base.

Applied to trunk

<DATE>  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

* config/arm/neon.md (fma<VCVTF:mode>4): Remove %?.
(fma<VH:mode>4_intrinsic): Likewise.
(*fmsub<VCVTF:mode>4): Likewise.
(*fmsub<VH:mode>4_intrinsic): Likewise.

regards
Ramana

From-SVN: r249999

Move ChangeLog entry to testsuite.

From-SVN: r249997

re PR target/81305 ([avr] avrtiny uses LDS for SREG in ISR routines which is out of range of LDS.)

gcc/
PR target/81305
* testsuite/gcc.target/avr/isr-test.h: New file.

From-SVN: r249996

re PR target/81305 ([avr] avrtiny uses LDS for SREG in ISR routines which is out of range of LDS.)

gcc/
PR target/81305
* config/avr/avr.c (avr_out_movhi_mr_r_xmega) [CONSTANT_ADDRESS_P]:
Don't depend on "optimize > 0".
(out_movhi_r_mr, out_movqi_mr_r): Same.
(out_movhi_mr_r, out_movqi_r_mr): Same.
(avr_address_cost) [CONSTANT_ADDRESS_P]: Don't depend cost for
io_address_operand on "optimize > 0".
* testsuite/gcc.target/avr/torture/isr-01-simple.c: New test.
* testsuite/gcc.target/avr/torture/isr-02-call.c: New test.
* testsuite/gcc.target/avr/torture/isr-03-fixed.c: New test.

From-SVN: r249995

tree-loop-distribution.c: Add general explanantion on the pass.

* tree-loop-distribution.c: Add general explanantion on the pass.
(generate_loops_for_partition): Mark distributed loop.
(pg_add_dependence_edges): New parameter.  Handle alias data
dependence specially and record it in the parameter if asked.
(struct pg_vdata, pg_edata, pg_edge_callback_data): New structs.
(init_partition_graph_vertices, add_partition_graph_edge): New.
(pg_skip_alias_edge, free_partition_graph_edata_cb): New.
(free_partition_graph_vdata, build_partition_graph): New.
(sort_partitions_by_post_order, merge_dep_scc_partitions): New.
(pg_collect_alias_ddrs, break_alias_scc_partitions): New.
(data_ref_segment_size, latch_dominated_by_data_ref): New.
(compute_alias_check_pairs, version_loop_by_alias_check): New.
(version_for_distribution_p, finalize_partitions): New.
(distribute_loop): Handle alias data dependence specially.  Factor
out loop fusion code as functions and call these functions.

gcc/testsuite
* gcc.dg/tree-ssa/ldist-4.c: Adjust test string.
* gcc.dg/tree-ssa/ldist-12.c: Ditto.
* gcc.dg/tree-ssa/ldist-13.c: Ditto.
* gcc.dg/tree-ssa/ldist-14.c: Ditto.

From-SVN: r249994

tree-loop-distribution.c (classify_partition): New parameter and better handle reduction statement.

* tree-loop-distribution.c (classify_partition): New parameter and
better handle reduction statement.
(rdg_build_partitions): Revise comment.
(distribute_loop): Compute statements in all partitions and pass it
to classify_partition.

gcc/testsuite
* gcc.dg/tree-ssa/ldist-26.c: New test.

From-SVN: r249993

tree-loop-distribution.c (enum partition_type): New.

* tree-loop-distribution.c (enum partition_type): New.
(struct partition): New field type.
(partition_merge_into): Add parameter.  Update partition type.
(data_dep_in_cycle_p, update_type_for_merge): New functions.
(build_rdg_partition_for_vertex): Compute partition type.
(rdg_build_partitions): Dump partition type.
(distribute_loop): Update calls to partition_merge_into.

From-SVN: r249992

tree-loop-distribution.c (struct ddr_hasher): New.

* tree-loop-distribution.c (struct ddr_hasher): New.
(ddr_hasher::hash, ::equal, get_data_dependence): New function.
(ddrs_table): New.
(classify_partition): Call get_data_dependence.
(pg_add_dependence_edges): Ditto.
(distribute_loop): Release data dependence hash table.

From-SVN: r249991

tree-loop-distribution.c (ref_base_address): Delete.

* tree-loop-distribution.c (ref_base_address): Delete.
(similar_memory_accesses): Rename ...
(share_memory_accesses): ... to this.  Check if partitions access
the same memory reference.
(distribute_loop): Call share_memory_accesses.

gcc/testsuite
* gcc.dg/tree-ssa/ldist-6.c: XFAIL.

From-SVN: r249990

tree-loop-distribution.c (struct partition): New field recording its data reference.

* tree-loop-distribution.c (struct partition): New field recording
its data reference.
(partition_alloc, partition_free): Init and release data refs.
(partition_merge_into): Merge data refs.
(build_rdg_partition_for_vertex): Collect data refs for partition.
(pg_add_dependence_edges): Change parameters from vector to bitmap.
Update uses.
(distribute_loop): Remve data refs from vertice data of partition
graph.

From-SVN: r249989

tree-loop-distribution.c (params.h): Include header file.

* tree-loop-distribution.c (params.h): Include header file.
(MAX_DATAREFS_NUM, DR_INDEX): New macro.
(datarefs_vec): New global var.
(create_rdg_vertices): Use datarefs_vec directly.
(free_rdg): Don't free data references.
(build_rdg): Update use.  Don't free data references.
(distribute_loop): Compute global variable for data references.
Bail out if there are too many data references.

From-SVN: r249988

tree-loop-distribution.c (loop_nest): New global var.

* tree-loop-distribution.c (loop_nest): New global var.
(build_rdg): Use loop directly, rather than loop nest.
(pg_add_dependence_edges): Remove loop nest parameter.  Use global
variable directly.
(distribute_loop): Compute global variable loop nest.  Update use.

From-SVN: r249987

tree-loop-distribution.c (enum fuse_type, [...]): New.

* tree-loop-distribution.c (enum fuse_type, fuse_message): New.
(partition_merge_into): New parameter.  Dump reason for fusion.
(distribute_loop): Update use of partition_merge_into.

From-SVN: r249986

tree-loop-distribution.c (bb_top_order_index): New.

* tree-loop-distribution.c (bb_top_order_index): New.
(bb_top_order_index_size, bb_top_order_cmp): New.
(stmts_from_loop): Use topological order.
(pass_loop_distribution::execute): Compute and release topological
order for basic blocks.

From-SVN: r249985

tree-loop-distribution.c (pass_loop_distribution::execute): Skip if no loops.

* tree-loop-distribution.c (pass_loop_distribution::execute): Skip
if no loops.

From-SVN: r249984

cfgloop.h (struct loop): Add comment.

* cfgloop.h (struct loop): Add comment.  New field orig_loop_num.
* cfgloopmanip.c (lv_adjust_loop_entry_edge): Comment change.
* internal-fn.c (expand_LOOP_DIST_ALIAS): New function.
* internal-fn.def (LOOP_DIST_ALIAS): New.
* tree-vectorizer.c (fold_loop_vectorized_call): Rename to ...
(fold_loop_internal_call): ... this.
(vect_loop_dist_alias_call): New function.
(set_uid_loop_bbs): Call fold_loop_internal_call.
(vectorize_loops): Fold IFN_LOOP_VECTORIZED and IFN_LOOP_DIST_ALIAS
internal calls.

From-SVN: r249983

Daily bump.

From-SVN: r249982

re PR target/81300 (-fpeephole2 breaks __builtin_ia32_sbb_u64, _subborrow_u64 on AMD64)

2017-07-04  Uros Bizjak  <ubizjak@gmail.com>

PR target/81300
* config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes):
Require dead FLAGS_REG at the beginning of a peephole.

testsuite/ChangeLog:

PR target/81300
* gcc.target/i386/pr81300.c: New test.

From-SVN: r249977

re PR target/81294 (_subborrow_u64 argument order inconsistent with intrinsic reference, icc)

PR target/81294
* config/i386/adxintrin.h (_subborrow_u32): Swap _X and _Y
arguments in the call to __builtin_ia32_sbb_u32.
(_subborrow_u64): Swap _X and _Y arguments in the call to
__builtin_ia32_sbb_u64.

testsuite/ChangeLog:

PR target/81294
* gcc.target/i386/adx-addcarryx32-2.c (adx_test): Swap
x and y arguments in the call to _subborrow_u32.
* gcc.target/i386/adx-addcarryx64-2.c (adx_test): Swap
x and y arguments in the call to _subborrow_u64.
* gcc.target/i386/pr81294-1.c: New test.
* gcc.target/i386/pr81294-2.c: Ditto.

From-SVN: r249976

re PR debug/81278 (-fcompare-debug failure (length))

PR debug/81278
* tree-vrp.c (compare_assert_loc): Turn into a function template
with stable template parameter.  Only test if a->e is NULL,
!a->e == !b->e has been verified already.  Use e == NULL or
e != NULL instead of e or ! e tests.  If stable is true, don't use
iterative_hash_expr, on the other side allow a or b or both NULL
and sort the NULLs last.
(process_assert_insertions): Sort using compare_assert_loc<false>
instead of compare_assert_loc, later sort using
compare_assert_loc<true> before calling process_assert_insertions_for
in a loop.  Use break instead of continue once seen NULL pointer.

From-SVN: r249975

[ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8

2017-07-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
    Cortex-R7 and Cortex-R8 processors.

From-SVN: r249974

ipa-utils.c (ipa_merge_profiles): Fix merging when dst is uninitialized while src is not.

* ipa-utils.c (ipa_merge_profiles): Fix merging when dst is
uninitialized while src is not.

From-SVN: r249973

[AArch64] Fix strict aliasing issue in gcc.target/aarch64/simd/vminmaxnm_1.c

While doing some unrelated work the gcc.target/aarch64/simd/vminmaxnm_1.c testcase started failing for me.
Upon investigation it turns out that it breaks the C strict aliasing rules in the CHECK macro by casting
a pointer to an incompatible type and dereferencing it. GCC even warns about it if compiled with -Wstrict-aliasing.

This patch fixes the testcase by making it use memcmp to compare the vector elements.
This avoids the undefined behaviour.

The testcase still passes on trunk.

    * gcc.target/aarch64/simd/vminmaxnm_1.c: Fix strict aliasing issues.

From-SVN: r249972

[arm] Move some generated files out of the source tree

When I originally started work on the new options framework for ARM
I'd worked on the assumption that AWK might not be available on every
build machine (only on developer's machines).  However, looking again
I notice that all the options framework relies on it being present for
every build.  This means that some of the generated files that come
from running parsecpu.awk do not need to be kept under revision
control.

Unfortunately, it's not _all_ generated files.  The build
infrastructure assumes that all .md fragments are in the source tree
and similarly that all .opt fragments are there as well.

Still, eliminating the very big .h files is a step forward as they are
very regular in structure and diff/patch/merge tools can sometimes
make mistakes when resolving conflicts.

So this patch removes the generated .h files from the source tree and
tweaks the make rules accordingly.  I've also changed the build rules
to use the stamp technique to eliminate some false dependencies in a
rebuild.

Top-level:

* contrib/gcc_update (files_and_dependencies): Remove stamp rules for
arm-specific auto-generated header files.

gcc:
* common/config/arm/arm-common.c: Adjust include path for
arm-cpu-cdata.h
* t-arm (TM_H): Adjust path for arm-cpu.h.
(arm-cpu.h): Create in build directory.  Adjust dependency rules.
(arm-cpu-data.h): Likewise.
(arm-cpu-cdata.h): Likewise.
* config/arm/arm-cpu.h: Delete.
* config/arm/arm-cpu-cdata.h: Delete.
* config/arm/arm-cpu-data.h: Delete.

From-SVN: r249971

[Patch ARM] Add initial tuning for Cortex-A55 and Cortex-A75

Much like my AArch64 patch a few weeks ago, this patch adds support
for the ARM Cortex-A75 and Cortex-A55 processors through the
-mcpu/-mtune values cortex-a55 and cortex-a75, and an
ARM DynamIQ big.LITTLE configuration of these two processors through
the -mcpu/-mtune value cortex-a75.cortex-a55

Both Cortex-A55 and Cortex-A75 support ARMv8-A with the ARM8.1-A and
ARMv8.2-A extensions. This is reflected in the patch, -mcpu=cortex-a75 is
treated as equivalent to passing -mtune=cortex-a75 -march=armv8.2-a+fp16

gcc/

2017-07-04  James Greenhalgh  <james.greenhalgh@arm.com>

* config/arm/arm-cpus.in (cortex-a55): New.
(cortex-a75): Likewise.
(cortex-a75.cortex-a55): Likewise.
* config/arm/driver-arm.c (arm_cpu_table): Add cortex-a55 and
cortex-a75.
* doc/invoke.texi (-mcpu): Document cortex-a55 and cortex-a75.

* config/arm/arm-cpu-cdata.h: Regenerate.
* config/arm/arm-cpu-data.h: Regenerate.
* config/arm/arm-cpu.h: Regenerate.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.

From-SVN: r249970

* haifa-sched.c (sched_create_recovery_edges): Update profile.

From-SVN: r249967

bb-reorder.c (better_edge_p): Fix handling of uninitialized probability.

* bb-reorder.c (better_edge_p): Fix handling of uninitialized
probability.

From-SVN: r249966

Fix ChangeLog format in r247584

This patch fixes relative pathnames in gcc/ChangeLog for r247584.

From-SVN: r249964

re PR c/81231 (ICE with invalid argument to __atomic_*)

PR c/81231
* c-common.c (sync_resolve_size): Give error for pointers to incomplete
types.

* gcc.dg/atomic-pr81231.c: New test.

From-SVN: r249963

brig-function.cc: Include profile-count.h.

* brigfrontend/brig-function.cc: Include profile-count.h.
* brigfrontend/brig-to-generic.cc: Likewise.

From-SVN: r249962

PR 81292: ICE on related strlens after r249880

r249880 installed the result of a strlen in a strinfo if the strinfo
wasn't previously a full string.  But as Jakub says in the PR comments,
we can't just do that in isolation, because there are no vdefs on the
call that would invalidate any related strinfos.

This patch updates the related strinfos if the adjustment is simple and
invalidates them otherwise.  As elsewhere, we treat adjustments of the
form strlen +/- INTEGER_CST as simple but anything else as too complex.

2017-07-04  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
PR tree-optimization/81292
* tree-ssa-strlen.c (handle_builtin_strlen): When setting
full_string_p, also call adjust_related_strinfos if the adjustment
is simple, otherwise invalidate related strinfos.

gcc/testsuite/
PR tree-optimization/81292
* gcc.dg/pr81292-1.c: New test.
* gcc.dg/pr81292-2.c: Likewise.

From-SVN: r249961

Enable addressable params sanitization with --param asan-stack=1.

2017-07-04  Martin Liska  <mliska@suse.cz>

PR sanitizer/81040
* sanopt.c (sanitize_rewrite_addressable_params): Mark the
newly created variable as DECL_IGNORED_P.
2017-07-04  Martin Liska  <mliska@suse.cz>

PR sanitizer/81040
* g++.dg/asan/function-argument-1.C: Run the test-case w/o
use-after-scope sanitization.

From-SVN: r249960

Use xstrdup_for_dump in ipa-inline.c (PR ipa/81293).

2017-07-04  Martin Liska  <mliska@suse.cz>

PR ipa/81293
* ipa-inline.c (inline_small_functions):
Use xstrdup_for_dump.

From-SVN: r249959

Save and restore EDGE_DFS_BACK in draw_cfg_edges

2017-07-04  Tom de Vries  <tom@codesourcery.com>

* graph.c (draw_cfg_edges): Save and restore EDGE_DFS_BACK.

From-SVN: r249954

Add missing libgcc/ChangeLog entry.

From-SVN: r249953

function-argument-3.C: Add -Wno-psabi to additional options.

* g++.dg/asan/function-argument-3.C: Add -Wno-psabi to additional
options.

From-SVN: r249952

re PR target/81175 (EXC_BAD_ACCESS in ::slpeel_duplicate_current_defs_from_edges(edge, edge, edge, edge) at is-a.h:192)

PR target/81175
* gcc.target/i386/pr69255-2.c (foo): Use the return value of the
gather.

From-SVN: r249951

vxworks.h (PTRDIFF_TYPE, SIZE_TYPE): Restore unconditional basic definitions.

2017-07-04  Olivier Hainque  <hainque@adacore.com>

* config/vxworks.h (PTRDIFF_TYPE, SIZE_TYPE): Restore
unconditional basic definitions.
(VXWORKS_LIBS_RTP): Likewise, prefixed by VXWORKS_SYSCALL_LIBS_RTP,
empty by default.
* config/i386/vxworks.h (PTRDIFF_TYPE, SIZE_TYPE): Redefine,
accounting for 64bit ABIs using cpu specific macros available for
this purpose.
(VXWORKS_SYSCALL_LIBS_RTP): Likewise.

From-SVN: r249950

Add dg-require ifunc for mvc test-cases.

2017-07-04  Martin Liska  <mliska@suse.cz>

PR ipa/81214
* g++.dg/ext/mvc2.C: Add dg-require ifunc.
* g++.dg/ext/mvc3.C: Likewise.
* gcc.target/i386/mvc2.c: Likewise.
* gcc.target/i386/mvc3.c: Likewise.

From-SVN: r249949

parser.c (cp_parser_decomposition_declaration): Replace decomposition declaration with structured binding in diagnostics.

* parser.c (cp_parser_decomposition_declaration): Replace
decomposition declaration with structured binding in diagnostics.
* decl.c (cp_finish_decomp): Likewise.
(grokdeclarator): Likewise.

* g++.dg/cpp1z/decomp1.C: Expect structured binding instead of
decomposition declaration in diagnostics.
* g++.dg/cpp1z/decomp2.C: Likewise.
* g++.dg/cpp1z/decomp3.C: Likewise.
* g++.dg/cpp1z/decomp4.C: Likewise.
* g++.dg/cpp1z/decomp5.C: Likewise.
* g++.dg/cpp1z/decomp6.C: Likewise.
* g++.dg/cpp1z/decomp7.C: Likewise.
* g++.dg/cpp1z/decomp8.C: Likewise.
* g++.dg/cpp1z/decomp13.C: Likewise.
* g++.dg/cpp1z/decomp14.C: Likewise.
* g++.dg/cpp1z/decomp18.C: Likewise.
* g++.dg/cpp1z/decomp19.C: Likewise.
* g++.dg/cpp1z/decomp22.C: Likewise.
* g++.dg/cpp1z/decomp23.C: Likewise.
* g++.dg/cpp1z/decomp24.C: Likewise.
* g++.dg/cpp1z/decomp25.C: Likewise.
* g++.dg/cpp1z/decomp26.C: Likewise.
* g++.dg/cpp1z/decomp28.C: Likewise.

From-SVN: r249948

re PR c++/81258 (ICE on C++1z code with invalid decomposition declaration: in cp_finish_decl, at cp/decl.c:6760)

PR c++/81258
* parser.c (cp_parser_decomposition_declaration): Diagnose invalid
forms of structured binding initializers.

* g++.dg/cpp1z/decomp21.C (foo): Adjust expected diagnostics.
* g++.dg/cpp1z/decomp30.C: New test.

From-SVN: r249947

* c-warn.c (warn_if_unused_value): Remove WITH_CLEANUP_EXPR handling.

From-SVN: r249943

Daily bump.

From-SVN: r249942

t-vxworks7: New file.

2017-06-27  Olivier Hainque  <hainque@adacore.com>

* config/t-vxworks7: New file.

New file mistakenly omitted from previous commit referencing it.

From-SVN: r249938

re PR c++/65775 (Late-specified return type bypasses return type checks (qualified, function, array))

/cp
2017-07-03  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/65775
* decl.c (grokdeclarator): Move checks on function return type after
the splice_late_return_type call; if declspecs->locations[ds_type_spec]
is UNKNOWN_LOCATION fall back to input_location.

/testsuite
2017-07-03  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/65775
* g++.dg/cpp0x/trailing14.C: New.

From-SVN: r249935

re PR fortran/79866 (diagnostics: typo in "Variable %s at %L of type EVENT_TYPE")

2017-07-03  Dominique d'Humieres  <dominiq@lps.ens.fr>

PR fortran/79866
* resolve.c (resolve_symbol): Fix typo.

PR testsuite/79866
* gfortran.dg/coarray_event_2.f08: New test.

From-SVN: r249934

re PR fortran/79843 (diagnostics: missing word in fortran/symbol.c, conflict_std)

2017-07-03  Dominique d'Humieres  <dominiq@lps.ens.fr>

PR fortran/79843
* symbol.c (check_conflict): Add missing "conflicts".

PR testsuite/79843
* gfortran.dg/namelist_3.f90: Adjust the dg-error string.
* gfortran.dg/pointer_intent_2.f90: Likewise.

From-SVN: r249933

C++: fix "RT_INTERATION" typo

gcc/cp/ChangeLog:
* parser.c (enum required_token): Fix spelling of
RT_INTERATION to RT_ITERATION.
(cp_parser_iteration_statement): Likewise.
(cp_parser_required_error): Likewise.

From-SVN: r249931

re PR bootstrap/81033 (there are cases where ld64 is not able to determine correct atom boundaries from the output GCC currently produces)

2017-07-03  Dominique d'Humieres  <dominiq@lps.ens.fr>

PR target/81033
* config/darwin.c (darwin_function_switched_text_sections):
Fix spaces.

From-SVN: r249930

* tree-vect-loop-manip.c (vect_do_peeling): Fix scaling up.

From-SVN: r249929

[arm] Add -mbe8 and -mbe32 to options summary.

* doc/invoke.texi (ARM Options): Add -mbe8 and -mbe32 to option summary.

From-SVN: r249928

Avoid minimum - 1 confusion in vectoriser

The variables that claimed to be the "minimum number of iterations" for
which vectorisation was profitable were actually the maximum number of
iterations for which vectorisation wasn't profitable.  The loop threshold
was too.

This patch makes the values be what the variable names suggest.

2017-07-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-loop.c (vect_analyze_loop_2): Treat min_scalar_loop_bound,
min_profitable_iters, and th as inclusive lower bounds.
Fix LOOP_VINFO_PEELING_FOR_GAPS condition.
(vect_estimate_min_profitable_iters): Return inclusive lower bounds
for min_profitable_iters and min_profitable_estimate.
(vect_transform_loop): Treat th as an inclusive lower bound.
* tree-vect-loop-manip.c (vect_loop_versioning): Likewise.

From-SVN: r249927

re PR bootstrap/81033 (there are cases where ld64 is not able to determine correct atom boundaries from the output GCC currently produces)

2017-07-03  Dominique d'Humieres  <dominiq@lps.ens.fr>

PR target/81033
* config/darwin.c (darwin_function_switched_text_sections):
Replace DECL_NAME with DECL_ASSEMBLER_NAME, split assemble_name_raw
in two pieces, and suppress the use of buf.

From-SVN: r249926

* hash-table.h (hash_table_mod1): Fix indentation.

From-SVN: r249925

re PR rtl-optimization/81290 (ICE in update_br_prob_note)

PR middle-end/81290
* predict.c (force_edge_cold): Be more careful about propagation
backward.
* profile-count.h (profile_probability::guessed,
profile_probability::fdo, profile_count::guessed, profile_count::fdo):
New.
* tree-ssa-threadupdate.c (recompute_probabilities): Result is guessed.

* gcc.c-torture/compile/pr81290.c: New.

From-SVN: r249924

Andrew pointed out that I did not document the new architecture extension flag I added for the RcPc extension.

Andrew pointed out that I did not document the new architecture extension
flag I added for the RcPc extension. This was intentional, as enabling the
rcpc extension does not change GCC code generation, and is just
an assembler flag. But for completeness, here is documentation for the
new option.

gcc/

2017-07-03  James Greenhalgh  <james.greenhalgh@arm.com>

* doc/invoke.texi (rcpc architecture extension): Document it.

From-SVN: r249923

configure.ac: Set srcdir when sourcing config-lang.in fragments.

* configure.ac: Set srcdir when sourcing config-lang.in fragments.
* configure: Rebuilt.

gcc/objcp/
* config-lang.in: Source cp/config-lang.in, sort objc++ gtfiles list.

From-SVN: r249922

Readd myself as c6x maintainer.

From-SVN: r249920

re PR tree-optimization/60510 (SLP blocks loop vectorization (with reduction))

2017-07-03  Richard Biener  <rguenther@suse.de>

PR tree-optimization/60510
* tree-vect-loop.c (vect_create_epilog_for_reduction): Pass in
the scalar reduction PHI and use it.
(vectorizable_reduction): Properly guard the single_defuse_cycle
path for non-SLP reduction chains where we cannot use it.
Rework reduc_def/index and vector type deduction.  Rework
vector operand gathering during reduction op code-gen.
* tree-vect-slp.c (vect_analyze_slp): For failed SLP reduction
chains dissolve the chain and leave it to non-SLP reduction
handling.

* gfortran.dg/vect/pr60510.f: New testcase.

From-SVN: r249919

Fix secure_getenv.h include in plugin-hsa.c

2017-07-03  Tom de Vries  <tom@codesourcery.com>

* plugin/plugin-hsa.c: Fix secure_getenv.h include.

From-SVN: r249918