yosys.git
5 years agoAdd proper test for SV-style arrays
Clifford Wolf [Thu, 20 Jun 2019 10:06:07 +0000 (12:06 +0200)]
Add proper test for SV-style arrays

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpack...
Clifford Wolf [Thu, 20 Jun 2019 10:03:00 +0000 (12:03 +0200)]
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays

5 years agoMerge pull request #1111 from acw1251/help_summary_fixes
Eddie Hung [Wed, 19 Jun 2019 22:30:50 +0000 (15:30 -0700)]
Merge pull request #1111 from acw1251/help_summary_fixes

Fixed the help summary line for a few commands

5 years agoFixed small typo in ice40_unlut help summary
acw1251 [Wed, 19 Jun 2019 20:39:46 +0000 (16:39 -0400)]
Fixed small typo in ice40_unlut help summary

5 years agoFixed the help summary line for a few commands
acw1251 [Wed, 19 Jun 2019 19:27:04 +0000 (15:27 -0400)]
Fixed the help summary line for a few commands

5 years agoFix bug in #1078, add entry to CHANGELOG
Eddie Hung [Wed, 19 Jun 2019 16:51:11 +0000 (09:51 -0700)]
Fix bug in #1078, add entry to CHANGELOG

5 years agoMerge pull request #1109 from YosysHQ/clifford/fix1106
Clifford Wolf [Wed, 19 Jun 2019 15:25:39 +0000 (17:25 +0200)]
Merge pull request #1109 from YosysHQ/clifford/fix1106

Add "read_verilog -pwires" feature

5 years agoAdd "read_verilog -pwires" feature, closes #1106
Clifford Wolf [Wed, 19 Jun 2019 12:38:50 +0000 (14:38 +0200)]
Add "read_verilog -pwires" feature, closes #1106

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1105 from YosysHQ/clifford/fixlogicinit
Clifford Wolf [Wed, 19 Jun 2019 11:53:07 +0000 (13:53 +0200)]
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit

Improve handling of initial/default values

5 years agoUnpacked array declaration using size
Tobias Wölfel [Wed, 19 Jun 2019 10:47:48 +0000 (12:47 +0200)]
Unpacked array declaration using size

Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.

5 years agoMake tests/aiger less chatty
Clifford Wolf [Wed, 19 Jun 2019 10:20:35 +0000 (12:20 +0200)]
Make tests/aiger less chatty

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd defvalue test, minor autotest fixes for .sv files
Clifford Wolf [Wed, 19 Jun 2019 10:12:08 +0000 (12:12 +0200)]
Add defvalue test, minor autotest fixes for .sv files

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUse input default values in hierarchy pass
Clifford Wolf [Wed, 19 Jun 2019 09:49:20 +0000 (11:49 +0200)]
Use input default values in hierarchy pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd defaultvalue attribute
Clifford Wolf [Wed, 19 Jun 2019 09:37:11 +0000 (11:37 +0200)]
Add defaultvalue attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix handling of "logic" variables with initial value
Clifford Wolf [Wed, 19 Jun 2019 09:25:11 +0000 (11:25 +0200)]
Fix handling of "logic" variables with initial value

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1100 from bwidawsk/home
Clifford Wolf [Wed, 19 Jun 2019 08:52:59 +0000 (10:52 +0200)]
Merge pull request #1100 from bwidawsk/home

Support ~ in filename parsing

5 years agoMerge pull request #1104 from whitequark/case-semantics
Clifford Wolf [Wed, 19 Jun 2019 08:50:32 +0000 (10:50 +0200)]
Merge pull request #1104 from whitequark/case-semantics

Clarify switch/case semantics in RTLIL

5 years agoExplain exact semantics of switch and case rules in the manual.
whitequark [Wed, 19 Jun 2019 05:22:40 +0000 (05:22 +0000)]
Explain exact semantics of switch and case rules in the manual.

5 years agoIn RTLIL::Module::check(), check process invariants.
whitequark [Wed, 19 Jun 2019 05:22:13 +0000 (05:22 +0000)]
In RTLIL::Module::check(), check process invariants.

5 years agoSupport filename rewrite in backends
Ben Widawsky [Mon, 17 Jun 2019 21:45:48 +0000 (14:45 -0700)]
Support filename rewrite in backends

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agoSupport ~ for home directory
Ben Widawsky [Mon, 17 Jun 2019 21:45:11 +0000 (14:45 -0700)]
Support ~ for home directory

This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
5 years agoMerge pull request #1086 from udif/pr_elab_sys_tasks2
Clifford Wolf [Tue, 18 Jun 2019 14:52:08 +0000 (16:52 +0200)]
Merge pull request #1086 from udif/pr_elab_sys_tasks2

Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)

5 years agoAdd timescale and generated-by header to yosys-smtbmc MkVcd
Clifford Wolf [Sun, 16 Jun 2019 21:12:03 +0000 (23:12 +0200)]
Add timescale and generated-by header to yosys-smtbmc MkVcd

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #829 from abdelrahmanhosny/master
Serge Bazanski [Thu, 13 Jun 2019 10:14:37 +0000 (12:14 +0200)]
Merge pull request #829 from abdelrahmanhosny/master

Dockerfile for Yosys

5 years agoFixed brojen $error()/$info/$warning() on non-generate blocks
Udi Finkelstein [Mon, 10 Jun 2019 23:52:06 +0000 (02:52 +0300)]
Fixed brojen $error()/$info/$warning() on non-generate blocks
(within always/initial blocks)

5 years agoAdd some more comments
Eddie Hung [Mon, 10 Jun 2019 17:27:55 +0000 (10:27 -0700)]
Add some more comments

5 years agoMerge pull request #1082 from corecode/u4k
David Shah [Mon, 10 Jun 2019 14:12:23 +0000 (15:12 +0100)]
Merge pull request #1082 from corecode/u4k

ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k

5 years agoice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
Simon Schubert [Mon, 10 Jun 2019 09:49:08 +0000 (11:49 +0200)]
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k

5 years agoMerge pull request #1078 from YosysHQ/eddie/muxcover_costs
Clifford Wolf [Sat, 8 Jun 2019 09:31:19 +0000 (11:31 +0200)]
Merge pull request #1078 from YosysHQ/eddie/muxcover_costs

Allow muxcover costs to be changed

5 years agoFix spacing from spaces to tabs
Eddie Hung [Fri, 7 Jun 2019 22:44:57 +0000 (15:44 -0700)]
Fix spacing from spaces to tabs

5 years agoMerge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Clifford Wolf [Fri, 7 Jun 2019 21:13:34 +0000 (23:13 +0200)]
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger

Fix read_aiger to really get tested, and fix some uncovered read_aiger issues

5 years agoAdd read_aiger to CHANGELOG
Eddie Hung [Fri, 7 Jun 2019 20:12:48 +0000 (13:12 -0700)]
Add read_aiger to CHANGELOG

5 years agoFix spacing (entire file is wrong anyway, will fix later)
Eddie Hung [Fri, 7 Jun 2019 18:30:36 +0000 (11:30 -0700)]
Fix spacing (entire file is wrong anyway, will fix later)

5 years agoRemove unnecessary std::getline() for ASCII
Eddie Hung [Fri, 7 Jun 2019 18:28:25 +0000 (11:28 -0700)]
Remove unnecessary std::getline() for ASCII

5 years agoTest *.aag too, by using *.aig as reference
Eddie Hung [Fri, 7 Jun 2019 18:28:05 +0000 (11:28 -0700)]
Test *.aag too, by using *.aig as reference

5 years agoFix read_aiger -- create zero driver, fix init width, parse 'b'
Eddie Hung [Fri, 7 Jun 2019 18:07:15 +0000 (11:07 -0700)]
Fix read_aiger -- create zero driver, fix init width, parse 'b'

5 years agoUse ABC to convert from AIGER to Verilog
Eddie Hung [Fri, 7 Jun 2019 18:06:57 +0000 (11:06 -0700)]
Use ABC to convert from AIGER to Verilog

5 years agoUse ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung [Fri, 7 Jun 2019 18:05:36 +0000 (11:05 -0700)]
Use ABC to convert AIGER to Verilog, then sat against Yosys

5 years agoAdd symbols to AIGER test inputs for ABC
Eddie Hung [Fri, 7 Jun 2019 18:05:25 +0000 (11:05 -0700)]
Add symbols to AIGER test inputs for ABC

5 years agoAllow muxcover costs to be changed
Eddie Hung [Fri, 7 Jun 2019 15:30:39 +0000 (08:30 -0700)]
Allow muxcover costs to be changed

5 years agoMerge pull request #1077 from YosysHQ/clifford/pr983
Clifford Wolf [Fri, 7 Jun 2019 11:39:46 +0000 (13:39 +0200)]
Merge pull request #1077 from YosysHQ/clifford/pr983

elaboration system tasks

5 years agoRename implicit_ports.sv test to implicit_ports.v
Clifford Wolf [Fri, 7 Jun 2019 11:12:25 +0000 (13:12 +0200)]
Rename implicit_ports.sv test to implicit_ports.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFixes and cleanups in AST_TECALL handling
Clifford Wolf [Fri, 7 Jun 2019 10:41:09 +0000 (12:41 +0200)]
Fixes and cleanups in AST_TECALL handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
Clifford Wolf [Fri, 7 Jun 2019 10:08:42 +0000 (12:08 +0200)]
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983

5 years agoMerge branch 'tux3-implicit_named_connection'
Clifford Wolf [Fri, 7 Jun 2019 09:53:46 +0000 (11:53 +0200)]
Merge branch 'tux3-implicit_named_connection'

5 years agoMerge pull request #1076 from thasti/centos7-build-fix
Clifford Wolf [Fri, 7 Jun 2019 09:48:33 +0000 (11:48 +0200)]
Merge pull request #1076 from thasti/centos7-build-fix

Fix pyosys-build on CentOS7

5 years agoCleanup tux3-implicit_named_connection
Clifford Wolf [Fri, 7 Jun 2019 09:46:16 +0000 (11:46 +0200)]
Cleanup tux3-implicit_named_connection

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3...
Clifford Wolf [Fri, 7 Jun 2019 09:41:54 +0000 (11:41 +0200)]
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection

5 years agoremove boost/log/exceptions.hpp from wrapper generator
Stefan Biereigel [Fri, 7 Jun 2019 07:47:33 +0000 (09:47 +0200)]
remove boost/log/exceptions.hpp from wrapper generator

5 years agoSystemVerilog support for implicit named port connections
tux3 [Tue, 4 Jun 2019 22:47:54 +0000 (00:47 +0200)]
SystemVerilog support for implicit named port connections

This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.

5 years agoMerge pull request #1060 from antmicro/parsing_attr_on_port_conn
Clifford Wolf [Thu, 6 Jun 2019 10:34:05 +0000 (12:34 +0200)]
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn

Added support for parsing attributes on port connections.

5 years agoMerge pull request #1073 from whitequark/ecp5-diamond-iob
David Shah [Thu, 6 Jun 2019 10:22:49 +0000 (11:22 +0100)]
Merge pull request #1073 from whitequark/ecp5-diamond-iob

ECP5: implement most Diamond I/O buffer primitives

5 years agoECP5: implement all Diamond I/O buffer primitives.
whitequark [Thu, 6 Jun 2019 10:03:03 +0000 (10:03 +0000)]
ECP5: implement all Diamond I/O buffer primitives.

5 years agoMerge pull request #1071 from YosysHQ/eddie/fix_1070
Clifford Wolf [Thu, 6 Jun 2019 04:50:12 +0000 (06:50 +0200)]
Merge pull request #1071 from YosysHQ/eddie/fix_1070

Fix typo in opt_rmdff causing register to be incorrectly removed

5 years agoMerge pull request #1072 from YosysHQ/eddie/fix_1069
Clifford Wolf [Thu, 6 Jun 2019 04:49:07 +0000 (06:49 +0200)]
Merge pull request #1072 from YosysHQ/eddie/fix_1069

Error out if no top module given before 'sim'

5 years agoMissing doc for -tech xilinx in shregmap
Eddie Hung [Wed, 5 Jun 2019 21:21:44 +0000 (14:21 -0700)]
Missing doc for -tech xilinx in shregmap

5 years agoError out if no top module given before 'sim'
Eddie Hung [Wed, 5 Jun 2019 21:16:24 +0000 (14:16 -0700)]
Error out if no top module given before 'sim'

5 years agoFix typo in opt_rmdff
Eddie Hung [Wed, 5 Jun 2019 21:08:14 +0000 (14:08 -0700)]
Fix typo in opt_rmdff

5 years agoMerge pull request #1067 from YosysHQ/clifford/fix1065
Eddie Hung [Wed, 5 Jun 2019 16:59:05 +0000 (09:59 -0700)]
Merge pull request #1067 from YosysHQ/clifford/fix1065

Suppress driver-driver conflict warning for unknown cell types

5 years agoFixed memory leak.
Maciej Kurc [Wed, 5 Jun 2019 08:42:43 +0000 (10:42 +0200)]
Fixed memory leak.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
5 years agoMerge pull request #1066 from YosysHQ/clifford/fix1056
Clifford Wolf [Wed, 5 Jun 2019 08:37:39 +0000 (10:37 +0200)]
Merge pull request #1066 from YosysHQ/clifford/fix1056

Remove yosys_banner() from python wrapper init

5 years agoMajor rewrite of wire selection in setundef -init
Clifford Wolf [Wed, 5 Jun 2019 08:26:48 +0000 (10:26 +0200)]
Major rewrite of wire selection in setundef -init

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoIndent fix
Clifford Wolf [Wed, 5 Jun 2019 07:53:06 +0000 (09:53 +0200)]
Indent fix

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #999 from jakobwenzel/setundefInitFix
Clifford Wolf [Wed, 5 Jun 2019 07:50:15 +0000 (09:50 +0200)]
Merge pull request #999 from jakobwenzel/setundefInitFix

initialize more registers in setundef -init

5 years agoFix typo in fmcombine log message, fixes #1063
Clifford Wolf [Wed, 5 Jun 2019 07:26:44 +0000 (09:26 +0200)]
Fix typo in fmcombine log message, fixes #1063

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoSuppress driver-driver conflict warning for unknown cell types, fixes #1065
Clifford Wolf [Wed, 5 Jun 2019 07:14:12 +0000 (09:14 +0200)]
Suppress driver-driver conflict warning for unknown cell types, fixes #1065

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRemove yosys_banner() from python wrapper init, fixes #1056
Clifford Wolf [Wed, 5 Jun 2019 06:57:33 +0000 (08:57 +0200)]
Remove yosys_banner() from python wrapper init, fixes #1056

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1062 from tux3/patch-1
Clifford Wolf [Tue, 4 Jun 2019 12:37:10 +0000 (14:37 +0200)]
Merge pull request #1062 from tux3/patch-1

README.md: Missing formatting for <tag>

5 years agoREADME.md: Missing formatting for <tag>
Tux3 [Tue, 4 Jun 2019 08:45:41 +0000 (10:45 +0200)]
README.md: Missing formatting for <tag>

5 years agoMoved tests that fail with Icarus Verilog to /tests/various. Those tests are just...
Maciej Kurc [Tue, 4 Jun 2019 08:42:42 +0000 (10:42 +0200)]
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
5 years agoMerge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map
Eddie Hung [Tue, 4 Jun 2019 03:23:37 +0000 (20:23 -0700)]
Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map

Execute techmap and arith_map simultaneously

5 years agoRemove extra newline
Eddie Hung [Tue, 4 Jun 2019 03:04:47 +0000 (20:04 -0700)]
Remove extra newline

5 years agoExecute techmap and arith_map simultaneously
Eddie Hung [Tue, 4 Jun 2019 02:36:09 +0000 (19:36 -0700)]
Execute techmap and arith_map simultaneously

5 years agoAdded tests for attributes
Maciej Kurc [Mon, 3 Jun 2019 07:12:51 +0000 (09:12 +0200)]
Added tests for attributes

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
5 years agoOnly support Symbiotic EDA flavored Verific
Clifford Wolf [Sun, 2 Jun 2019 08:14:50 +0000 (10:14 +0200)]
Only support Symbiotic EDA flavored Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdded support for parsing attributes on port connections.
Maciej Kurc [Fri, 31 May 2019 10:24:12 +0000 (12:24 +0200)]
Added support for parsing attributes on port connections.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
5 years agoFix "tee" handling of log_streams
Clifford Wolf [Fri, 31 May 2019 07:28:51 +0000 (09:28 +0200)]
Fix "tee" handling of log_streams

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoEnable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes...
Clifford Wolf [Thu, 30 May 2019 08:03:54 +0000 (10:03 +0200)]
Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1057 from mmicko/fix_478
Clifford Wolf [Thu, 30 May 2019 07:58:51 +0000 (09:58 +0200)]
Merge pull request #1057 from mmicko/fix_478

Aded one more load of .conf to support change of prefix

5 years agoAded one more load of .conf to support change of prefix
Miodrag Milanovic [Wed, 29 May 2019 16:57:03 +0000 (18:57 +0200)]
Aded one more load of .conf to support change of prefix

5 years agoMerge pull request #1049 from YosysHQ/clifford/fix1047
Clifford Wolf [Tue, 28 May 2019 17:02:26 +0000 (19:02 +0200)]
Merge pull request #1049 from YosysHQ/clifford/fix1047

 Do not use shiftmul peepopt pattern when mul result is truncated

5 years agoMerge pull request #1050 from YosysHQ/clifford/wandwor
Clifford Wolf [Tue, 28 May 2019 15:42:16 +0000 (17:42 +0200)]
Merge pull request #1050 from YosysHQ/clifford/wandwor

Refactored wand/wor support

5 years agoDo not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Clifford Wolf [Tue, 28 May 2019 13:33:47 +0000 (15:33 +0200)]
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1048 from mmicko/fix_enable_pyosys
Clifford Wolf [Tue, 28 May 2019 14:52:40 +0000 (16:52 +0200)]
Merge pull request #1048 from mmicko/fix_enable_pyosys

Moved pyosys block in Makefile

5 years agoRefactor hierarchy wand/wor handling
Clifford Wolf [Tue, 28 May 2019 14:43:25 +0000 (16:43 +0200)]
Refactor hierarchy wand/wor handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd actual wandwor test that is part of "make test"
Clifford Wolf [Tue, 28 May 2019 14:42:50 +0000 (16:42 +0200)]
Add actual wandwor test that is part of "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandwor
Clifford Wolf [Tue, 28 May 2019 13:45:15 +0000 (15:45 +0200)]
Merge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandwor

5 years agoRemove info line in 2nd load of conf file
Miodrag Milanovic [Tue, 28 May 2019 13:43:27 +0000 (15:43 +0200)]
Remove info line in 2nd load of conf file

5 years agoMoved pyosys block in Makefile
Miodrag Milanovic [Tue, 28 May 2019 12:53:07 +0000 (14:53 +0200)]
Moved pyosys block in Makefile

5 years agoMerge pull request #1045 from mmicko/afl-gcc-target
Clifford Wolf [Tue, 28 May 2019 12:00:28 +0000 (14:00 +0200)]
Merge pull request #1045 from mmicko/afl-gcc-target

afl-fuzzer compile config

5 years agomake config-afl-gcc to help creating conf file
Miodrag Milanovic [Mon, 27 May 2019 18:43:10 +0000 (20:43 +0200)]
make config-afl-gcc to help creating conf file

5 years agoAdded afl-gcc as target for fuzzer
Miodrag Milanovic [Mon, 27 May 2019 18:38:44 +0000 (20:38 +0200)]
Added afl-gcc as target for fuzzer

5 years agoMerge branch 'master' into wandwor
Stefan Biereigel [Mon, 27 May 2019 17:07:46 +0000 (19:07 +0200)]
Merge branch 'master' into wandwor

5 years agoreformat wand/wor test
Stefan Biereigel [Mon, 27 May 2019 16:45:54 +0000 (18:45 +0200)]
reformat wand/wor test

5 years agoremove port direction workaround from test case
Stefan Biereigel [Mon, 27 May 2019 16:10:39 +0000 (18:10 +0200)]
remove port direction workaround from test case

5 years agoupdate README.md with wand/wor information
Stefan Biereigel [Mon, 27 May 2019 16:07:12 +0000 (18:07 +0200)]
update README.md with wand/wor information

5 years agoremove leftovers from ast data structures
Stefan Biereigel [Mon, 27 May 2019 16:01:44 +0000 (18:01 +0200)]
remove leftovers from ast data structures

5 years agomove wand/wor resolution into hierarchy pass
Stefan Biereigel [Mon, 27 May 2019 16:00:22 +0000 (18:00 +0200)]
move wand/wor resolution into hierarchy pass

5 years agoMerge pull request #1044 from mmicko/invalid_width_range
Clifford Wolf [Mon, 27 May 2019 11:26:12 +0000 (13:26 +0200)]
Merge pull request #1044 from mmicko/invalid_width_range

Give error instead of asserting for invalid range, fixes #947

5 years agoMerge pull request #1043 from mmicko/unsized_constant
Clifford Wolf [Mon, 27 May 2019 11:25:52 +0000 (13:25 +0200)]
Merge pull request #1043 from mmicko/unsized_constant

Added support for unsized constants, fixes #1022