gallium/targets: fix bool setting on BE architectures

val_bool and val_int are in a union. val_bool gets the first byte, which
happens to work on LE when setting via the int, but breaks on BE. By
setting the value properly, we are able to use DRI3 on BE architectures.
Tested by running glxgears with a NV34 in a G5 PPC.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
[Emil Velikov: squash the vmwgfx hunk]
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

docs: add release calendar page and references to it

Add a page that has information which release is expected when and
associated information.

Reference to it from the "Releasing process" and "Release notes" pages.

v2:
 - Add Andres for 17.0.5
 - Rework table format to include the branch (Eric)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

travis: bump MAKEFLAGS to -j4

The instance should have 2 cores, yet bumping the jobs to 4 should give
us a minor speed improvement.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: enable wayland support

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: add Gallium state-tracker targets

Split into OpenCL and others, since the former is quite time consuming.

v2:
 - explicitly enable/disable components
 - build libvdpau 1.1 requirement
 - enable st/vdpau
 - build libva 1.6.2 (API 0.38) requirement

v3: Drop ubuntu-toolchain-r-test from sources (Andres)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: model scons check target like the make one

Should make things a bit more consistent across the board.

Cc: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: split the make target to three separate ones

Split the target to allow faster builds for each run.

The overall build time will be more, yet Travis runs multiple builds in
parallel so we're limited by the slowest one.

Things are split roughly as:
 - DRI loaders, classic DRI drivers, classic OSMesa, make check
 - All Gallium drivers (minus the SWR) alongside st/dri (mesa)
 - The Vulkan drivers - ANV and RADV, make check (anv)

v2:
 - rework RUN_CHECK to MAKE_CHECK_COMMAND
 - explicitly disable DRI loaders
 - generate linux/memfd.h locally and enable ANV
 - add libedit-dev

v3: Use printf to create the header (Andres).
v4: Really add the libedit + printf hunks.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: add "make swr" to the build matrix

v2: Quote OVERRIDE variables.
v3: Add missplaced libedit-dev hunk (Andres).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: add "scons swr" to the build matrix

Requires GCC 5.0 (due to the C++14 requirement) and LLVM 3.9.

v2: Enable the target, add libedit-dev, rework check target.
v3: Comment the current check target, add -j4 SCONSFLAGS, quote OVERRIDE
variables.
v4: Keep check target as-is (Andres)

Cc: Tim Rowley <timothy.o.rowley@intel.com>
Cc: George Kyriazis <george.kyriazis@intel.com>
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: add separate "scons" and "scons llvm" targets

The former does not require any LLVM, while the latter uses LLVM 3.3.

This way we'll quickly catch any LLVM 3.3+ functionality that gets
introduced where it shouldn't.

Add the full list of addons for each build permutation.

v2: Keep libedit-dev, rework check target.
v3: Comment the current check target, add -j4 SCONSFLAGS
v4:
 - Remove llvm-toolchain-trusty-3.3 source (Andres)
 - Keep check target as-is (Andres)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: split out matrix from env

With next commits we'll add a couple of more options.

v2: Rework check target.
v3: Comment the current check target, add -j4 SCONSFLAGS
v4: Keep check target as-is, will rework with later patch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: rework "if test" blocks in the script section

Split the "if test" blocks so that we get more sensible output in case
of a failure.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: remove unused -dev packages

We effectively override libdrm-dev and libxcb-dri2-0-dev since we build
and install the package locally.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: automatically manage ccache caching

According to the manual

"If you are using ccache, use:

  language: c # or other C/C++ variants

  cache: ccache

to cache $HOME/.ccache and automatically add /usr/lib/ccache to your
$PATH."

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: enable apt cache

Provides a small, but consistent improvement.
Example numbers of the jobs added later in the series.

"make loaders/classic DRI" - 1s
"scons SWR" - 6s

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

travis: add the possibility of using the txc-dxtn library

The txc-dxtn library implements the patented S3 Texture Compression
algorithm.

By default it won't be used but we add the possibility of setting the
USE_TXC_DXTN variable to yes in the travis web UI so it will be
installed and used for the scons tests.

Cc: Eric Anholt <eric@anholt.net>
Cc: Rhys Kidd <rhyskidd@gmail.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
[Emil Velikov: keep the LIB prefix, drop the LD_LIBRARY_PATH, fold URL]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

travis: replace Trusty-based LLVM toolchain apt-get with apt addon

Trusty's LLVM toochain repository was whitelisted some time ago. See:
https://github.com/travis-ci/apt-source-whitelist/commit/479067c5e74cb0c1e2419209179b1afe2edce274

Signed-off-by: Andres Gomez <agomez@igalia.com>
[Emil Velikov]
 - set sudo to false
 - reference the Trusty change (Rhys)
 - keep libedit-dev
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

travis: explicitly LD_LIBRARY_PATH the local libraries

Some of the libraries may be dlopened, which may not always work due to
the non-standard prefix that we're using.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

st/wgl: whitespace, formatting fixes in stw_pixelformat.c

Trivial.

st/wgl: allow WGL_BIND_TO_TEXTURE_RGB_ARB for RGBA visuals

We do not need to restrict WGL_BIND_TO_TEXTURE_RGB_ARB to
RGB visuals only. It can be supported with RGBA visuals as well.

This fixes the early exit of cinebench-r15-test trace.

Tested with cinebench-r15, piglit, glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>

st/wgl: use ARRAY_SIZE() macro in wglChoosePixelFormatARB()

Trivial.

st/wgl: whitespace/formatting fixes in stw_ext_pixelformat.c

Trivial.

svga: implement sRGB rendering for imported surfaces

If texture is imported and templ format is sRGB, use compatible sRGB format
to the imported texture format while creating surface view.

tested with MTT piglit, glretrace, viewperf and conform

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: add function svga_linear_to_srgb()

This function will return compatible svga srgb format for corresponding
linear format

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

glx: add missing sRGB attribute check in fbconfigs_compatible()

This patch will allow driver to choose srgb capable FBconfig
if GLX_FRAMEBUFFER_SRGB_CAPABLE_ARB attribute is 1

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: Add a more elaborate format compatibility determination v2

dri3 is a bit sloppy about its format compatibility requirements, so add
a possibility to import xrgb surfaces as argb textures and vice versa.

At the same time, make the svga_texture_from_handle() function a bit more
readable and fix the error path where we leaked a winsys surface.

v2: Addressed review comments by Brian.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

swr/rast: add memory api to SwrGetInterface()

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: use gather instruction for odd format fetch

Small fetch performance optimization - use gather instruction
for odd format fetch instead of slow emulated code.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: enable SIMD16 8x2 tile backend

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add SwrInit() to init backend/memory tables

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: increment depth/stencil tile pointer in SIMD16 BE

Misplaced #endif preventing depth and stencil hot tile pointers
from incrementing in SIMD16 8x2 configuration of BackendPixelRate.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add SwrGetInterface() function to return api

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: enable per-warp scratch space for CS

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: reduce simd{16}vertex stack for VS output

Frontend - reduce simdvertex/simd16vertex stack usage for VS output in
ProcessDraw, fixes stack overflow in some of the deeper call stacks under
SIMD16.

1. Move the vertex store out of PA_FACTORY, and off the stack
2. Allocate the vertex store out of the aligned heap (pointer is
   temporarily stored in TLS, but will be migrated to thread pool
   along with other frontend temporary buffers).
3. Grow the vertex store as necessary for the number of verts per
   primitive, in chunks of 8/4 simdvertex/simd16vertex

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: remove default argument from SwrSync()

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: remove unused variables in the SIMD16 FE

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: move construction of const above goto

Fixes gcc error for SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: name threads to aid debugging

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: disable buffer overrun warning for Assemble()

Disabling buffer overrun warning for Assemble(uint32_t slot,
simdvector *verts) due to what looks like a MSVC compiler bug
when compiling the SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: clean up clipper comments

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add SIMDAPI decorators in binner/clipper

Fixes MSVC errors with SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add additional jit utility functions

Not used yet.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: more flexible max attribute slots

Ability to allocate space for an arbitrary number (at compile time)
of positions in the vertex layout.

Removes KNOB_NUM_ATTRIBUTES from knobs.h, replaces the VTX slot
number #defines with the SWR_VTX_SLOTS enum (which contains
replacement for NUM_ATTRIBUTES: SWR_VTX_NUM_SLOTS)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

i965: Drop BRW_NEW_CONTEXT from 3DSTATE_DS/GS on Gen7-7.5.

We already have BRW_NEW_BATCH, which completely covers all the cases
that BRW_NEW_CONTEXT would handle.  Drop it.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Drop _NEW_TRANSFORM from 3DSTATE_DS/GS on Gen7-7.5.

There's no reason for this as far as I can tell.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.

Gen4-5 and Gen8+ already set this, but Gen6-7.5 did not.  We ought to
be consistent - the answer depends on the API, not the hardware generation.

The Sandybridge PRM says about RASTRULE_UPPER_RIGHT:

   "To match OpenGL point rasterization rules (round to +infinity, where
    this is the upper right direction wrt OpenGL screen origin of lower
    left).

So this is likely the one we should use.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

i965: Always set AALINEDISTANCE_TRUE on Sandybridge.

We set this unconditionally on every other platform.  Zero (Manhattan)
isn't even listed as an option in the Sandybridge docs - only "true".

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Use true AA line distance on G45/Ironlake.

The original Broadwater and Crestline platforms computed antialiased
line distances using "manhattan" distance, aka a + b = c.  Eaglelake
and Cantiga added "true" distance, which apparently does something
like max(a, b) + min(a, b) / 4.  Not exactly "true", but at least
more accurate.

The G45 documentation indicates that the old manhattan distance setting
is "only for debug purposes" and should never be used.  The Ironlake
documentation no longer mentions AALINEDISTANCE_MANHATTAN, though it
does still contain the narrative about the feature.

At any rate, we should use the more accurate mode.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

docs: add news item and link release notes for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add sha256 checksums for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 6cb65ce2d3689ae7f692f8cf08559109037dd74e)

docs: add release notes for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 61b134a862ecc1877bbe2f2c14e493b5fb607e04)

radeonsi: don't load unused compute shader input SGPRs and VGPRs

Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine
whether to load BLOCK_ID for each component separately, and set the number
of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave
rate in most cases.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

tgsi/scan: record compute shader system value usage

v2: just do indexing with swizzle[i]

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add a HUD query for draw calls with primitive restart

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: tell LLVM not to remove s_barrier instructions

LLVM 5.0 removes s_barrier instructions if the max-work-group-size
attribute is not set. What a surprise.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix tess offchip offset for per-patch attributes

We need 4 more bits there. I don't know what is fixed by this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: pass tessellation ring addresses via user SGPRs

This removes s_load_dword latency for tess rings.

We need just 1 SGPR for the address if we use 64K alignment. The final asm
for recreating the descriptor is:

    // s2 is (address >> 16)
    s_mov_b32 s3, 0
    s_lshl_b64 s[4:5], s[2:3], 16
    s_mov_b32 s6, -1
    s_mov_b32 s7, 0x27fac

v2: bitcast the descriptor type from v2i64 to v4i32

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove VS epilog code, compile VS with PrimID export on demand

The use of PrimID in the pixel shader is too rare to deserve such
a sizable support code.

The initial idea of the VS epilog was to move the clipping code there and
remove it based on states, but optimized variants are now used to do that
and are easier to support, so the VS epilog has turned out to be not so
useful.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3

VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't load PrimID in TES if it's not used

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: explain (non-)monolithic shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable OpenGL 4.5

Tentatively enable it, expecting the scratch buffer support to be done before
the next Mesa release.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1st

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add reference counting for shader selectors

The 2nd shader of merged shaders should take a reference of the 1st shader.
The next commit will do that.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set TES registers for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GS

not implemented yet

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: always compile monolithic ES-GS (asynchronously)

In addition to the non-monolithic variant.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add support for monolithic ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: make sure the 1st shader's main part exists for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: select shader parts for non-monolithic ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add GS prolog support for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add VS prolog support for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: store ES outputs to LDS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: load GS inputs from LDS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: get GS wave ID from the correct input

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add the function signature of merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set registers and shader key for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add GS user SGPRs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rename declare_tess_lds -> declare_lds_as_pointer

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: simplify some shader type conditions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rename the swizzle parameter of lds_store

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add si_shader::prolog2

For a GS prolog in merged ES-GS.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add support for monolithic merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between them

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't store the HS control word

GFX9 doesn't have it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pass inputs from LS to TCS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add TCS epilog support for merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add VS prolog support for merged LS-HS

HS input VGPRs must be reserved.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: merged shaders have scratch offset at the beginning

also, screen wasn't initialized for compute shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: define LS-HS main shader function prototype

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: assign VS/TCS/TES/GS shader input parameter locations dynamically

They will vary with merged stages.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: define and set LS-HS user SGPRs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set up shader registers for merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add initial code generation for non-monolithic merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: separate out code for selecting the VS prolog

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add si_shader::previous_stage for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>