litex.git
5 years agocores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time...
Florent Kermarrec [Fri, 5 Jul 2019 13:49:17 +0000 (15:49 +0200)]
cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency.

5 years agosoc/cores/spi: remove too complicated and does not seem reliable in all cases.
Florent Kermarrec [Fri, 5 Jul 2019 12:37:46 +0000 (14:37 +0200)]
soc/cores/spi: remove too complicated and does not seem reliable in all cases.

5 years agocores: add bitbang class with minimal hardware for I2C/SPI software bit-banging
Florent Kermarrec [Fri, 5 Jul 2019 12:26:10 +0000 (14:26 +0200)]
cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging

5 years agocores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash)
Florent Kermarrec [Fri, 5 Jul 2019 11:13:31 +0000 (13:13 +0200)]
cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash)

5 years agocores/gpio: remove Blinker
Florent Kermarrec [Fri, 5 Jul 2019 11:09:21 +0000 (13:09 +0200)]
cores/gpio: remove Blinker

5 years agoMerge pull request #210 from DurandA/master
Tim Ansell [Thu, 4 Jul 2019 00:23:36 +0000 (17:23 -0700)]
Merge pull request #210 from DurandA/master

Add verilog submodule from CPU cores to manifest

5 years agoAdd verilog submodule from CPU cores to manifest
Arnaud Durand [Wed, 3 Jul 2019 22:58:26 +0000 (00:58 +0200)]
Add verilog submodule from CPU cores to manifest

5 years agocsr: add assert to ensure CSR size < busword (thanks tweakoz)
Florent Kermarrec [Wed, 3 Jul 2019 11:43:34 +0000 (13:43 +0200)]
csr: add assert to ensure CSR size < busword (thanks tweakoz)

5 years agosoc_core: update default RocketChip mem_map
Florent Kermarrec [Fri, 28 Jun 2019 21:40:01 +0000 (23:40 +0200)]
soc_core: update default RocketChip mem_map

5 years agosoc_core: rearrange default mem_map
Florent Kermarrec [Fri, 28 Jun 2019 21:27:23 +0000 (23:27 +0200)]
soc_core: rearrange default mem_map

5 years agobios/main: fix #ifdefs for fw command
Florent Kermarrec [Fri, 28 Jun 2019 20:42:02 +0000 (22:42 +0200)]
bios/main: fix #ifdefs for fw command

5 years agolibnet/tftp: fix compilation warning
Florent Kermarrec [Fri, 28 Jun 2019 20:32:45 +0000 (22:32 +0200)]
libnet/tftp: fix compilation warning

5 years agobios/main: fix spiflash compilation warnings
Florent Kermarrec [Fri, 28 Jun 2019 20:18:24 +0000 (22:18 +0200)]
bios/main: fix spiflash compilation warnings

5 years agosoc_sdram: allow main_ram_size > 256MB (limitation no longer exists)
Florent Kermarrec [Thu, 27 Jun 2019 21:32:23 +0000 (23:32 +0200)]
soc_sdram: allow main_ram_size > 256MB (limitation no longer exists)

5 years agotargets: use new prefered way to add wishbone slave
Florent Kermarrec [Thu, 27 Jun 2019 21:28:12 +0000 (23:28 +0200)]
targets: use new prefered way to add wishbone slave

5 years agosoc_core: use new way to add wisbone slave (now prefered)
Florent Kermarrec [Thu, 27 Jun 2019 21:20:12 +0000 (23:20 +0200)]
soc_core: use new way to add wisbone slave (now prefered)

5 years agosoc_core: remove 256MB mem_map limitation
Florent Kermarrec [Thu, 27 Jun 2019 21:07:26 +0000 (23:07 +0200)]
soc_core: remove 256MB mem_map limitation

mem_map was limited to 8 256MB for simplicity but has become an issue for
complex SoCs. Default mem_map size is still 256MB (retro-compatibility) but
size can now be specified.

5 years agosoc/core: remove #!/usr/bin/env python3
Florent Kermarrec [Fri, 28 Jun 2019 19:37:52 +0000 (21:37 +0200)]
soc/core: remove #!/usr/bin/env python3

5 years agoMerge pull request #206 from gsomlo/gls-tftp-spinner
enjoy-digital [Thu, 27 Jun 2019 15:02:29 +0000 (17:02 +0200)]
Merge pull request #206 from gsomlo/gls-tftp-spinner

BIOS: TFTP: ASCII spinner progress indicator (cosmetic)

5 years agoBIOS: TFTP: ASCII spinner progress indicator (cosmetic)
Gabriel L. Somlo [Thu, 27 Jun 2019 14:31:33 +0000 (10:31 -0400)]
BIOS: TFTP: ASCII spinner progress indicator (cosmetic)

5 years agoMerge pull request #204 from antmicro/write_to_flash
enjoy-digital [Tue, 25 Jun 2019 17:10:17 +0000 (19:10 +0200)]
Merge pull request #204 from antmicro/write_to_flash

fw (flash write) command

5 years agocore/spi_flash: re-integrate bitbang write support
Florent Kermarrec [Tue, 25 Jun 2019 17:09:30 +0000 (19:09 +0200)]
core/spi_flash: re-integrate bitbang write support

5 years agobios: add fw (flash write) command
Mateusz Holenko [Tue, 25 Jun 2019 09:59:22 +0000 (11:59 +0200)]
bios: add fw (flash write) command

5 years agoREADME: remove LiteUSB (deprecated)
Florent Kermarrec [Mon, 24 Jun 2019 13:40:32 +0000 (15:40 +0200)]
README: remove LiteUSB (deprecated)

5 years agoboards: community supported boards are now located at https://github.com/litex-hub...
Florent Kermarrec [Mon, 24 Jun 2019 10:05:02 +0000 (12:05 +0200)]
boards: community supported boards are now located at https://github.com/litex-hub/litex-boards

5 years agoliteeth: update mac imports (olds still works, but that's now the prefered way)
Florent Kermarrec [Mon, 24 Jun 2019 09:44:41 +0000 (11:44 +0200)]
liteeth: update mac imports (olds still works, but that's now the prefered way)

5 years agosoc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB
Florent Kermarrec [Mon, 24 Jun 2019 08:58:36 +0000 (10:58 +0200)]
soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB

LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.

5 years agoREADME: update Intro
Florent Kermarrec [Mon, 24 Jun 2019 07:59:10 +0000 (09:59 +0200)]
README: update Intro

5 years agomake sure #!/usr/bin/env python3 is before copyright header
Florent Kermarrec [Mon, 24 Jun 2019 05:29:24 +0000 (07:29 +0200)]
make sure #!/usr/bin/env python3 is before copyright header

5 years agotest: add copyright header
Florent Kermarrec [Sun, 23 Jun 2019 21:31:11 +0000 (23:31 +0200)]
test: add copyright header

5 years agoadd CONTRIBUTORS file and add copyright header to all files
Florent Kermarrec [Sun, 23 Jun 2019 20:36:00 +0000 (22:36 +0200)]
add CONTRIBUTORS file and add copyright header to all files

5 years agobios/sdram: set init_done/error when DDRCTRL is present (litedram_gen)
Florent Kermarrec [Sat, 22 Jun 2019 08:53:12 +0000 (10:53 +0200)]
bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen)

5 years agoConvert top level comment to a docstring.
Tim 'mithro' Ansell [Fri, 21 Jun 2019 19:03:30 +0000 (12:03 -0700)]
Convert top level comment to a docstring.

5 years agoMerge pull request #202 from xobs/add-up5kspram
enjoy-digital [Fri, 21 Jun 2019 08:26:07 +0000 (10:26 +0200)]
Merge pull request #202 from xobs/add-up5kspram

soc: cores: add up5kspram module

5 years agosoc: cores: add up5kspram module
William D. Jones [Thu, 20 Jun 2019 18:12:46 +0000 (11:12 -0700)]
soc: cores: add up5kspram module

The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
5 years agocores/frequency_meter: allow passing clk to be measured as a parameter
Florent Kermarrec [Thu, 20 Jun 2019 07:02:08 +0000 (09:02 +0200)]
cores/frequency_meter: allow passing clk to be measured as a parameter

5 years agoMerge pull request #201 from gsomlo/gls-fix-initmem
enjoy-digital [Wed, 19 Jun 2019 06:32:38 +0000 (08:32 +0200)]
Merge pull request #201 from gsomlo/gls-fix-initmem

tools/litex_sim: fix default endianness for mem_init

5 years agotools/litex_sim: fix default endianness for mem_init
Gabriel L. Somlo [Tue, 18 Jun 2019 20:29:23 +0000 (16:29 -0400)]
tools/litex_sim: fix default endianness for mem_init

Initializing ROM and/or RAM content requires knowing the CPU
endianness before the SimSoC->SoCSDRAM->SoCCore constructor
sequence is invoked (before the SoC's self.cpu.endianness
could be accessed). Given that the majority of supported CPU
models use "little", set it as the new default, and override
only for the two models that use "big" endianness.

5 years agoMerge pull request #200 from gsomlo/gls-rocket-variants
enjoy-digital [Tue, 18 Jun 2019 11:15:30 +0000 (13:15 +0200)]
Merge pull request #200 from gsomlo/gls-rocket-variants

cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants

5 years agocpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants
Gabriel L. Somlo [Tue, 18 Jun 2019 10:42:40 +0000 (06:42 -0400)]
cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants

5 years agocpu/rocket: update submodule
Florent Kermarrec [Tue, 18 Jun 2019 07:44:09 +0000 (09:44 +0200)]
cpu/rocket: update submodule

5 years agointegration/soc_core: move cpu_variant checks/formating to cpu
Florent Kermarrec [Mon, 17 Jun 2019 07:55:27 +0000 (09:55 +0200)]
integration/soc_core: move cpu_variant checks/formating to cpu

5 years agocpu/vexriscv: add "linux+no-dsp" variant
Florent Kermarrec [Mon, 17 Jun 2019 07:54:17 +0000 (09:54 +0200)]
cpu/vexriscv: add "linux+no-dsp" variant

5 years agocpu/vexriscv: update
Florent Kermarrec [Mon, 17 Jun 2019 07:24:57 +0000 (09:24 +0200)]
cpu/vexriscv: update

5 years agotargets/ulx3s: use CAS latency of 3 to be compatible with production boards
Florent Kermarrec [Mon, 17 Jun 2019 07:20:21 +0000 (09:20 +0200)]
targets/ulx3s: use CAS latency of 3 to be compatible with production boards

5 years agoMerge pull request #199 from ambrop72/no-ethmac-fix
enjoy-digital [Thu, 13 Jun 2019 05:14:03 +0000 (07:14 +0200)]
Merge pull request #199 from ambrop72/no-ethmac-fix

bios: Fix build when ethphy is present but ethmac is not.

5 years agobios: Fix build when ethphy is present but ethmac is not.
Ambroz Bizjak [Wed, 12 Jun 2019 23:02:22 +0000 (01:02 +0200)]
bios: Fix build when ethphy is present but ethmac is not.

While testing my Ethernet DMA, I renamed the `ethmac` module to `ethmac_dma` so that it wouldn't be used from the BIOS, but I got an undefined reference to `eth_init` because `bios.c` checks different CSR defines than the code that defines `eth_init`.

5 years agotest/test_axi: remove litex.gen.sim import (was only useful for debug)
Florent Kermarrec [Wed, 12 Jun 2019 09:28:06 +0000 (11:28 +0200)]
test/test_axi: remove litex.gen.sim import (was only useful for debug)

5 years agosetup.py: add migen to install_requires
Florent Kermarrec [Wed, 12 Jun 2019 09:26:57 +0000 (11:26 +0200)]
setup.py: add migen to install_requires

5 years agoMerge pull request #198 from TomKeddie/tomk_20190610_artyspi
enjoy-digital [Tue, 11 Jun 2019 13:50:02 +0000 (15:50 +0200)]
Merge pull request #198 from TomKeddie/tomk_20190610_artyspi

boards/arty : Add directly connected spi clk pin

5 years agotest/test_code8b10b: add test_coding
Florent Kermarrec [Mon, 10 Jun 2019 16:53:30 +0000 (18:53 +0200)]
test/test_code8b10b: add test_coding

5 years agoboards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2
Tom Keddie [Mon, 10 Jun 2019 15:33:02 +0000 (08:33 -0700)]
boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2

5 years agotest/test_prbs: add PRBSGenerator/Checker tests
Florent Kermarrec [Mon, 10 Jun 2019 14:05:53 +0000 (16:05 +0200)]
test/test_prbs: add PRBSGenerator/Checker tests

5 years agosoc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker
Florent Kermarrec [Mon, 10 Jun 2019 14:05:36 +0000 (16:05 +0200)]
soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker

Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.

5 years agotools/litex_term: exit on 2 consecutive CTRL-C
Florent Kermarrec [Mon, 10 Jun 2019 13:06:57 +0000 (15:06 +0200)]
tools/litex_term: exit on 2 consecutive CTRL-C

When running OS with LiteX and when LiteXTerm is use, we want to be able to
send CTRl-C to the OS. Ensure a specific sequence is sent to close the terminal.

5 years agocpu/vexriscv: update submodule
Florent Kermarrec [Mon, 10 Jun 2019 10:57:10 +0000 (12:57 +0200)]
cpu/vexriscv: update submodule

5 years agodoc: add litex-hub logo
Florent Kermarrec [Sun, 9 Jun 2019 17:36:09 +0000 (19:36 +0200)]
doc: add litex-hub logo

5 years agodoc: redesign new logo
Florent Kermarrec [Sat, 8 Jun 2019 22:36:46 +0000 (00:36 +0200)]
doc: redesign new logo

5 years agodoc: add new logo
Florent Kermarrec [Fri, 7 Jun 2019 22:45:30 +0000 (00:45 +0200)]
doc: add new logo

5 years agocpu/vexriscv: update submodule
Florent Kermarrec [Fri, 7 Jun 2019 16:36:46 +0000 (18:36 +0200)]
cpu/vexriscv: update submodule

5 years agobuild/sim: allow configuring verilator optimization level
Florent Kermarrec [Fri, 7 Jun 2019 10:28:20 +0000 (12:28 +0200)]
build/sim: allow configuring verilator optimization level

5 years agobuild/sim: allow defining start/end cycles for tracing
Florent Kermarrec [Fri, 7 Jun 2019 09:50:57 +0000 (11:50 +0200)]
build/sim: allow defining start/end cycles for tracing

5 years agobuild/sim: use -O0 for verilator compilation
Florent Kermarrec [Fri, 7 Jun 2019 09:16:39 +0000 (11:16 +0200)]
build/sim: use -O0 for verilator compilation

In most of the case, execution speed is already fast enough with -O0 and
with complex design -O0 is a lost faster to compile than -O3. In the future
we could add a switch to choose which optimization we want.

5 years agosoc/integration/soc_core: list rocket as supported CPU
Florent Kermarrec [Fri, 7 Jun 2019 09:14:36 +0000 (11:14 +0200)]
soc/integration/soc_core: list rocket as supported CPU

5 years agosoftware/bios: change prompt to "litex" in green.
Florent Kermarrec [Fri, 7 Jun 2019 09:10:04 +0000 (11:10 +0200)]
software/bios: change prompt to "litex" in green.

5 years agointegration/soc_core: improve readibility (add separators/comments)
Florent Kermarrec [Wed, 5 Jun 2019 21:43:16 +0000 (23:43 +0200)]
integration/soc_core: improve readibility (add separators/comments)

5 years agotest/test_targets: add de10lite
Florent Kermarrec [Wed, 5 Jun 2019 18:03:19 +0000 (20:03 +0200)]
test/test_targets: add de10lite

5 years agoMerge pull request #196 from msloniewski/de10lite_support
enjoy-digital [Wed, 5 Jun 2019 17:44:54 +0000 (19:44 +0200)]
Merge pull request #196 from msloniewski/de10lite_support

De10lite support

5 years agoMerge pull request #195 from antmicro/extend_generated_headers
enjoy-digital [Wed, 5 Jun 2019 17:20:15 +0000 (19:20 +0200)]
Merge pull request #195 from antmicro/extend_generated_headers

Extend generated headers & csv

5 years agoboards/targets: add target for de10lite platform
msloniewski [Wed, 5 Jun 2019 16:53:49 +0000 (18:53 +0200)]
boards/targets: add target for de10lite platform

5 years agoboards/platforms: add de10lite Terasic platform support
msloniewski [Wed, 5 Jun 2019 16:53:30 +0000 (18:53 +0200)]
boards/platforms: add de10lite Terasic platform support

5 years agobuild/altera: Add possibility to turn off generation of .rbf file
msloniewski [Wed, 5 Jun 2019 16:52:40 +0000 (18:52 +0200)]
build/altera: Add possibility to turn off generation of .rbf file

For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.

5 years agointegration/builder: generate flash_boot address to csv
Mateusz Holenko [Wed, 5 Jun 2019 15:27:27 +0000 (17:27 +0200)]
integration/builder: generate flash_boot address to csv

5 years agointegration/builder: generate shadow_base address to mem.h and csv
Mateusz Holenko [Wed, 5 Jun 2019 15:35:47 +0000 (17:35 +0200)]
integration/builder: generate shadow_base address to mem.h and csv

5 years agoMerge pull request #193 from gsomlo/gls-memcpy-fix
enjoy-digital [Tue, 4 Jun 2019 19:49:18 +0000 (21:49 +0200)]
Merge pull request #193 from gsomlo/gls-memcpy-fix

software/libbase: memcpy: simple, arch-width agnostic implementation

5 years agosoftware/libbase: memcpy: simple, arch-width agnostic implementation
Gabriel L. Somlo [Tue, 4 Jun 2019 18:42:54 +0000 (14:42 -0400)]
software/libbase: memcpy: simple, arch-width agnostic implementation

Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.

Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agoMerge pull request #192 from sutajiokousagi/pr_c99_types
Tim Ansell [Sun, 2 Jun 2019 23:54:20 +0000 (16:54 -0700)]
Merge pull request #192 from sutajiokousagi/pr_c99_types

fix signed char type to be explicitly signed

5 years agofix signed char type to be explicitly signed
bunnie [Mon, 3 Jun 2019 06:00:27 +0000 (06:00 +0000)]
fix signed char type to be explicitly signed

5 years agoupdate stdint.h to include c99 types
bunnie [Sun, 2 Jun 2019 22:26:18 +0000 (22:26 +0000)]
update stdint.h to include c99 types

needed for some third party libraries to compile

5 years agoMerge pull request #191 from sergachev/master
Tim Ansell [Sun, 2 Jun 2019 20:00:20 +0000 (13:00 -0700)]
Merge pull request #191 from sergachev/master

Fix interrupt_name in soc_core/add_interrupt

5 years agofix csr_name in add_csr()
Ilia Sergachev [Sun, 2 Jun 2019 18:56:02 +0000 (20:56 +0200)]
fix csr_name in add_csr()

5 years agofix interrupt_name
Ilia Sergachev [Sun, 2 Jun 2019 18:48:08 +0000 (20:48 +0200)]
fix interrupt_name

5 years agotest/test_targets: add de2_115, de1soc
Florent Kermarrec [Sun, 2 Jun 2019 17:22:09 +0000 (19:22 +0200)]
test/test_targets: add de2_115, de1soc

5 years agoboards/platform/arty: add Arty A7-100 variant
Florent Kermarrec [Sun, 2 Jun 2019 17:10:44 +0000 (19:10 +0200)]
boards/platform/arty: add Arty A7-100 variant

5 years agoMerge pull request #189 from open-design/terasic-boards
enjoy-digital [Sun, 2 Jun 2019 16:40:57 +0000 (18:40 +0200)]
Merge pull request #189 from open-design/terasic-boards

Add support for Terasic DE2-115 and Terasic DE1-SoC boards

5 years agoMerge pull request #190 from sutajiokousagi/pr_c99_types
Tim Ansell [Sun, 2 Jun 2019 15:15:52 +0000 (08:15 -0700)]
Merge pull request #190 from sutajiokousagi/pr_c99_types

update stdint.h to include c99 types

5 years agoboards: add Terasic DE2-115 initial support
Antony Pavlov [Mon, 27 May 2019 08:17:51 +0000 (11:17 +0300)]
boards: add Terasic DE2-115 initial support

See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=1
for board details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
5 years agoboards: add Terasic DE1-SoC Board support
Antony Pavlov [Wed, 29 May 2019 06:12:48 +0000 (09:12 +0300)]
boards: add Terasic DE1-SoC Board support

See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
for board details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
5 years agoMerge pull request #188 from gsomlo/gls-csr-cleanup
enjoy-digital [Thu, 30 May 2019 20:40:39 +0000 (22:40 +0200)]
Merge pull request #188 from gsomlo/gls-csr-cleanup

Miscellaneous cleanup patches

5 years agosoc/integration/cpu_interface: improve code legibility
Gabriel L. Somlo [Wed, 29 May 2019 14:07:43 +0000 (10:07 -0400)]
soc/integration/cpu_interface: improve code legibility

Factor out code appearing in both branches of an if/else.

5 years agosoc/interconnect/gearbox: add msb_first/lsb_first order
Florent Kermarrec [Wed, 29 May 2019 08:25:25 +0000 (10:25 +0200)]
soc/interconnect/gearbox: add msb_first/lsb_first order

5 years agoboards/targets/arty: generate 25MHz ethernet clock with S7PLL
Florent Kermarrec [Tue, 28 May 2019 07:55:06 +0000 (09:55 +0200)]
boards/targets/arty: generate 25MHz ethernet clock with S7PLL

Allow ethernet to work when sys_clk_freq != 100MHz

5 years agoMerge pull request #187 from open-design/indent
Tim Ansell [Sun, 26 May 2019 10:01:31 +0000 (03:01 -0700)]
Merge pull request #187 from open-design/indent

litex/boards/targets: don't use tab for indentation

5 years agolitex/boards/targets: don't use tab for indentation
Antony Pavlov [Sun, 26 May 2019 08:59:13 +0000 (11:59 +0300)]
litex/boards/targets: don't use tab for indentation

Fix pep8 E101 "indentation contains mixed spaces and tab" error.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
5 years agosoc/interconnect/axi: add round/robin arbitration between writes/reads
Florent Kermarrec [Sat, 25 May 2019 08:02:31 +0000 (10:02 +0200)]
soc/interconnect/axi: add round/robin arbitration between writes/reads

5 years agotravis: update RISC-V toolchain
Florent Kermarrec [Sat, 25 May 2019 07:30:54 +0000 (09:30 +0200)]
travis: update RISC-V toolchain

5 years agobios/irc: remove compilation workaround
Florent Kermarrec [Sat, 25 May 2019 07:24:48 +0000 (09:24 +0200)]
bios/irc: remove compilation workaround

5 years agoREADME: update RISC-V toolchain
Florent Kermarrec [Sat, 25 May 2019 07:24:25 +0000 (09:24 +0200)]
README: update RISC-V toolchain

5 years ago.gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog
Florent Kermarrec [Fri, 24 May 2019 08:39:48 +0000 (10:39 +0200)]
.gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog

5 years agosoftware/bios/isr.c: workaround compilation issue (need to be fixed)
Florent Kermarrec [Fri, 24 May 2019 08:13:24 +0000 (10:13 +0200)]
software/bios/isr.c: workaround compilation issue (need to be fixed)