Remove split_shiftx call

Revert "Merge branch 'eddie/split_shiftx' into xc7mux"

This reverts commit 3042d5833041021bb45252b0cc862e9eff3d27d3, reversing
changes made to feff9764540cbf1152459cb377fc68d8e10c7153.

Missing newline

Add -undef option to equiv_opt, passed to equiv_induct

Actually use pm.st.shiftxB

Cleanup superseded

bitblast_shiftx -> split_shiftx

Fix for when B_WIDTH has trailing zeroes

Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux

In order to indicate a failed pattern, blacklist?

Add test

Elaborate on help message

Merge branch 'eddie/split_shiftx' into xc7mux

Add split_shiftx command

Make pmgen support files more generic

synth_xilinx to call bitblast_shiftx

Misspelling

Remove topo sort no-loop assertion, with test

Add -nocarry option to synth_xilinx

Fix abc9 with (* keep *) wires

Refactor into AigerReader::post_process()

Merge pull request #957 from YosysHQ/oai4fix

Fixes for OAI4 cell implementation

Fixes for OAI4 cell implementation

Fixes #955 and the underlying issue in #954

Signed-off-by: David Shah <dave@ds0.me>

Format some names using inline code

Fix spelling

Remove some left-over log_dump()

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Tweak

Fix for A_WIDTH == 2 but B_WIDTH==3

Trim A_WIDTH by Y_WIDTH-1

Add comment

Fix for mux_case_* mappings

Fix for non-pow2 width muxes

Merge pull request #914 from YosysHQ/xc7srl

synth_xilinx to now infer SRL16E/SRLC32E

Add synth_xilinx -nomux option

Cleanup, call pmux2shiftx even without -nosrl

Merge branch 'xaig' into xc7mux

Temporarily remove 'r' extension

Merge remote-tracking branch 'origin/xc7srl' into xc7mux

Update help message

Allow POs to be PIs in XAIG

Remove kernel/cost.cc since master has refactored it

Merge remote-tracking branch 'origin/master' into xaig

Merge pull request #952 from YosysHQ/clifford/fix370

Determine correct signedness and expression width in for-loop unrolling

Merge pull request #951 from YosysHQ/clifford/logdebug

Add log_debug() framework

Merge pull request #949 from YosysHQ/clifford/pmux2shimprove

Add full_pmux feature to pmux2shiftx

Merge pull request #953 from YosysHQ/clifford/fix948

Add support for zero-width signals to Verilog back-end

Move 'shregmap -tech xilinx' into map_cells

Add support for zero-width signals to Verilog back-end, fixes #948

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/master' into xc7srl

Determine correct signedness and expression width in for loop unrolling, fixes #370

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add log_debug() framework

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #950 from whitequark/attrmap_remove_wildcard

attrmap: extend -remove to allow removing attributes with any value

attrmap: extend -remove to allow removing attributes with any value.

Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.

Updaye pmux2shiftx test

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add full_pmux feature to pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Set ENABLE_LIBYOSYS=0 by default

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Set ENABLE_PYOSYS=0 by default

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #905 from christian-krieg/feature/python_bindings

Feature/python bindings

Merge pull request #941 from Wren6991/sim_lib_io_clke

ice40 cells_sim.v: update clock enable behaviour based on hardware experiments

Merge branch 'dh73-master'

Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master

Re-added clean after techmap in synth_xilinx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #916 from YosysHQ/map_cells_before_map_luts

synth_xilinx to map_cells before map_luts

Merge pull request #911 from mmicko/gowin-nobram

Make nobram false by default for gowin

Merge pull request #909 from zachjs/master

support repeat loops with constant repeat counts outside of constant functions

Merge pull request #944 from YosysHQ/clifford/pmux2shiftx

Add pmux2shiftx command

Merge pull request #945 from YosysHQ/clifford/libwb

New behavior for read_verilog handling of whiteboxes

Merge remote-tracking branch 'origin/clifford/libwb' into xaig

Disable blackbox detection in techmap files

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Tidy up, fix for -nosrl

Convert to use #945

Merge remote-tracking branch 'origin/clifford/libwb' into xaig

Merge branch 'map_cells_before_map_luts' into xc7srl

Merge branch 'master' into map_cells_before_map_luts

Add comments

Use new pmux2shiftx from #944, remove my old attempt

ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments

Fix tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "noblackbox" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/clifford/pmux2shiftx' into xc7srl

Merge remote-tracking branch 'origin/master' into xc7srl

New behavior for front-end handling of whiteboxes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/master' into xaig

Merge pull request #943 from YosysHQ/clifford/whitebox

[WIP] Add "whitebox" attribute, add "read_verilog -wb"

Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl

Merge remote-tracking branch 'origin' into xc7srl

Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "onehot" pass, improve "pmux2shiftx" onehot handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "techmap -wb", use in formal flows

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Check blackbox attribute in techmap/simplemap

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "wbflip" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #942 from YosysHQ/clifford/fix931

Improve proc full_case detection and handling

ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set

Improve "pmux2shiftx"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix some typos

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in "pmux2shiftx"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Select to find union of both sets on stack

Fixes for simple_abc9 tests

Improvements in pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add test for pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>