Steve Reinhardt [Tue, 19 Dec 2006 07:11:48 +0000 (02:11 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
4bd4f8bb8e48e09562a2d9ae6eb7d061be973c5e
Ali Saidi [Tue, 19 Dec 2006 07:11:47 +0000 (02:11 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
fa8ce7149973245a73bb562b9378db13be647a14
Ali Saidi [Tue, 19 Dec 2006 07:11:33 +0000 (02:11 -0500)]
fix twinx loads a little bit
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle
src/arch/sparc/isa/formats/mem/blockmem.isa:
twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
fix the fault check for twinx
src/arch/sparc/tlb.cc:
tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
don't halt on a couple more instruction (ldx, stx) when things differ
beacuse of the way tlb faults are handled in legion.
--HG--
extra : convert_revision :
1e156dead6ebd58b257213625ed63c3793ef4b71
Steve Reinhardt [Tue, 19 Dec 2006 07:07:52 +0000 (23:07 -0800)]
Streamline Cache/Tags interface: get rid of redundant functions,
don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.
--HG--
extra : convert_revision :
171018aa6e331d98399c4e5ef24e173c95eaca28
Steve Reinhardt [Tue, 19 Dec 2006 05:53:06 +0000 (21:53 -0800)]
No need to template prefetcher on cache TagStore type.
--HG--
rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc
extra : convert_revision :
56c0b51e424a3a6590332dba4866e69a1ad19598
Steve Reinhardt [Tue, 19 Dec 2006 04:47:12 +0000 (20:47 -0800)]
Get rid of generic CacheTags object (fold back into Cache).
--HG--
extra : convert_revision :
8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
Nathan Binkert [Mon, 18 Dec 2006 22:08:42 +0000 (14:08 -0800)]
Fix unittest compiles
--HG--
extra : convert_revision :
1163437081e1f1eab3f4512d04317dc94a673b9b
Nathan Binkert [Mon, 18 Dec 2006 22:07:52 +0000 (14:07 -0800)]
cast chars to int when we want to print integers so we get a number
instead of a character
--HG--
extra : convert_revision :
7bfa88ba23ad057b751eb01a80416d9f72cfe81a
Ali Saidi [Mon, 18 Dec 2006 08:37:52 +0000 (03:37 -0500)]
move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD
src/arch/sparc/isa/decoder.isa:
move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
Make QUAD_LDD asi ok to execute
--HG--
extra : convert_revision :
2a44d1c9e4edb627079fc05776c28d918c8508ce
Nathan Binkert [Mon, 18 Dec 2006 02:58:50 +0000 (18:58 -0800)]
Nate's utility for compiling m5
--HG--
extra : convert_revision :
84b21f667736dfe07891323dcc810437ccb3c7c0
Nathan Binkert [Mon, 18 Dec 2006 02:58:05 +0000 (18:58 -0800)]
Utilities for doing a format check for some elements of proper
m5 style and fixing whitespace. For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.
--HG--
extra : convert_revision :
d0591663c028a388635fc71c6c1d31f700748cf6
Gabe Black [Sun, 17 Dec 2006 16:16:04 +0000 (11:16 -0500)]
Compilation fixes.
--HG--
extra : convert_revision :
4932ab507580e0c9f7012398e71921ce58fc3c4e
Gabe Black [Sun, 17 Dec 2006 16:15:37 +0000 (11:15 -0500)]
Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.
--HG--
extra : convert_revision :
5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
Gabe Black [Sat, 16 Dec 2006 17:55:55 +0000 (12:55 -0500)]
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
c8718b3df72b8c951c24742e8ce517a93bc23fe9
Gabe Black [Sat, 16 Dec 2006 17:55:15 +0000 (12:55 -0500)]
Merge zizzer:/bk/sparcfs/
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
2764b356ef01d1fcb6ed272e4ef96179cd651d4e
Gabe Black [Sat, 16 Dec 2006 17:54:28 +0000 (12:54 -0500)]
Support for twin loads.
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision :
ad42821a97dcda17744875b1e5dc00a9642e59b7
Gabe Black [Sat, 16 Dec 2006 17:53:01 +0000 (12:53 -0500)]
Compiler error fix.
--HG--
extra : convert_revision :
39e2638a10bf3e821e8f3d4d8c664008c98fc921
Lisa Hsu [Fri, 15 Dec 2006 23:07:39 +0000 (18:07 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
a6a40a3bc2e07bc7828de08fa2ce1c847105483d
Lisa Hsu [Fri, 15 Dec 2006 23:02:23 +0000 (18:02 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
68e9bb607fbeb1ed0ea4192411e804dc8e6ddd95
Lisa Hsu [Fri, 15 Dec 2006 22:58:20 +0000 (17:58 -0500)]
small change to eliminate address range overlap.
--HG--
extra : convert_revision :
c8309a8774265a707c87c4f516bec1f81aff4a79
Lisa Hsu [Fri, 15 Dec 2006 22:55:47 +0000 (17:55 -0500)]
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.
src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
pioSize indicates SIZE, not a mask
--HG--
extra : convert_revision :
d385521fcfe58f8dffc8622260937e668a47a948
Lisa Hsu [Fri, 15 Dec 2006 18:27:53 +0000 (13:27 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
Lisa Hsu [Fri, 15 Dec 2006 18:06:37 +0000 (13:06 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
92a865a90a7c3e251ed1443f79640f761b359c1d
Lisa Hsu [Fri, 15 Dec 2006 18:05:46 +0000 (13:05 -0500)]
some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
--HG--
extra : convert_revision :
c5b9d56ab99018a91d04de47ba1d5ca7768590bb
Lisa Hsu [Fri, 15 Dec 2006 18:01:06 +0000 (13:01 -0500)]
loadstore.isa:
this privilegedString is never used
--HG--
extra : convert_revision :
5e6881d467792b670e0009cee8d5e96bc7a79a95
Lisa Hsu [Fri, 15 Dec 2006 17:58:02 +0000 (12:58 -0500)]
tlb.cc:
fix namespace indentations
src/arch/alpha/tlb.cc:
fix namespace indentations
--HG--
extra : convert_revision :
327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
Ali Saidi [Fri, 15 Dec 2006 06:49:41 +0000 (01:49 -0500)]
Use my range_map to speed up findPort() in the bus. The snoop code could still use some work.
--HG--
extra : convert_revision :
ba0a68bd378d68e4ebd80a101b965d36c8be1db9
Ali Saidi [Fri, 15 Dec 2006 06:48:09 +0000 (01:48 -0500)]
Optimized the TLB translations with some caching
--HG--
extra : convert_revision :
f79f863393f918ff9363b2c261f8c0dfec64312e
Ali Saidi [Fri, 15 Dec 2006 00:01:21 +0000 (19:01 -0500)]
flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
src/arch/sparc/asi.cc:
flesh out twinx asis
src/arch/sparc/miscregfile.cc:
fix TICK register reads
src/arch/sparc/tlb.cc:
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
--HG--
extra : convert_revision :
1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
Steve Reinhardt [Thu, 14 Dec 2006 06:04:36 +0000 (22:04 -0800)]
Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
--HG--
extra : convert_revision :
cb1b88246c95b36aa0cf26d534127d3714ddb774
Lisa Hsu [Wed, 13 Dec 2006 22:52:24 +0000 (17:52 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
8cf3e824e4892249b12ed0fd92bb310748b18fa2
Lisa Hsu [Wed, 13 Dec 2006 22:51:28 +0000 (17:51 -0500)]
fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG--
extra : convert_revision :
4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
Lisa Hsu [Wed, 13 Dec 2006 19:33:59 +0000 (14:33 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
Lisa Hsu [Wed, 13 Dec 2006 19:33:32 +0000 (14:33 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
c6d174716641f0b8286b8478bcb9053b3eec54e3
Lisa Hsu [Wed, 13 Dec 2006 02:19:51 +0000 (21:19 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
6e58629b1e51f1fc493a89f16c3f2e676dc5d191
Kevin Lim [Tue, 12 Dec 2006 22:55:50 +0000 (17:55 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
--HG--
extra : convert_revision :
d420ee86454b72b0e5d3a98bac3b496f172c1788
Ali Saidi [Tue, 12 Dec 2006 22:55:27 +0000 (17:55 -0500)]
Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case
--HG--
extra : convert_revision :
70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
Kevin Lim [Tue, 12 Dec 2006 22:35:46 +0000 (17:35 -0500)]
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly. The eon benchmark should run now.
src/cpu/o3/iew_impl.hh:
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
--HG--
extra : convert_revision :
b7d202dee1754539ed814f0fac59adb8c6328ee1
Steve Reinhardt [Tue, 12 Dec 2006 17:58:40 +0000 (09:58 -0800)]
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG--
extra : convert_revision :
b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
Steve Reinhardt [Tue, 12 Dec 2006 17:54:59 +0000 (09:54 -0800)]
If no tests are specified for regression, just build the binaries
(instead of complaining and exiting).
--HG--
extra : convert_revision :
24ac0bab7fd92d9e74c80847a667f0affcd0473d
Steve Reinhardt [Tue, 12 Dec 2006 07:21:03 +0000 (02:21 -0500)]
Get rid of unused lock code.
--HG--
extra : convert_revision :
a8030132268662ca54f487b8d32d09ba224317a8
Kevin Lim [Tue, 12 Dec 2006 04:51:21 +0000 (23:51 -0500)]
Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation).
--HG--
extra : convert_revision :
43f4ea5e6a234cc6071006eab72135c11b8523c8
Kevin Lim [Tue, 12 Dec 2006 04:47:30 +0000 (23:47 -0500)]
Fix for fetch to use the icache's block size to generate proper access size.
--HG--
extra : convert_revision :
0f292233ac05b584f527c32f80e3ca3d40a6a2c1
Steve Reinhardt [Sun, 10 Dec 2006 07:05:33 +0000 (02:05 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
--HG--
extra : convert_revision :
c961d1bf2acaae6807870b78f444a4a606be65cc
Steve Reinhardt [Sun, 10 Dec 2006 07:04:53 +0000 (02:04 -0500)]
Reorder CacheTags members for better cache performance.
--HG--
extra : convert_revision :
cac6e9d447675805e3fcc4342e3bfdbef179fbf5
Steve Reinhardt [Sun, 10 Dec 2006 06:52:18 +0000 (01:52 -0500)]
Get rid of dummy 'hello world' outputs.
--HG--
extra : convert_revision :
e03634b5ec6b3c855c463618968984b5df7782f9
Steve Reinhardt [Sun, 10 Dec 2006 06:50:12 +0000 (01:50 -0500)]
Delete parser reference outputs so that test will no longer be run.
Runtimes are way too long with current inputs.
--HG--
extra : convert_revision :
19323308b40fb7de00c77ee552e39ca6558804b8
Steve Reinhardt [Sun, 10 Dec 2006 06:42:31 +0000 (01:42 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
--HG--
extra : convert_revision :
7c78ae3298645aed2179ed4f2aa361619406f9de
Steve Reinhardt [Sun, 10 Dec 2006 06:42:16 +0000 (01:42 -0500)]
Add '-j' option directly to regress script (passed to scons).
--HG--
extra : convert_revision :
9776806b24da70b815280e47d2d5ec8674c82669
Steve Reinhardt [Sun, 10 Dec 2006 06:05:30 +0000 (22:05 -0800)]
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
e1ed5c8edb95e99200b4d26317f55f71338a96df
Ali Saidi [Sat, 9 Dec 2006 23:27:54 +0000 (18:27 -0500)]
fix lisa's hand merge
--HG--
extra : convert_revision :
d25604156ae0b2cf29d92fb960b8f5d77427985b
Ali Saidi [Sat, 9 Dec 2006 23:00:49 +0000 (18:00 -0500)]
Merge zizzer:/bk/sparcfs
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
c51fd95f7acd7cffb3ea705d7216772f0a801844
Ali Saidi [Sat, 9 Dec 2006 23:00:40 +0000 (18:00 -0500)]
Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision :
d7d771900f6f25219f3dc6a6e51986d342a32e03
Lisa Hsu [Fri, 8 Dec 2006 20:07:26 +0000 (15:07 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge
--HG--
extra : convert_revision :
5157fa5d7053cb93f73241c63871eaae6f58b8a6
Lisa Hsu [Fri, 8 Dec 2006 19:37:31 +0000 (14:37 -0500)]
mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
--HG--
extra : convert_revision :
d12d1147b508121075ee9be4599693554d4b9eae
Ali Saidi [Thu, 7 Dec 2006 23:50:33 +0000 (18:50 -0500)]
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
--HG--
extra : convert_revision :
ed5dfdfb28633bf36e5ae07d244f7510a02874ca
Steve Reinhardt [Thu, 7 Dec 2006 19:41:56 +0000 (14:41 -0500)]
Change detault regression build from opt to fast.
--HG--
extra : convert_revision :
b6db0254b73a97ab6e3685c90cc9cd30ea274d4f
Ali Saidi [Thu, 7 Dec 2006 00:25:53 +0000 (19:25 -0500)]
Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
--HG--
extra : convert_revision :
7a14450485816e6ee3bc8c80b462a13e1edf0ba0
Ali Saidi [Wed, 6 Dec 2006 19:29:10 +0000 (14:29 -0500)]
Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision :
1e11aa004e8f42c156e224c1d30d49479ebeed28
Kevin Lim [Wed, 6 Dec 2006 19:23:31 +0000 (14:23 -0500)]
Fix for MIPS_SE/m5.fast compile.
--HG--
extra : convert_revision :
dbb893250974ac6db7b6c1ba67263fd35098ca43
Kevin Lim [Tue, 5 Dec 2006 16:12:18 +0000 (11:12 -0500)]
Override default SConscript options and only build the SimpleCPUs.
--HG--
extra : convert_revision :
cfcfb787d8442cb76ed766aa5bc947636f067209
Steve Reinhardt [Tue, 5 Dec 2006 15:24:13 +0000 (07:24 -0800)]
Merge zizzer.eecs.umich.edu:bk/newmem-cache2
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
0a7d17460f17c96fe869124f54f9c92409495003
Steve Reinhardt [Tue, 5 Dec 2006 15:23:20 +0000 (10:23 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
a5569cef10ab22da1865e368f0bb5e7532772227
Steve Reinhardt [Tue, 5 Dec 2006 15:18:35 +0000 (10:18 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
ca78bf2fc1ddefd56b98a90eaffab57d93026626
Steve Reinhardt [Tue, 5 Dec 2006 15:16:36 +0000 (07:16 -0800)]
Don't compress data on writebacks unless it's actually necessary.
--HG--
extra : convert_revision :
7a068e28f9ea2f6aab57be7133b47bda72d10302
Steve Reinhardt [Tue, 5 Dec 2006 05:35:48 +0000 (21:35 -0800)]
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
e456687d940c833d8255a88633555778480f7825
Ali Saidi [Tue, 5 Dec 2006 01:29:55 +0000 (20:29 -0500)]
forgot to commit miscreg file
--HG--
extra : convert_revision :
c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
Gabe Black [Tue, 5 Dec 2006 00:56:04 +0000 (19:56 -0500)]
Merge zizzer:/bk/sparcfs
into zower.eecs.umich.edu:/eecshome/m5/newmemmid
--HG--
extra : convert_revision :
45d9599dd883e10c283812c1c241c20323f44cec
Gabe Black [Tue, 5 Dec 2006 00:55:52 +0000 (19:55 -0500)]
Add in code to pass the ASI to translation.
--HG--
extra : convert_revision :
4a985635cda7680abcddaf0bc9579fa03d5bc7c6
Lisa Hsu [Tue, 5 Dec 2006 00:39:58 +0000 (19:39 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
3186d6055794b41c26eb8d2411903869b5b39329
Ali Saidi [Tue, 5 Dec 2006 00:39:57 +0000 (19:39 -0500)]
reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes)
Protect other pieces of code so that sparc compiles SE again
src/arch/sparc/SConscript:
Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
protect legion code so it doesn't try to compile under se
--HG--
extra : convert_revision :
6b3c9f6f95b4da8544525f4f82e92861383ede76
Lisa Hsu [Tue, 5 Dec 2006 00:37:50 +0000 (19:37 -0500)]
automatically build sparc system or alpha system.
configs/example/fs.py:
make it an automatic system build for alpha vs. sparc.
--HG--
extra : convert_revision :
4c217cf9309c6209be7f80e358f6640857a785e8
Steve Reinhardt [Tue, 5 Dec 2006 00:10:50 +0000 (16:10 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision :
df2b33a629ae4298c4da33383b491e3cbefab92d
Steve Reinhardt [Tue, 5 Dec 2006 00:07:00 +0000 (19:07 -0500)]
Update SPEC CPU2000 tests with actual benchmark output.
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.out:
tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-timing/stderr:
tests/long/30.eon/ref/alpha/linux/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout:
Update with actual benchmark output.
--HG--
extra : convert_revision :
12e8de58172dd717d9cc8c5c27dd926a7257153c
Steve Reinhardt [Tue, 5 Dec 2006 00:05:09 +0000 (19:05 -0500)]
Only update stderr, stdout, m5stats.txt, and config.* on update_ref,
since we don't know which of the other files are outputs and which
are inputs.
--HG--
extra : convert_revision :
b038bd15930721ab9fceb0a18ab5c895aacb5309
Steve Reinhardt [Mon, 4 Dec 2006 23:57:17 +0000 (18:57 -0500)]
Clean up SPEC CPU2000 reference files.
Get rid of reference files for o3-atomic (non-existent configuration)
and mcf (doesn't seem to be working).
Left in empty refs for parser/simple-timing... this appears to be
dying because it's running out of memory, so maybe it will be OK
once we get the memory leak fixed.
--HG--
extra : convert_revision :
ae3bc8dfec44d09a2a084da5041ec386fe16be8b
Ali Saidi [Mon, 4 Dec 2006 23:25:21 +0000 (18:25 -0500)]
delete m5stats which shouldn't have been commited
--HG--
extra : convert_revision :
cc9f65c94145e957ea96e0b765ae2ea0ae093029
Ali Saidi [Mon, 4 Dec 2006 23:22:55 +0000 (18:22 -0500)]
Legion actually writes to tl-1 in the data structure, so we need to compare correctly
--HG--
extra : convert_revision :
60fef1bd5dc03d7b107150dba922dd4a3f51626f
Lisa Hsu [Mon, 4 Dec 2006 22:51:07 +0000 (17:51 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
3bce43982689e9bda3a12e21a24b5ea390f347b8
Steve Reinhardt [Mon, 4 Dec 2006 17:10:53 +0000 (09:10 -0800)]
Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.
--HG--
extra : convert_revision :
fce0fbd041149b9c781eb23f480ba84fddbfd4a0
Steve Reinhardt [Mon, 4 Dec 2006 17:09:36 +0000 (09:09 -0800)]
Better handling of scons -u targets.
--HG--
extra : convert_revision :
7bf0688a1c83d8385b77a59a1c75040e9624c0ae
Steve Reinhardt [Mon, 4 Dec 2006 16:59:53 +0000 (08:59 -0800)]
SConstruct:
Couple minor fixes.
SConstruct:
Couple minor fixes.
--HG--
extra : convert_revision :
25f3c12570287334c2cbd1cf9b8227043a57e7d1
Steve Reinhardt [Mon, 4 Dec 2006 16:55:06 +0000 (08:55 -0800)]
import os.path.join as joinpath
--HG--
extra : convert_revision :
200612675e49908b9ff9c965aede35a657241391
Ali Saidi [Mon, 4 Dec 2006 05:54:40 +0000 (00:54 -0500)]
More changes to get SPARC fs closer. Now at 1.2M cycles before difference
configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller
--HG--
extra : convert_revision :
8024ae07b765a04ff6f600e5875b55d8a7d3d276
Steve Reinhardt [Sun, 3 Dec 2006 06:26:40 +0000 (22:26 -0800)]
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
321f7fcc8bd6c6aaaab92d10172814f4d07d5e65
Steve Reinhardt [Sun, 3 Dec 2006 06:24:52 +0000 (22:24 -0800)]
Support better param conversions to/from numeric subclasses.
--HG--
extra : convert_revision :
2ccb75b0912a384789458710fd9bbb65626f839e
Steve Reinhardt [Sun, 3 Dec 2006 06:23:46 +0000 (22:23 -0800)]
Fix help strings on GenRepl params.
--HG--
extra : convert_revision :
520814e193b9e86b6410f3ab98d62ed131d295aa
Steve Reinhardt [Sun, 3 Dec 2006 06:22:58 +0000 (22:22 -0800)]
Make cache compression policy a runtime virtual thing
instead of a template policy.
--HG--
extra : convert_revision :
6a4ac7a189a950390a973fdfce94f56190de92db
Steve Reinhardt [Sun, 3 Dec 2006 06:12:26 +0000 (22:12 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision :
4a077b463b938c54b546b00e586d8609c24ae465
Steve Reinhardt [Sun, 3 Dec 2006 06:11:24 +0000 (01:11 -0500)]
Delete src/oldmem.
util/make_release.py:
src/oldmem gone from repo, no need to delete here.
--HG--
extra : convert_revision :
570fa1b8d7144376cf13a010160a39d1c1cccbc2
Steve Reinhardt [Sun, 3 Dec 2006 03:52:26 +0000 (19:52 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision :
4c8de6e4c6f729c83e92abd81ea6c1347e647756
Kevin Lim [Sat, 2 Dec 2006 18:33:46 +0000 (13:33 -0500)]
Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch_impl.hh:
Fixes for MIPS_SE compile.
--HG--
extra : convert_revision :
fde9616f8e72b397c5ca965774172372cff53790
Lisa Hsu [Sat, 2 Dec 2006 16:11:58 +0000 (11:11 -0500)]
stats update
--HG--
extra : convert_revision :
b47d3817d204a43e0afb89aafc8dacf619c3f910
Nathan Binkert [Sat, 2 Dec 2006 06:33:18 +0000 (22:33 -0800)]
don't blow away the whole destination directory
--HG--
extra : convert_revision :
7370bad15cc30e75ebb0c8685324d8db06fc2936
Lisa Hsu [Fri, 1 Dec 2006 20:04:48 +0000 (15:04 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
07119747d9b08ea51f21942e36f22afcc62f16e1
Lisa Hsu [Fri, 1 Dec 2006 18:51:49 +0000 (13:51 -0500)]
change this to be a quick one so that it's in the regressions every night - it's only maybe 15 min. long.
tests/configs/twosys-tsunami-simple-atomic.py:
don't need this import
--HG--
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
rename : tests/long/80.netperf-stream/test.py => tests/quick/80.netperf-stream/test.py
extra : convert_revision :
68497b2ef8b21590cb6c636485703e46dc616513
Lisa Hsu [Fri, 1 Dec 2006 06:24:16 +0000 (01:24 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
b62ca8009105aad7173bdbc5d528de243d21a82c
Lisa Hsu [Fri, 1 Dec 2006 06:24:01 +0000 (01:24 -0500)]
add a simple netperf-stream test to the long tests.
tests/SConscript:
add a new configuration for two-system tests (atomic simple only)
--HG--
extra : convert_revision :
16c260ab16f38779fe17b1cab18f36d5c7a70846
Nathan Binkert [Fri, 1 Dec 2006 04:53:30 +0000 (20:53 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/m5/incoming
--HG--
extra : convert_revision :
05060a06e0b6d66a9c1e7005c233047c6e8ba15f
Nathan Binkert [Fri, 1 Dec 2006 04:50:47 +0000 (20:50 -0800)]
Get rid of the old release-edits script and create make_release.py
which takes care of almost everything needed for putting together
a release.
--HG--
extra : convert_revision :
b05d418a1002633b1286591eb8a8588ba33f5df1