Jason Ekstrand [Fri, 15 Jan 2016 04:42:47 +0000 (20:42 -0800)]
i965/fs: Always set hannel 2 of texture headers in some stages
Jason Ekstrand [Fri, 15 Jan 2016 04:27:51 +0000 (20:27 -0800)]
i965/fs/generator: Take an actual shader stage rather than a string
Jason Ekstrand [Fri, 15 Jan 2016 02:58:25 +0000 (18:58 -0800)]
anv/apply_pipeline_layout: Stomp texture array size to 1
Jason Ekstrand [Fri, 15 Jan 2016 02:40:35 +0000 (18:40 -0800)]
nir/spirv: Fix texture return types
We were just hard-coding everything to a vec4. This meant we weren't
handling shadow samplers at all and integer things were getting the wrong
return type.
Kristian Høgsberg Kristensen [Thu, 14 Jan 2016 23:18:40 +0000 (15:18 -0800)]
vk: Fix struct field indentation
Chad Versace [Thu, 14 Jan 2016 21:18:40 +0000 (13:18 -0800)]
anv: Document anv_cmd_state::current_pipeline
It's the value of PIPELINE_SELECT.PipelineSelection.
Chad Versace [Thu, 14 Jan 2016 21:12:35 +0000 (13:12 -0800)]
anv: Make vkBeginCommandBuffer reset the command buffer
If its the command buffer's first call to vkBeginCommandBuffer, we must
*initialize* the command buffer's state. Otherwise, we must *reset* its
state. In both cases, let's use anv_ResetCommandBuffer.
From the Vulkan 1.0 spec:
If a command buffer is in the executable state and the command buffer
was allocated from a command pool with the
VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
vkBeginCommandBuffer implicitly resets the command buffer, behaving
as if vkResetCommandBuffer had been called with
VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
the command buffer in the recording state.
Chad Versace [Thu, 14 Jan 2016 20:58:46 +0000 (12:58 -0800)]
anv: Add FIXME for vkResetCommandPool
vkResetCommandPool currently destroys its command buffers. The Vulkan
1.0 spec requires that it only reset them:
Resetting a command pool recycles all of the resources from all of
the command buffers allocated from the command pool back to the
command pool. All command buffers that have been allocated from the
command pool are put in the initial state.
Chad Versace [Thu, 14 Jan 2016 03:37:40 +0000 (19:37 -0800)]
anv: Remove duplicate func prototype
anv_private.h declared anv_cmd_buffer_begin_subpass twice.
Chad Versace [Mon, 11 Jan 2016 23:05:47 +0000 (15:05 -0800)]
anv/meta: Add FINISHME for clearing multi-layer framebuffers
Jason Ekstrand [Thu, 14 Jan 2016 20:04:20 +0000 (12:04 -0800)]
i965/vec4: Use UW type for multiply into accumulator on GEN8+
BDW adds the following restriction: "When multiplying DW x DW, the dst
cannot be accumulator."
Jason Ekstrand [Thu, 14 Jan 2016 19:36:17 +0000 (11:36 -0800)]
Merge remote-tracking branch 'mesa-public/master' into vulkan
This fixes the bitfieldextract and bitfieldinsert CTS tests
Ilia Mirkin [Thu, 14 Jan 2016 18:44:54 +0000 (13:44 -0500)]
st/mesa: use surface format to generate mipmaps when available
This fixes the recently posted mipmap + texture views piglit test.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Wed, 13 Jan 2016 17:42:02 +0000 (18:42 +0100)]
radeonsi: don't miss changes to SPI_TMPRING_SIZE
I'm not sure about the consequences of this bug, but it's definitely
dangerous.
This applies to SI, CIK, VI.
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Charmaine Lee [Tue, 22 Dec 2015 19:20:41 +0000 (11:20 -0800)]
svga: add DXGenMips command support
For those formats that support hw mipmap generation, use the
DXGenMips command. Otherwise fallback to the mipmap generation utility.
Tested with piglit, OpenGL apps (Heaven, Turbine, Cinebench)
v2: make sure the texture surface was created with the render target bind flag
set relocation flag to SVGA_RELOC_WRITE for the texture surface
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Charmaine Lee [Mon, 21 Dec 2015 19:07:08 +0000 (11:07 -0800)]
svga: add num-generate-mipmap HUD query
The actual increment of the num-generate-mipmap counter will be done
in a subsequent patch when hw generate mipmap is supported.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Charmaine Lee [Thu, 14 Jan 2016 17:22:17 +0000 (10:22 -0700)]
gallium/st: add pipe_context::generate_mipmap()
This patch adds a new interface to support hardware mipmap generation.
PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify
if this new interface is supported; if not supported, the state tracker will
fallback to mipmap generation by rendering/texturing.
v2: add PIPE_CAP_GENERATE_MIPMAP to the disabled section for all drivers
v3: add format to the generate_mipmap interface to allow mipmap generation
using a format other than the resource format
v4: fix return type of trace_context_generate_mipmap()
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 14 Jan 2016 17:38:17 +0000 (10:38 -0700)]
st/mesa: declare struct pipe_screen in st_cb_bufferobjects.h
To silence a compiler warning. Trivial.
Matt Turner [Wed, 13 Jan 2016 19:09:11 +0000 (11:09 -0800)]
nir: Lower bitfield_extract.
The OpenGL specifications for bitfieldExtract() says:
The result will be undefined if <offset> or <bits> is negative, or if
the sum of <offset> and <bits> is greater than the number of bits
used to store the operand.
Therefore passing bits=32, offset=0 is legal and defined in GLSL.
But the earlier SM5 ubfe/ibfe opcodes are specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits
of the width operand, making them not able to implement the GLSL-specified
behavior directly.
This commit adds ubfe/ibfe operations from SM5 and a lowering pass for
bitfield_extract to to handle the trivial case of <bits> = 32 as
bitfieldExtract:
bits > 31 ? value : bfe(value, offset, bits)
Fixes:
ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
Matt Turner [Wed, 13 Jan 2016 19:08:37 +0000 (11:08 -0800)]
nir: Handle <bits>=32 case in bitfield_insert lowering.
The OpenGL specifications for bitfieldInsert() says:
The result will be undefined if <offset> or <bits> is negative, or if
the sum of <offset> and <bits> is greater than the number of bits
used to store the operand.
Therefore passing bits=32, offset=0 is legal and defined in GLSL.
But the earlier SM5 bfi opcode is specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low
5 bits of the width operand, making them not able to implement the
GLSL-specified behavior directly.
This commit fixes the lowering of bitfield_insert to handle the trivial
case of <bits> = 32 as
bitfieldInsert:
bits > 31 ? insert : bfi(bfm(bits, offset), insert, base)
Fixes:
ES31-CTS.shader_bitfield_operation.bitfieldInsert.uint_2
ES31-CTS.shader_bitfield_operation.bitfieldInsert.uvec4_3
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
Jason Ekstrand [Thu, 14 Jan 2016 17:12:32 +0000 (09:12 -0800)]
nir/spirv: Add initial support for Vertex/Instance index
Jason Ekstrand [Thu, 14 Jan 2016 16:37:54 +0000 (08:37 -0800)]
vulkan.h: Pull in 1.0.1 header
Jason Ekstrand [Thu, 14 Jan 2016 16:10:07 +0000 (08:10 -0800)]
vulkan-1.0.0: Bump the version to 1.0.0
Jason Ekstrand [Thu, 14 Jan 2016 16:09:39 +0000 (08:09 -0800)]
vulkan-1.0.0: Rework memory barriers
Brian Paul [Wed, 13 Jan 2016 23:20:09 +0000 (16:20 -0700)]
st/mesa: add check for color logicop in blit_copy_pixels()
We check that a bunch of raster operations are disabled in
blit_copy_pixels(). We also need to check that color logicop is
disabled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Thu, 14 Jan 2016 16:02:44 +0000 (08:02 -0800)]
vulkan-1.0.0: No-op WSI changes
Jason Ekstrand [Thu, 14 Jan 2016 16:00:18 +0000 (08:00 -0800)]
vulkan-1.0.0: Make extents unsigned
Jason Ekstrand [Thu, 14 Jan 2016 15:59:37 +0000 (07:59 -0800)]
vulkan-1.0.0: Rework blits to use four offsets
Jason Ekstrand [Thu, 14 Jan 2016 15:45:15 +0000 (07:45 -0800)]
vulkan-1.0.0: Split out command buffer inheritance info
Jason Ekstrand [Thu, 14 Jan 2016 15:43:05 +0000 (07:43 -0800)]
vulkan-1.0.0: Re-order some structs in the header
Jason Ekstrand [Thu, 14 Jan 2016 15:41:45 +0000 (07:41 -0800)]
vulkan-1.0.0: Misc. field and argument renames
Jason Ekstrand [Thu, 14 Jan 2016 15:32:16 +0000 (07:32 -0800)]
vulkan-1.0.0: Get rid of MIPMAP_MODE_BASE
Jason Ekstrand [Thu, 14 Jan 2016 15:29:58 +0000 (07:29 -0800)]
vulkan-1.0.0: Convert pPreserveAttachments to a uint32_t
Jason Ekstrand [Thu, 14 Jan 2016 14:58:11 +0000 (06:58 -0800)]
anv/device: Update features and limits
Jason Ekstrand [Thu, 14 Jan 2016 14:50:18 +0000 (06:50 -0800)]
anv/cmd_buffer: Fix setting of viewport/scissor count
Jason Ekstrand [Thu, 7 Jan 2016 03:48:57 +0000 (19:48 -0800)]
anv/state: Respect SamplerCreateInfo.anisotropyEnable
Jason Ekstrand [Thu, 7 Jan 2016 03:27:10 +0000 (19:27 -0800)]
anv/image: Fill out VkSubresourceLayout.arrayPitch
BogDan Vatra [Tue, 5 Jan 2016 19:44:16 +0000 (21:44 +0200)]
WIP: Partially upgrade to vulkan v0.221.0
TODO, make use of:
- VkPhysicalDeviceFeatures.drawIndirectFirstInstance,
- VkPhysicalDeviceFeatures.inheritedQueries
- VkPhysicalDeviceLimits.timestampComputeAndGraphics
- VkSubmitInfo.pWaitDstStageMask
- VkSubresourceLayout.arrayPitch
- VkSamplerCreateInfo.anisotropyEnable
Nicolai Hähnle [Tue, 12 Jan 2016 14:29:18 +0000 (09:29 -0500)]
gallium/radeon: do not reallocate user memory buffers
The whole point of AMD_pinned_memory is that applications don't have to map
buffers via OpenGL - but they're still allowed to, so make sure we don't break
the link between buffer object and user memory unless explicitly instructed
to.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 14 Jan 2016 14:41:04 +0000 (09:41 -0500)]
gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFER
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 11 Jan 2016 00:54:44 +0000 (19:54 -0500)]
gallium/radeon: reset valid_buffer_range on PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
This accomodates a streaming pattern where the discard flag is set when the
application wraps back to the beginning of the buffer.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 9 Jan 2016 23:05:58 +0000 (18:05 -0500)]
st/mesa: implement Driver.InvalidateBufferSubData
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 11 Jan 2016 22:44:45 +0000 (17:44 -0500)]
st/mesa: use pipe->invalidate_resource instead of buffer re-allocation
Drivers are expected to avoid unnecessary work when possible in this code
path.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 11 Jan 2016 22:38:08 +0000 (17:38 -0500)]
gallium: add PIPE_CAP_INVALIDATE_BUFFER
It makes sense to re-use pipe->invalidate_resource for the purpose of
glInvalidateBufferData, but this function is already implemented in vc4
where it doesn't have the expected behavior. So add a capability flag
to indicate that the driver supports the expected behavior.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 9 Jan 2016 22:53:07 +0000 (17:53 -0500)]
mesa: add Driver.InvalidateBufferSubData
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Sat, 9 Jan 2016 22:51:39 +0000 (17:51 -0500)]
mesa: fix the checks in _mesa_InvalidateBuffer(Sub)Data
Change the check to be in line with what the quoted spec fragment says.
I have sent out a piglit test for this as well.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Tue, 12 Jan 2016 17:28:11 +0000 (12:28 -0500)]
winsys/radeon: fix warnings about incompatible pointer types
Some confusion between pb_buffer and radeon_bo as well as between
radeon_drm_winsys and radeon_winsys.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Neil Roberts [Wed, 13 Jan 2016 19:28:45 +0000 (19:28 +0000)]
texobj: Check completeness with InternalFormat rather than Mesa format
The internal Mesa format used for a texture might not match the one
requested in the internalFormat when the texture was created, for
example if the driver is internally remapping RGB textures to RGBA.
Otherwise it can cause false positives for completeness if one mipmap
image is created as RGBA and the other as RGB because they would both
have an RGBA Mesa format. If we check the InternalFormat instead then
we are directly checking the API usage which I think better matches
the intention of the check.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93700
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jordan Justen [Tue, 12 Jan 2016 05:53:35 +0000 (21:53 -0800)]
nir/spirv: Add support for ArrayLength op
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 13 Jan 2016 23:09:45 +0000 (15:09 -0800)]
nir/spirv/alu: Properly implement mod/rem
Jason Ekstrand [Wed, 13 Jan 2016 23:09:00 +0000 (15:09 -0800)]
i965: Implement nir_op_irem and nir_op_srem
Ben Widawsky [Wed, 30 Dec 2015 17:47:17 +0000 (09:47 -0800)]
i965: Remove unused hw_must_use_separate_stencil
I spotted this while looking for what needs updating in future platforms.
I'm too lazy to go through the git logs, but it was probably missed by Jason
when all the brw refactoring happened.
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 14 Jan 2016 00:17:26 +0000 (16:17 -0800)]
i965: Drop extra newline from shader compile messages.
Ilia changed shader-db's run.c to not expect messages to contain a
newline in shader-db commit
51bbc8035.
Jason Ekstrand [Wed, 13 Jan 2016 23:05:39 +0000 (15:05 -0800)]
nir: Add more modulus and remainder opcodes
SPIR-V makes a distinction between "modulus" and "remainder" for both
floating-point and signed integer variants. The difference is primarily
one of which source they take their sign from. The "remainder" opcode for
integers is equivalent to the C/C++ "%" operation while the "modulus"
opcode is more mathematically correct (at least for an unsigned divisor).
This commit adds corresponding opcodes to NIR.
Jason Ekstrand [Wed, 13 Jan 2016 04:02:04 +0000 (20:02 -0800)]
nir/spirv: Add support for OpSpecConstantOp
Jason Ekstrand [Wed, 13 Jan 2016 01:16:48 +0000 (17:16 -0800)]
nir/spirv/alu: Factor out the opcode table
Jason Ekstrand [Wed, 13 Jan 2016 00:30:43 +0000 (16:30 -0800)]
anv/pipeline: Pass through specialization constants
Jason Ekstrand [Wed, 13 Jan 2016 00:28:28 +0000 (16:28 -0800)]
nir/spirv: Add initial support for specialization constants
Matt Turner [Fri, 8 Jan 2016 00:16:35 +0000 (16:16 -0800)]
nir: Change bfm's semantics to match Intel/AMD/SM5.
Intel/AMD's hardware instructions do not handle arguments of 32.
Constant evaluation should not produce a result different from the
hardware instruction.
The s/1ull/1u/ change is intentional: previously we wanted defined
behavior for the "1 << 32" case, but we're making this case undefined so
we can make it 1u and save ourselves a 64-bit operation.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 30 Dec 2015 19:48:22 +0000 (14:48 -0500)]
glsl: Fix undefined shifts.
Shifting into the sign bit is undefined, as is shifting by 32.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Mon, 11 Jan 2016 18:54:19 +0000 (10:54 -0800)]
glsl: Handle failure of Python codegen scripts.
If a Python codegen script failed, it would write a zero-byte file,
which on subsequent invocations of make would trick it into thinking the
file was appropriately generated.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 8 Jan 2016 00:01:51 +0000 (16:01 -0800)]
glsl, nir: Make ir_triop_bitfield_extract a vectorized operation.
We would like to be able to combine
result.x = bitfieldExtract(src0.x, src1.x, src2.x);
result.y = bitfieldExtract(src0.y, src1.y, src2.y);
result.z = bitfieldExtract(src0.z, src1.z, src2.z);
result.w = bitfieldExtract(src0.w, src1.w, src2.w);
into a single ivec4 bitfieldInsert operation. This should be possible
with most drivers.
This patch changes the offset and bits parameters from scalar ints
to ivecN or uvecN. The type of all three operands will be the same,
for simplicity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Tue, 5 Jan 2016 12:01:11 +0000 (04:01 -0800)]
glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.
We would like to be able to combine
result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x);
result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y);
result.z = bitfieldInsert(src0.z, src1.z, src2.z, src3.z);
result.w = bitfieldInsert(src0.w, src1.w, src2.w, src3.w);
into a single ivec4 bitfieldInsert operation. This should be possible
with most drivers.
This patch changes the offset and bits parameters from scalar ints
to ivecN or uvecN. The type of all four operands will be the same,
for simplicity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Thu, 7 Jan 2016 23:54:16 +0000 (15:54 -0800)]
glsl: Delete the ir_binop_bfm and ir_triop_bfi opcodes.
TGSI doesn't use these - it just translates ir_quadop_bitfield_insert
directly. NIR can handle ir_quadop_bitfield_insert as well.
These opcodes were only used for i965, and with Jason's recent patches,
we can do this lowering in NIR (which also gains us SPIR-V handling).
So there's not much point to retaining this GLSL IR lowering code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 11 Jan 2016 20:13:24 +0000 (12:13 -0800)]
nir: Fix constant evaluation of bfm.
NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's
ir_binop_bfm takes <bits> as src0 and <offset> as src1.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 11 Jan 2016 17:34:50 +0000 (09:34 -0800)]
i965/fs: Skip assertion on NaN.
A shader in Unreal4 uses the result of divide by zero in its color
output, producing NaN and triggering this assertion since NaN is not
equal to itself.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93560
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Fri, 27 Feb 2015 00:06:45 +0000 (16:06 -0800)]
i965/fs: Add debugging to constant combining pass.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Brian Paul [Tue, 12 Jan 2016 15:46:40 +0000 (08:46 -0700)]
meta: remove const qualifier on _mesa_meta_fb_tex_blit_begin()
To silence a compiler warning about a const/non-const mismatch.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Tue, 12 Jan 2016 01:22:50 +0000 (18:22 -0700)]
st/mesa: fix incorrect buffer token passed to _mesa_BindFramebuffer()
I added this code right at the end, and got it wrong.
Only used by the WGL_ARB_render_texture code.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Emil Velikov [Wed, 13 Jan 2016 13:27:50 +0000 (15:27 +0200)]
docs: add news item and link release notes for 11.1.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Wed, 13 Jan 2016 13:23:53 +0000 (15:23 +0200)]
docs: add sha256 checksums for 11.1.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
4b2d9f29e9b75cbbeb76ccf753a256e11f07ee1a)
Emil Velikov [Wed, 13 Jan 2016 10:11:33 +0000 (12:11 +0200)]
docs: add release notes for 11.1.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
330aa44a0da7548000a6b2fc2bb580e9c8e733cc)
Neil Roberts [Thu, 19 Nov 2015 15:25:21 +0000 (16:25 +0100)]
i965/gen9: Don't allow the RGBX formats for texturing/rendering
The RGBX surface formats aren't renderable so we internally remap them
to RGBA when rendering. They are retained as RGBX when used as
textures. However since the previous patch fast clears are disabled
for surfaces that use a different format for rendering than for
texturing. To avoid this situation we can just pretend not to support
RGBX formats at all. This will cause the upper layers of mesa to pick
an RGBA format internally instead. This should be safe because we
always override the alpha component to 1.0 for RGBX in the texture
swizzle anyway. We could also do this for all gens except that it's a
bit more difficult when the hardware doesn't support texture
swizzling. Gens using the blorp have further problems because that
doesn't implement this swizzle override.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Marek Olšák [Sat, 2 Jan 2016 22:09:58 +0000 (23:09 +0100)]
radeonsi: move POSITION and FACE fragment shader inputs to system values
And FACE becomes integer instead of float.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Marek Olšák [Thu, 7 Jan 2016 19:00:34 +0000 (20:00 +0100)]
radeonsi: simplify gl_FragCoord behavior
It will become a system value, not an input.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Samuel Iglesias Gonsálvez [Tue, 5 Jan 2016 12:21:17 +0000 (13:21 +0100)]
glsl: add image_format check in cross_validate_globals()
Fixes CTS test:
ES31-CTS.shader_image_load_store.negative-linkErrors
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93410
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tapani Pälli [Mon, 4 Jan 2016 07:55:52 +0000 (09:55 +0200)]
mesa: do not validate io of non-compute and compute stage
Fixes regression on SSO tests that have both non-compute and
compute programs in a program pipeline.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93532
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Tapani Pälli [Tue, 12 Jan 2016 09:03:14 +0000 (11:03 +0200)]
glsl: add packed varyings for outputs with single stage program
Commit
8926dc8 added a check where we add packed varyings of output
stage only when we have multiple stages, however duplicates are already
handled by changes in commit
0508d950 and we want to add outputs also in
case where we have only one stage.
Fixes regression caused by
8926dc8 for following test:
ES31-CTS.program_interface_query.separate-programs-vertex
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Roland Scheidegger [Wed, 13 Jan 2016 03:48:41 +0000 (04:48 +0100)]
llvmpipe: (trivial) use cast wrapper for __m128d to __m128 casts
some compiler was unhappy.
Roland Scheidegger [Wed, 6 Jan 2016 00:05:35 +0000 (01:05 +0100)]
llvmpipe: avoid most 64 bit math in rasterization
The trick here is to recognize that in the c + n * dcdx calculations,
not only can the lower FIXED_ORDER bits not change (as the dcdx values
have those all zero) but that this means the sign bit of the calculations
cannot be different as well, that is
sign(c + n*dcdx) == sign((c >> FIXED_ORDER) + n*(dcdx >> FIXED_ORDER)).
That shaves off more than enough bits to never require 64bit masks.
A shifted plane c value could still easily exceed 32 bits, however since we
throw out planes which are trivial accept even before binning (and similarly
don't even get to see tris for which there was a trivial reject plane)) this
is never a problem.
The idea isnt't all that revolutionary, in fact something similar was tried
ages ago (
9773722c2b09d5f0615a47cecf4347859474dc56) back when the values were
only 32 bit anyway. I believe now it didn't quite work then because the
adjustment needed for testing trivial reject / partial masks wasn't handled
correctly.
This still keeps the separate 32/64 bit paths for now, as the 32 bit one still
looks minimally simpler (and also because if we'd pass in dcdx/dcdy/eo unscaled
from setup which would be a good reason to ditch the 32 bit path, we'd need to
change the special-purpose rasterization functions for small tris).
This passes piglit triangle-rasterization (-fbo -auto -max_size
-subpixelbits 8) and triangle-rasterization-overdraw (with some hacks
to make it work correctly with large sizes) easily (full piglit as
well of course, but most tests wouldn't use triangles large enough to
be affected, that is tris with a bounding box over 128x128).
The profiler says indeed time spent in rast_tri functions is reduced
substantially, BUT of course only if the tris are large. I measured a 3%
improvement in mesa gloss demo when supersized to twice the screen size...
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sun, 3 Jan 2016 00:13:45 +0000 (01:13 +0100)]
llvmpipe: scale up bounding box planes to subpixel precision
Otherwise some planes we get in rasterization have subpixel precision, others
not. Doesn't matter so far, but will soon. (OpenGL actually supports viewports
with subpixel accuracy, so could even do bounding box calcs with that).
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sat, 2 Jan 2016 03:59:16 +0000 (04:59 +0100)]
llvmpipe: add sse code for fixed position calculation
This is quite a few less instructions, albeit still do the 2 64bit muls
with scalar c code (they'd need way more shuffles, plus fixup for the signed
mul so it totally doesn't seem worth it - x86 can do 32x32->64bit signed
scalar muls natively just fine after all (even on 32bit).
(This still doesn't have a very measurable performance impact in reality,
although profiler seems to say time spent in setup indeed has gone down by
10% or so overall. Maybe good for a 3% or so improvement in openarena.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Tue, 12 Jan 2016 17:47:44 +0000 (18:47 +0100)]
draw: fix key comparison with uninitialized value
Discovered by accident, valgrind was complaining (could have possibly caused
us to create redundant geometry shader variants).
v2: convinced by Brian and Jose, just use memset for both gs and vs keys,
just as easy and less error prone.
Jason Ekstrand [Tue, 12 Jan 2016 23:36:38 +0000 (15:36 -0800)]
nir/spirv: Add support for OpQuantize
Jason Ekstrand [Tue, 12 Jan 2016 23:35:00 +0000 (15:35 -0800)]
i965: Implement nir_op_fquantize2f16
Jason Ekstrand [Tue, 12 Jan 2016 23:32:51 +0000 (15:32 -0800)]
nir: Add a fquantize2f16 opcode
This opcode simply takes a 32-bit floating-point value and reduces its
effective precision to 16 bits.
Timothy Arceri [Tue, 12 Jan 2016 08:37:38 +0000 (19:37 +1100)]
mesa: print the invalid enum when CreateShader fails
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Jason Ekstrand [Tue, 12 Jan 2016 21:48:32 +0000 (13:48 -0800)]
anv/device: Bump the max program size again
No one will ever need more than 128K, right?
Kenneth Graunke [Mon, 11 Jan 2016 22:51:38 +0000 (14:51 -0800)]
glsl: Make read_from_write_only_variable_visitor ignore .length().
.length() on an unsized SSBO variable doesn't actually read any data
from the SSBO, and is allowed on variables marked 'writeonly'.
Fixes compute shader compilation in Shadow of Mordor.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Mon, 11 Jan 2016 20:25:12 +0000 (12:25 -0800)]
i965: Mark TCS URB writes as having side effects.
This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing
reads and writes from being incorrectly scheduled.
Fixes rendering in GFXBench 4.0's tessellation demo.
For some reason, we haven't ever listed URB writes as having
side-effects. This hasn't been a problem because in most stages, we
never read from the URB, and only write to each location once.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93526
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kristian Høgsberg Kristensen [Tue, 12 Jan 2016 19:46:09 +0000 (11:46 -0800)]
vk: Implement workaround for occlusion queries
We have an issue with occlusion queries (PIPE_CONTROL depth writes)
after using the pipeline with the VS disabled. We work around it by
using a depth cache flush PIPE_CONTROL before doing a depth write.
Fixes dEQP-VK.query_pool.*
Jason Ekstrand [Tue, 12 Jan 2016 19:43:48 +0000 (11:43 -0800)]
anv/UpdateDescriptorSets: Respect write.dstArrayElement
Kristian Høgsberg Kristensen [Tue, 12 Jan 2016 18:54:26 +0000 (10:54 -0800)]
Merge ../mesa into vulkan
Merge master again to get the brw_device_info with the
correct slice counts for KBL.
Kristian Høgsberg Kristensen [Mon, 11 Jan 2016 20:29:42 +0000 (12:29 -0800)]
vk: Support SpvBuiltInViewportIndex
Kristian Høgsberg Kristensen [Mon, 11 Jan 2016 20:27:51 +0000 (12:27 -0800)]
vk: Use the correct stride for CC_VIEWPORT structs
Tom St Denis [Tue, 3 Nov 2015 17:41:54 +0000 (12:41 -0500)]
st/omx: Avoid segfault in deconstructor if constructor fails
If the constructor fails before the LIST_INIT calls the pointers
will be null and the deconstructor will segfault.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Christian König [Wed, 16 Dec 2015 13:19:41 +0000 (14:19 +0100)]
vl: use preferred format for deinterlacing
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Christian König [Tue, 15 Dec 2015 20:21:50 +0000 (21:21 +0100)]
vl: improve motion adaptive deinterlacer
Handle other formats than YV12 as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Christian König [Tue, 8 Dec 2015 12:18:43 +0000 (13:18 +0100)]
st/va: add BOB deinterlacing v2
Tested with MPV.
v2: correctly handle compositor deinterlacing as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Christian König [Mon, 7 Dec 2015 15:40:29 +0000 (16:40 +0100)]
st/va: add NV12 -> NV12 post processing v2
Usefull for mpv and GStreamer.
v2: use common functionality for size adjustment.
Signed-off-by: Indrajit-kumar Das <Indrajit-kumar.Das@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>