Cesar_Strauss [Fri, 13 Nov 2020 10:24:23 +0000 (10:24 +0000)]
Add Tomasulo model example
lkcl [Fri, 13 Nov 2020 02:19:25 +0000 (02:19 +0000)]
lkcl [Fri, 13 Nov 2020 02:07:06 +0000 (02:07 +0000)]
lkcl [Fri, 13 Nov 2020 02:06:00 +0000 (02:06 +0000)]
lkcl [Fri, 13 Nov 2020 00:11:48 +0000 (00:11 +0000)]
lkcl [Wed, 11 Nov 2020 22:24:46 +0000 (22:24 +0000)]
lkcl [Wed, 11 Nov 2020 21:51:46 +0000 (21:51 +0000)]
lkcl [Wed, 11 Nov 2020 21:27:32 +0000 (21:27 +0000)]
Tobias Platen [Wed, 11 Nov 2020 18:48:15 +0000 (19:48 +0100)]
add dcbz and tlbio instruction needed by mmu
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 16:21:51 +0000 (16:21 +0000)]
add minerva nmigen-soc example
lkcl [Mon, 9 Nov 2020 11:02:59 +0000 (11:02 +0000)]
lkcl [Mon, 9 Nov 2020 10:59:14 +0000 (10:59 +0000)]
lkcl [Mon, 9 Nov 2020 10:48:36 +0000 (10:48 +0000)]
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 19:32:12 +0000 (19:32 +0000)]
add EOMA68+LibreSOC gadie section
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 18:44:58 +0000 (18:44 +0000)]
add EOMA68+LibreSOC gadie section
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:56:49 +0000 (17:56 +0000)]
extend gaddie pitch
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:49:33 +0000 (17:49 +0000)]
extend gaddie pitch
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:49:22 +0000 (17:49 +0000)]
extend gaddie pitch
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 17:32:15 +0000 (17:32 +0000)]
add gaddie pitch section for LibreSOC
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 14:36:54 +0000 (14:36 +0000)]
update nlnet FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:57:13 +0000 (11:57 +0000)]
update FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:50:11 +0000 (11:50 +0000)]
add name tag to FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:49:50 +0000 (11:49 +0000)]
add name tag to FAQ
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 11:49:06 +0000 (11:49 +0000)]
add name tag to FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 18:55:29 +0000 (18:55 +0000)]
add to nlnet FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:54:55 +0000 (15:54 +0000)]
add to NLnet FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:49:33 +0000 (15:49 +0000)]
add to NLnet FAQ
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:29:11 +0000 (15:29 +0000)]
show tab on imag
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:26:35 +0000 (15:26 +0000)]
update FPGA connector images
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:26:26 +0000 (15:26 +0000)]
add circuit refs
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:22:53 +0000 (15:22 +0000)]
change to use 3.3v on VERSA X3
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 15:21:23 +0000 (15:21 +0000)]
add NLnet FAQ
Cole Poirier [Wed, 4 Nov 2020 01:37:45 +0000 (17:37 -0800)]
HDL_wokflow update ulx3s jtag jumper wire connection images to be
smaller
Cole Poirier [Wed, 4 Nov 2020 01:09:32 +0000 (17:09 -0800)]
HDL_workflow/ECP5_FPGA provide two images showing different orientation
of stlinkv2
Cole Poirier [Wed, 4 Nov 2020 00:55:59 +0000 (16:55 -0800)]
update photo for stlinkv2 JTAG wires in HDL_Workflow/ECP5_FPGA
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:31:45 +0000 (14:31 +0000)]
colour-mark X3 VERSA ECP5 JTAG pins
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:26:35 +0000 (14:26 +0000)]
update jtag table, add colour to images
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:11:28 +0000 (14:11 +0000)]
add stlinkv2 photos
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 14:10:33 +0000 (14:10 +0000)]
add stlinkv2 connector images
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:53:28 +0000 (13:53 +0000)]
swap wires around to match ulx3s
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:50:32 +0000 (13:50 +0000)]
format table
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:47:29 +0000 (13:47 +0000)]
add ECP5 JTAG connections
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:35:24 +0000 (13:35 +0000)]
add image links to ECP5 page
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:33:28 +0000 (13:33 +0000)]
add versa ecp5 x3 photo
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:29:07 +0000 (13:29 +0000)]
add VERSA-ECP5 images, rename FPGA page
Cole Poirier [Sun, 1 Nov 2020 22:17:06 +0000 (14:17 -0800)]
add images to wiki for ulx3s jtag stlinkv2 wires
add page use ulx3s fpga gpio pins for Libre-SOC JTAG connections to STLINKV2
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 12:23:35 +0000 (12:23 +0000)]
add cross-ref links
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 12:15:20 +0000 (12:15 +0000)]
adjust image size
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 12:11:29 +0000 (12:11 +0000)]
add description of table
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 11:48:15 +0000 (11:48 +0000)]
change image size
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 11:47:33 +0000 (11:47 +0000)]
add image size
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 11:47:04 +0000 (11:47 +0000)]
add start of isa-to-virtual regs
Luke Kenneth Casson Leighton [Sat, 31 Oct 2020 11:45:14 +0000 (11:45 +0000)]
add isa to virtual regs lookup
Luke Kenneth Casson Leighton [Fri, 30 Oct 2020 15:38:57 +0000 (15:38 +0000)]
add clock switch resource
Luke Kenneth Casson Leighton [Fri, 30 Oct 2020 10:53:09 +0000 (10:53 +0000)]
spelling
Luke Kenneth Casson Leighton [Fri, 30 Oct 2020 10:52:44 +0000 (10:52 +0000)]
add 180nm tapeout to progress
Luke Kenneth Casson Leighton [Thu, 29 Oct 2020 14:51:17 +0000 (14:51 +0000)]
whitespace
lkcl [Thu, 29 Oct 2020 14:25:13 +0000 (14:25 +0000)]
lkcl [Thu, 29 Oct 2020 14:13:48 +0000 (14:13 +0000)]
Luke Kenneth Casson Leighton [Tue, 27 Oct 2020 20:46:44 +0000 (20:46 +0000)]
further investigation note
Luke Kenneth Casson Leighton [Tue, 27 Oct 2020 20:34:20 +0000 (20:34 +0000)]
further investigation note
Luke Kenneth Casson Leighton [Tue, 27 Oct 2020 20:33:38 +0000 (20:33 +0000)]
further investigation note
Jacob Lifshay [Tue, 27 Oct 2020 19:46:35 +0000 (12:46 -0700)]
add header
Jacob Lifshay [Tue, 27 Oct 2020 19:43:14 +0000 (12:43 -0700)]
finish compared_to_register_renaming.mdwn
Luke Kenneth Casson Leighton [Tue, 27 Oct 2020 12:59:23 +0000 (12:59 +0000)]
add link to tomasulo_transformation for notes on "nameless" registers
Jacob Lifshay [Tue, 27 Oct 2020 04:54:35 +0000 (21:54 -0700)]
working on compared_to_register_renaming.mdwn
lkcl [Tue, 27 Oct 2020 01:44:33 +0000 (01:44 +0000)]
lkcl [Tue, 27 Oct 2020 01:42:35 +0000 (01:42 +0000)]
lkcl [Mon, 26 Oct 2020 23:42:43 +0000 (23:42 +0000)]
lkcl [Mon, 26 Oct 2020 23:41:48 +0000 (23:41 +0000)]
lkcl [Mon, 26 Oct 2020 22:41:15 +0000 (22:41 +0000)]
lkcl [Mon, 26 Oct 2020 21:27:11 +0000 (21:27 +0000)]
lkcl [Mon, 26 Oct 2020 21:25:59 +0000 (21:25 +0000)]
lkcl [Mon, 26 Oct 2020 21:25:25 +0000 (21:25 +0000)]
lkcl [Mon, 26 Oct 2020 21:17:23 +0000 (21:17 +0000)]
lkcl [Mon, 26 Oct 2020 21:16:47 +0000 (21:16 +0000)]
lkcl [Mon, 26 Oct 2020 21:15:46 +0000 (21:15 +0000)]
lkcl [Mon, 26 Oct 2020 21:15:09 +0000 (21:15 +0000)]
lkcl [Mon, 26 Oct 2020 21:13:41 +0000 (21:13 +0000)]
lkcl [Mon, 26 Oct 2020 21:09:34 +0000 (21:09 +0000)]
lkcl [Mon, 26 Oct 2020 20:58:24 +0000 (20:58 +0000)]
lkcl [Mon, 26 Oct 2020 20:57:55 +0000 (20:57 +0000)]
lkcl [Mon, 26 Oct 2020 20:27:40 +0000 (20:27 +0000)]
lkcl [Mon, 26 Oct 2020 20:18:19 +0000 (20:18 +0000)]
lkcl [Mon, 26 Oct 2020 20:17:50 +0000 (20:17 +0000)]
projects / libreriscv.git / log