Brad Beckmann [Fri, 29 Apr 2011 00:18:14 +0000 (17:18 -0700)]
garnet: removed flit_width from Routers
Brad Beckmann [Fri, 29 Apr 2011 00:18:14 +0000 (17:18 -0700)]
network: adjusted default endpoint bandwidth
The simple network's endpoint bandwidth value is used to adjust the overall
bandwidth of the network. Specifically, the ration between endpoint bandwidth
and the MESSAGE_SIZE_MULTIPLIER determines the increase. By setting the value
to 1000, that means the bandwdith factor specified in the links translates to
the link bandwidth in bytes. Previously, it was increasing that value by 10.
This patch will likely require a reset of the ruby regression tester stats.
Brad Beckmann [Fri, 29 Apr 2011 00:18:14 +0000 (17:18 -0700)]
network: removed the unused network-wide latency param
Brad Beckmann [Fri, 29 Apr 2011 00:18:14 +0000 (17:18 -0700)]
network: moved network config params
Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.
Brad Beckmann [Fri, 29 Apr 2011 00:18:14 +0000 (17:18 -0700)]
network: basic link bw for garnet and simple networks
This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.
--HG--
rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc
rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh
rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py
Brad Beckmann [Fri, 29 Apr 2011 00:18:14 +0000 (17:18 -0700)]
network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.
By making this change, many aspects of the Topology class were simplified.
--HG--
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
Brad Beckmann [Fri, 29 Apr 2011 00:18:12 +0000 (17:18 -0700)]
garnet: cleaned up flexible network header file
Brad Beckmann [Fri, 29 Apr 2011 00:18:12 +0000 (17:18 -0700)]
ruby: moved topology to the top network directory
Moved the Topology class to the top network directory because it is shared by
both the simple and Garnet networks.
--HG--
rename : src/mem/ruby/network/simple/Topology.cc => src/mem/ruby/network/Topology.cc
rename : src/mem/ruby/network/simple/Topology.hh => src/mem/ruby/network/Topology.hh
Brad Beckmann [Fri, 29 Apr 2011 00:18:12 +0000 (17:18 -0700)]
ruby: removed dated comment in SimpleNetwork
Nathan Binkert [Thu, 28 Apr 2011 23:45:17 +0000 (16:45 -0700)]
event: fix PythonEvent
order of %includes since they matter for this case
Nathan Binkert [Mon, 25 Apr 2011 21:18:08 +0000 (14:18 -0700)]
stats: update 20.parser o3 now that it works. realview-o3 works too.
Nilay Vaish [Mon, 25 Apr 2011 17:23:37 +0000 (12:23 -0500)]
base: include types.hh in base/stats/mysql.hh
Due to certain changes made via changeset 8229, the compilation was failing
in certain cases. The compiler pointed to base/stats/mysql.hh for not naming
a certain types like uint64_t. To rectify this, base/types.hh is being
included in base/stats/mysql.hh.
Gabe Black [Sat, 23 Apr 2011 22:02:29 +0000 (15:02 -0700)]
X86: When decoding a memory only inst, fault on reg encodings, don't assert.
This change makes the decoder figure out if an instruction that only supports
memory is using a register encoding and decodes directly to "Unknown" which will
behave appropriately. This prevents other parts of the instruction creation
process from seeing the mismatch and asserting.
Nathan Binkert [Fri, 22 Apr 2011 17:18:51 +0000 (10:18 -0700)]
tests: updates for stat name change
Nathan Binkert [Thu, 21 Apr 2011 02:07:46 +0000 (19:07 -0700)]
stats: ensure that stat names are valid
Nathan Binkert [Thu, 21 Apr 2011 02:07:45 +0000 (19:07 -0700)]
stats: one more name violation
Nathan Binkert [Thu, 21 Apr 2011 02:07:44 +0000 (19:07 -0700)]
python: fix another bug from changes to main.py
Nathan Binkert [Thu, 21 Apr 2011 01:45:03 +0000 (18:45 -0700)]
fix some build problems from prior changesets
Steve Reinhardt [Wed, 20 Apr 2011 20:47:42 +0000 (13:47 -0700)]
Change default regression build from 'fast' to 'opt'
Brad Danofsky [Wed, 20 Apr 2011 18:14:52 +0000 (11:14 -0700)]
stats: add user settable separator string for arrayed stats
Default is '::', so no visible change unless it is overridden
Brad Danofsky [Wed, 20 Apr 2011 18:14:51 +0000 (11:14 -0700)]
scons: Allow the build directory live under an EXTRAS directory
Nathan Binkert [Wed, 20 Apr 2011 01:45:23 +0000 (18:45 -0700)]
tests: update stats for name changes
Nathan Binkert [Wed, 20 Apr 2011 01:45:21 +0000 (18:45 -0700)]
stats: rename stats so they can be used as python expressions
Nathan Binkert [Tue, 19 Apr 2011 18:13:01 +0000 (11:13 -0700)]
python: different import for dealing with demandimport
Nathan Binkert [Sun, 17 Apr 2011 21:21:04 +0000 (14:21 -0700)]
style: fix all_regions code and remove bogus region type
Nathan Binkert [Sun, 17 Apr 2011 20:57:40 +0000 (13:57 -0700)]
style: remove extra debugging print
Nathan Binkert [Sun, 17 Apr 2011 20:57:03 +0000 (13:57 -0700)]
file_types: Make code work in Python 2.4
Nathan Binkert [Fri, 15 Apr 2011 17:45:11 +0000 (10:45 -0700)]
unittest: Make unit tests capable of using swig and python, convert stattest
Nathan Binkert [Fri, 15 Apr 2011 17:44:59 +0000 (10:44 -0700)]
python: cleanup python code so stuff doesn't automatically happen at startup
this allows things to be overridden at startup (e.g. for tests)
Nathan Binkert [Fri, 15 Apr 2011 17:44:44 +0000 (10:44 -0700)]
scons: make a flexible system for guarding source files
This is similar to guards on mercurial queues and they're used for selecting
which files are compiled into some given object. We already do something
similar, but it's mostly hard coded for the m5 binary and the m5 library
and I'd like to make it more flexible to better support the unittests
Nathan Binkert [Fri, 15 Apr 2011 17:44:32 +0000 (10:44 -0700)]
trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
Nathan Binkert [Fri, 15 Apr 2011 17:44:15 +0000 (10:44 -0700)]
debug: create a Debug namespace
Nathan Binkert [Fri, 15 Apr 2011 17:44:14 +0000 (10:44 -0700)]
includes: fix up code after sorting
Nathan Binkert [Fri, 15 Apr 2011 17:44:06 +0000 (10:44 -0700)]
includes: sort all includes
Nathan Binkert [Fri, 15 Apr 2011 17:43:51 +0000 (10:43 -0700)]
style: add sort_includes to the style hook
Nathan Binkert [Fri, 15 Apr 2011 17:43:47 +0000 (10:43 -0700)]
style: move style verifiers into classes
Nathan Binkert [Fri, 15 Apr 2011 17:43:30 +0000 (10:43 -0700)]
style: add a user interface wrapper class
makes things work both with mercurial and stand alone with stdio
Nathan Binkert [Fri, 15 Apr 2011 17:43:06 +0000 (10:43 -0700)]
util: python implementation of a routine that will sort includes
I didn't realize that the perl version existed when I started this,
this version has a lot more features than the previous one since it will
sort and separate python, system, and m5 headers in separate groups, it
will remove duplicates, it will also convert c headers to stl headers
Nathan Binkert [Fri, 15 Apr 2011 17:42:32 +0000 (10:42 -0700)]
region: add a utility class for keeping track of regions of some range
This is basically like the range_map stuff in src/base (range already
exists in Python). This code is like a set of ranges. I'm using it
to keep track of changed lines in source code, but it could be use to
keep track of memory ranges and holes in memory regions. It could
also be used in memory allocation type stuff. (Though it's not at all
optimized.)
Nathan Binkert [Fri, 15 Apr 2011 17:38:02 +0000 (10:38 -0700)]
SortedDict: add functions for getting ranges of keys, values, items
Nathan Binkert [Fri, 15 Apr 2011 17:37:28 +0000 (10:37 -0700)]
python: figure out if the m5.internal package exists even with demandimport
Nathan Binkert [Wed, 13 Apr 2011 16:32:19 +0000 (09:32 -0700)]
refcnt: Update doxygen comments
Nathan Binkert [Wed, 13 Apr 2011 16:32:18 +0000 (09:32 -0700)]
refcnt: Inline comparison functions
Nathan Binkert [Wed, 13 Apr 2011 16:32:18 +0000 (09:32 -0700)]
main: separate out interact() so it can be used by other functions
Nathan Binkert [Wed, 13 Apr 2011 16:32:17 +0000 (09:32 -0700)]
util: fix the language type function
Ali Saidi [Tue, 12 Apr 2011 20:09:20 +0000 (16:09 -0400)]
ARM: Fix stats for ARM_SE checkpoint restore fix.
Register reads/writes done in startup() count against the stats while they
don't count if done in initState().
Ali Saidi [Mon, 11 Apr 2011 01:02:28 +0000 (21:02 -0400)]
ARM: Fix checkpoint restoration in ARM_SE.
Ali Saidi [Mon, 11 Apr 2011 01:02:28 +0000 (21:02 -0400)]
ARM: Get rid of some comments/todos that no longer apply.
Brad Beckmann [Wed, 6 Apr 2011 21:41:41 +0000 (14:41 -0700)]
ruby: fixes to support more types of RubyRequests
Ali Saidi [Mon, 4 Apr 2011 16:42:32 +0000 (11:42 -0500)]
ARM: Update stats for default inclusion of CF adapter.
Ali Saidi [Mon, 4 Apr 2011 16:42:31 +0000 (11:42 -0500)]
ARM: Include IDE/CF controller by default in PBX model.
Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
Anthony Gutierrez [Mon, 4 Apr 2011 16:42:31 +0000 (11:42 -0500)]
Sim: Fix Simulation.py to allow more than 1 core for standard switching.
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.
Ali Saidi [Mon, 4 Apr 2011 16:42:31 +0000 (11:42 -0500)]
ARM: Update stats for previous changes.
Ali Saidi [Mon, 4 Apr 2011 16:42:29 +0000 (11:42 -0500)]
ARM: Use CPU local lock before sending load to mem system.
This change uses the locked_mem.hh header to handle implementing CLREX. It
simplifies the current implementation greatly.
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.
This change fixes a small bug in the arm copyRegs() code where some registers
wouldn't be copied if the processor was in a mode other than MODE_USER.
Additionally, this change simplifies the way the O3 switchCpu code works by
utilizing TheISA::copyRegs() to copy the required context information
rather than the adhoc copying that goes on in the CPU model. The current code
makes assumptions about the visibility of int and float registers that aren't
true for all architectures in FS mode.
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Fix bug in MicroLdrNeon templates for initiateAcc().
William Wang [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Cleanup and small fixes to some NEON ops to match the spec.
Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
Ali Saidi [Mon, 4 Apr 2011 16:42:28 +0000 (11:42 -0500)]
ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.
Ali Saidi [Mon, 4 Apr 2011 16:42:27 +0000 (11:42 -0500)]
ARM: Tag appropriate instructions as IsReturn
Ali Saidi [Mon, 4 Apr 2011 16:42:27 +0000 (11:42 -0500)]
ARM: Fix table walk going on while ASID changes error
Ali Saidi [Mon, 4 Apr 2011 16:42:26 +0000 (11:42 -0500)]
CPU: Remove references to memory copy operations
Ali Saidi [Mon, 4 Apr 2011 16:42:25 +0000 (11:42 -0500)]
O3: Update stats for memory order violation checking patch.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
O3: Tighten memory order violation checking to 16 bytes.
The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
IDE: Support x86, Alpha, and ARM use of the IDE controller.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
ARM: Fix checkpointing case where PL111 is powered off.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
ARM: Remove debugging warn that was accidently left in.
Ali Saidi [Mon, 4 Apr 2011 16:42:23 +0000 (11:42 -0500)]
ARM: Fix multiplication error in udelay
Brad Beckmann [Fri, 1 Apr 2011 22:50:23 +0000 (15:50 -0700)]
hammer: fixed dma uniproc error
Fixed an error reguarding DMA for uninprocessor systems. Basically removed an
overly agressive optimization that lead to inconsistent state between the
cache and the directory.
Lisa Hsu [Fri, 1 Apr 2011 01:20:12 +0000 (18:20 -0700)]
CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return
a return value. In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable. This is kind of a hack to get around
those issues, but suggestions welcome.
Lisa Hsu [Fri, 1 Apr 2011 00:18:00 +0000 (17:18 -0700)]
Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code. Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).
This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed. So, now, things you can do that you couldn't before
include:
Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;
or
cache_entry.DataBlk := getCacheEntry(address).DataBlk;
or even
cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;
Lisa Hsu [Fri, 1 Apr 2011 00:17:57 +0000 (17:17 -0700)]
Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.
Lisa Hsu [Fri, 1 Apr 2011 00:17:51 +0000 (17:17 -0700)]
Ruby: have the rubytester pass contextId to Ruby.
Lisa Hsu [Fri, 1 Apr 2011 00:17:49 +0000 (17:17 -0700)]
Ruby: enable multiple sequencers in one controller.
Lisa Hsu [Fri, 1 Apr 2011 00:17:47 +0000 (17:17 -0700)]
Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists. This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.
Lisa Hsu [Thu, 31 Mar 2011 19:20:16 +0000 (12:20 -0700)]
Ruby: Bug in SLICC forgot semicolon at end of code.
Korey Sewell [Tue, 29 Mar 2011 23:36:36 +0000 (19:36 -0400)]
sim: typecast Tick to UTick for eventQ assert
Gabe Black [Tue, 29 Mar 2011 17:04:19 +0000 (13:04 -0400)]
Power: Fix compilation.
Somayeh Sardashti [Mon, 28 Mar 2011 15:49:45 +0000 (10:49 -0500)]
This patch supports cache flushing in MOESI_hammer
Nilay Vaish [Mon, 28 Mar 2011 15:49:36 +0000 (10:49 -0500)]
Config: Import math in MI_example.py
Steve Reinhardt [Sun, 27 Mar 2011 05:24:36 +0000 (22:24 -0700)]
tests: update reference outputs for ruby cache index change
MOESI_CMP_token is the only protocol that showed noticeable stats
differences.
Korey Sewell [Sat, 26 Mar 2011 13:23:52 +0000 (09:23 -0400)]
mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
anyway.
Brad Beckmann [Fri, 25 Mar 2011 17:13:50 +0000 (10:13 -0700)]
ruby: fixed cache index setting
Gabe Black [Fri, 25 Mar 2011 04:46:14 +0000 (00:46 -0400)]
Arm: Add in a missing miscRegName.
Gabe Black [Thu, 24 Mar 2011 18:39:00 +0000 (14:39 -0400)]
Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.
Gabe Black [Thu, 24 Mar 2011 18:00:15 +0000 (14:00 -0400)]
Arm: Get rid of the unused copyStringArray32 method from Arm process classes.
Gabe Black [Thu, 24 Mar 2011 17:55:16 +0000 (13:55 -0400)]
ISA parser: Set up op_src_decl and op_dest_decl for pc operands.
Tushar Krishna [Wed, 23 Mar 2011 03:38:09 +0000 (23:38 -0400)]
This patch fixes a build error in networktest.cc that occurs with gcc4.2
Nilay Vaish [Tue, 22 Mar 2011 11:41:54 +0000 (06:41 -0500)]
Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.
Tushar Krishna [Tue, 22 Mar 2011 02:51:59 +0000 (22:51 -0400)]
This patch makes garnet use the info about active and inactive vnets during allocation and power estimations etc
Tushar Krishna [Tue, 22 Mar 2011 02:51:59 +0000 (22:51 -0400)]
fix garnet fleible pipeline
Tushar Krishna [Tue, 22 Mar 2011 02:51:58 +0000 (22:51 -0400)]
This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
Nilay Vaish [Sun, 20 Mar 2011 14:23:27 +0000 (09:23 -0500)]
SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from the
slicc/ast directory. I had forgotten to remove the import calls for these
files from slicc/ast/__init__.py. This resulted in error while running
regressions on zizzer. This patch does the needful.
Lisa Hsu [Sun, 20 Mar 2011 04:13:04 +0000 (21:13 -0700)]
configs: combine ruby_se.py and se.py to avoid all that code duplication
Lisa Hsu [Sun, 20 Mar 2011 04:13:02 +0000 (21:13 -0700)]
enable x86 workloads on se.py
Lisa Hsu [Sun, 20 Mar 2011 04:12:59 +0000 (21:12 -0700)]
se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads. Only caveat is that now,
for sanity checking, your -n X must match the number of benches in the list.
Lisa Hsu [Sun, 20 Mar 2011 04:12:55 +0000 (21:12 -0700)]
util: update aggregator to handle x86 checkpoints.
Also, make update to understand some of the newer serialized variables
Nilay Vaish [Sat, 19 Mar 2011 23:34:59 +0000 (18:34 -0500)]
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
Nilay Vaish [Sat, 19 Mar 2011 23:34:37 +0000 (18:34 -0500)]
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.
Brad Beckmann [Sat, 19 Mar 2011 21:17:48 +0000 (14:17 -0700)]
MOESI_hammer: minor fixes to full-bit dir