safe_iterator.h (_Safe_iterator<>::_M_constant()): Rename in...

2018-05-09  François Dumont  <fdumont@gcc.gnu.org>

* include/debug/safe_iterator.h (_Safe_iterator<>::_M_constant()):
Rename in...
(_Safe_iterator<>::_S_constant()): ...that.
* include/debug/safe_local_iterator.h
(_Safe_local_iterator<>::_M_constant()): Rename in...
(_Safe_local_iterator<>::_S_constant()): ...that.
* include/debug/formatter.h: Remove bits/cpp_type_traits.h include.
(_Iterator_state::__rbegin): New.
(_Iterator_state::__rmiddle): New.
(_Iterator_state::__rend): New.
(_Parameter::_Parameter(const _Safe_iterator<>&, const char*,
_Is_iterator)): Use _Safe_iterator<>::_S_constant. Grab normal underlying
iterator type.
(_Parameter::_Parameter(const _Safe_local_iterator<>&, const char*,
_Is_iterator)): Likewise.
(_Parameter::_S_reverse_state(_Iterator_state)): New.
        (_Parameter(__gnu_cxx::__normal_iterator<> const&, const char*,
_Is_iterator)): New.
(_Parameter(std::reverse_iterator<> const&, const char*,
_Is_iterator)): New.
(_Parameter(std::reverse_iterator<_Safe_iterator<>> const&,
const char*, _Is_iterator)): New.
(_Parameter(std::move_iterator<> const&, const char*, _Is_iterator):
New.
(_Parameter(std::move_iterator<_Safe_iterator<>> const&, const char*,
_Is_iterator)): New.
* testsuite/24_iterators/move_iterator/debug_neg.cc: New.
* testsuite/24_iterators/normal_iterator/debug_neg.cc: New.
* testsuite/24_iterators/reverse_iterator/debug_neg.cc: New.

From-SVN: r260093

re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)

2018-05-09  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/85713
* g++.dg/cpp1y/lambda-generic-85713.C: New.

From-SVN: r260092

builtins-8-runnable.c: New builtin test file.

gcc/testsuite/ChangeLog:

2018-05-09 Carl Love  <cel@us.ibm.com>
* gcc.target/powerpc/builtins-8-runnable.c: New builtin test file.

From-SVN: r260090

re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)

/cp
2018-05-09  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/85713
Revert:
2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/84588
* parser.c (cp_parser_parameter_declaration_list): When the
entire parameter-declaration-list is erroneous maybe call
abort_fully_implicit_template.

/testsuite
2018-05-09  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/85713
Revert:
2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/84588
* g++.dg/cpp1y/pr84588.C: New.

From-SVN: r260087

re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)

/cp
2018-05-09  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/85713
Revert:
2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/84588
* parser.c (cp_parser_parameter_declaration_list): When the
entire parameter-declaration-list is erroneous maybe call
abort_fully_implicit_template.

/testsuite
2018-05-09  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/85713
Revert:
2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/84588
* g++.dg/cpp1y/pr84588.C: New.

From-SVN: r260086

[openacc, libgomp] Use GOMP_ASYNC_SYNC in GOACC_declare

2018-05-09  Tom de Vries  <tom@codesourcery.com>

PR libgomp/82901
* oacc-parallel.c (GOACC_declare): Use GOMP_ASYNC_SYNC as async argument
to GOACC_enter_exit_data.

From-SVN: r260085

Add ax_pthread.m4 for use in binutils-gdb

config/
* ax_pthread.m4: Add file

From-SVN: r260083

* gcc.target/aarch64/sve/vcond_6.c: Add missing brace.

From-SVN: r260082

[openacc] Factor out async argument utility functions

2018-05-09  Tom de Vries  <tom@codesourcery.com>

PR libgomp/83792
* oacc-int.h (async_valid_stream_id_p, async_valid_p)
(async_synchronous_p): New function.
* oacc-async.c (acc_async_test, acc_wait, acc_wait_all_async): Use
async_valid_p.
* oacc-cuda.c (acc_get_cuda_stream, acc_set_cuda_stream): Use
async_valid_stream_id_p.
* oacc-mem.c (gomp_acc_remove_pointer): Use async_synchronous_p.
* oacc-parallel.c (GOACC_parallel_keyed): Same.

From-SVN: r260081

Make std::function tolerate semantically non-CopyConstructible objects

To satisfy the CopyConstructible requirement a callable object stored in
a std::function must behave the same when copied from a const or
non-const source. If copying a non-const object doesn't produce an
equivalent copy then the behaviour is undefined. But we can make our
std::function more tolerant of such objects by ensuring we always copy
from a const lvalue.

Additionally use an if constexpr statement in the _M_get_pointer
function to avoid unnecessary instantiations in the discarded branch.

* include/bits/std_function.h (_Base_manager::_M_get_pointer):
Use constexpr if in C++17 mode.
(_Base_manager::_M_clone(_Any_data&, const _Any_data&, true_type)):
Copy from const object.
* testsuite/20_util/function/cons/non_copyconstructible.cc: New.

From-SVN: r260080

tree-vect-slp.c (vect_bb_slp_scalar_cost): Fill a cost vector.

2018-05-09  Richard Biener  <rguenther@suse.de>

* tree-vect-slp.c (vect_bb_slp_scalar_cost): Fill a cost
vector.
(vect_bb_vectorization_profitable_p): Adjust.  Compute
actual scalar cost using the cost vector and the add_stmt_cost
machinery.

From-SVN: r260078

rs6000: Give an argument to every REG_CFA_REGISTER (PR85645)

The one for the prologue mflr did not have any value set, which means
use the SET that is in the insn pattern.  This works fine, except when
some late pass decides to replace the SET_SRC -- this changes the
meaning of the REG_CFA_REGISTER!  Such passes should not do these
things, but let's be more explicit here, for extra robustness.  It
could be argued that this defaulting is a design misfeature (it does
not save much space either, etc.)

PR rtl-optimization/85645
* config/rs6000/rs6000.c (rs6000_emit_prologue_components): Put a SET
in the REG_CFA_REGISTER note for LR, don't leave it empty.

From-SVN: r260077

shrink-wrap: Improve spread_components (PR85645)

In the testcase for PR85645 we do a pretty dumb placement of the
prologue/epilogue for the LR component: we place an epilogue for LR
before a control flow split where one of the branches clobbers LR
eventually, and the other does not.  The branch that does clobber it
will need a prologue again some time later.  Because saving and
restoring LR is a two step process---it needs to be moved via a GPR---
the backend emits CFI directives so that we get correct unwind
information.  But both regcprop and regrename do not properly handle
such CFI directives leading to ICEs.

Now, neither of the two branches needs to have LR restored at all,
because both of the branches end up in an infinite loop.

This patch makes spread_component return a boolean saying if anything
was changed, and if so, it is called again.  This obviously is finite
(there is a finite number of basic blocks, each with a finite number
of components, and spread_components can only assign more components
to a block, never less).  I also instrumented the code, and on a
bootstrap+regtest spread_components made changes a maximum of two
times.  Interestingly though it made changes on two iterations in
a third of the cases it did anything at all!

PR rtl-optimization/85645
* shrink-wrap.c (spread_components): Return a boolean saying if
anything was changed.
(try_shrink_wrapping_separate): Iterate spread_components until
nothing changes anymore.

From-SVN: r260076

regrename: Don't rename the dest of a REG_CFA_REGISTER (PR85645)

We should never change the destination of a REG_CFA_REGISTER, just
like for insns with a REG_CFA_RESTORE, because we need to have the
same control flow information on all branches that join.  It is very
doubtful that renaming the scratch registers used for prologue/epilogue
will help anything either.

PR rtl-optimization/85645
* regrename.c (build_def_use): Also kill the chains that include the
destination of a REG_CFA_REGISTER note.

From-SVN: r260075

regcprop: Avoid REG_CFA_REGISTER notes (PR85645)

Changing a SET that has a REG_CFA_REGISTER note is wrong if we are
changing the SET_DEST, or if the REG_CFA_REGISTER has nil as its
argument, and maybe some other cases.  It's never really useful to
propagate into such an instruction, so let's just bail whenever we
see such a note.

PR rtl-optimization/85645
*  regcprop.c (copyprop_hardreg_forward_1): Don't propagate into an
insn that has a REG_CFA_REGISTER note.

From-SVN: r260074

Add clobbers around IFN_LOAD/STORE_LANES

We build up the input to IFN_STORE_LANES one vector at a time.
In RTL, each of these vector assignments becomes a write to
subregs of the form (subreg:VEC (reg:AGGR R)), where R is the
eventual input to the store lanes instruction.  The problem is
that RTL isn't very good at tracking liveness when things are
initialised piecemeal by subregs, so R tends to end up being
live on all paths from the entry block to the store.  This in
turn leads to unnecessary spilling around calls, as well as to
excess register pressure in vector loops.

This patch adds gimple clobbers to indicate the liveness of the
IFN_STORE_LANES variable and makes sure that gimple clobbers are
expanded to rtl clobbers where useful.  For consistency it also
uses clobbers to mark the point at which an IFN_LOAD_LANES
variable is no longer needed.

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* cfgexpand.c (expand_clobber): New function.
(expand_gimple_stmt_1): Use it.
* tree-vect-stmts.c (vect_clobber_variable): New function,
split out from...
(vectorizable_simd_clone_call): ...here.
(vectorizable_store): Emit a clobber either side of an
IFN_STORE_LANES sequence.
(vectorizable_load): Emit a clobber after an IFN_LOAD_LANES sequence.

gcc/testsuite/
* gcc.target/aarch64/store_lane_spill_1.c: New test.
* gcc.target/aarch64/sve/store_lane_spill_1.c: Likewise.

From-SVN: r260073

[nvptx] Make trap insn noreturn

2018-05-09  Tom de Vries  <tom@codesourcery.com>

PR target/85626
* config/nvptx/nvptx.md (define_insn "trap", define_insn "trap_if_true")
(define_insn "trap_if_false"): Add exit after trap.

From-SVN: r260072

re PR rtl-optimization/85638 (build failure for Ada runtime with SJLJ exceptions on x86)

PR rtl-optimization/85638
* bb-reorder.c: Include common/common-target.h.
(create_forwarder_block): New function extracted from...
(fix_up_crossing_landing_pad): ...here.  Rename into...
(dw2_fix_up_crossing_landing_pad): ...this.
(sjlj_fix_up_crossing_landing_pad): New function.
(find_rarely_executed_basic_blocks_and_crossing_edges): In SJLJ mode,
call sjlj_fix_up_crossing_landing_pad if there are incoming EH edges
from both partitions and exit the loop after one iteration.

From-SVN: r260070

PR c++/85706 - class deduction under decltype

* pt.c (for_each_template_parm_r): Handle DECLTYPE_TYPE.  Clear
*walk_subtrees whether or not we walked into the operand.
(type_uses_auto): Only look at deduced contexts.

From-SVN: r260066

revert: extend.texi (PowerPC Built-in Functions): Rename this subsection.

2018-05-08  Kelvin Nilsen  <kelvin@gcc.gnu.org>

Revert:
* doc/extend.texi (PowerPC Built-in Functions): Rename this
subsection.
(Basic PowerPC Built-in Functions): The new name of the
subsection previously known as "PowerPC Built-in Functions".
(Basic PowerPC Built-in Functions Available on all Configurations):
New subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.05): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.06): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.07): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 3.0): New
subsubsection.

From-SVN: r260065

Daily bump.

From-SVN: r260063

* de.po, sv.po: Update.

From-SVN: r260057

[PATCH] RISC-V: Use new linker emulations for glibc ABI.

gcc/
* config/riscv/linux.h (MUSL_ABI_SUFFIX): Delete unnecessary backslash.
(LD_EMUL_SUFFIX): New.
(LINK_SPEC): Use it.

From-SVN: r260056

builtins-8-p9-runnable.c: Add new test file.

gcc/testsuite/ChangeLog:

2018-05-08  Carl Love  <cel@us.ibm.com>
* gcc.target/powerpc/builtins-8-p9-runnable.c: Add new test file.

From-SVN: r260055

debug.cc [...]: Include execinfo.h.

2018-05-08  François Dumont  <fdumont@gcc.gnu.org>

* src/c++11/debug.cc [_GLIBCXX_HAVE_EXECINFO_H]: Include execinfo.h.
[_GLIBCXX_HAVE_EXECINFO_H](_Error_formatter::_M_error): Render
backtrace.

From-SVN: r260054

macros.h (__glibcxx_check_valid_range_at): New.

2018-05-08  François Dumont  <fdumont@gcc.gnu.org>

* include/debug/macros.h (__glibcxx_check_valid_range_at): New.
* include/debug/functions.h (__check_valid_range): Use latter.
* include/debug/macros.h (__glibcxx_check_valid_constructor_range): New,
use latter.
* include/debug/deque
(deque::deque<_Iter>(_Iter, _Iter, const _Alloc&)): Use latter.
* include/debug/forward_list
(forward_list::forward_list<_Iter>(_Iter, _Iter, const _Alloc&)):
Likewise.
* include/debug/list
(list::list<_Iter>(_Iter, _Iter, const _Alloc&)): Likewise.
* include/debug/list
(list::list<_Iter>(_Iter, _Iter, const _Alloc&)): Likewise.
* include/debug/map.h
(map::map<_Iter>(_Iter, _Iter, const _Alloc&)): Likewise.
(map::map<_Iter>(_Iter, _Iter, const _Compare&, const _Alloc&)):
Likewise.
* include/debug/multimap.h
(multimap::multimap<_Iter>(_Iter, _Iter, const _Alloc&)): Likewise.
(multimap::multimap<_Iter>(_Iter, _Iter, const _Compare&,
const _Alloc&)): Likewise.
* include/debug/set.h
(set::set<_Iter>(_Iter, _Iter, const _Alloc&)): Likewise.
(set::set<_Iter>(_Iter, _Iter, const _Compare&, const _Alloc&)):
Likewise.
* include/debug/multiset.h
(multiset::multiset<_Iter>(_Iter, _Iter, const _Alloc&)): Likewise.
(multiset::multiset<_Iter>(_Iter, _Iter, const _Compare&,
const _Alloc&)): Likewise.
* include/debug/string
(basic_string::basic_string<_Iter>(_Iter, _Iter, const _Alloc&)):
Likewise.
* include/debug/unordered_map
(unordered_map::unordered_map<_Iter>(_Iter, _Iter, const _Alloc&)):
Likewise.
(unordered_multimap::unordered_multimap<_Iter>(_Iter, _Iter,
const _Alloc&)): Likewise.
* include/debug/unordered_set
(unordered_set::unordered_set<_Iter>(_Iter, _Iter, const _Alloc&)):
Likewise.
(unordered_multiset::unordered_multiset<_Iter>(_Iter, _Iter,
const _Alloc&)): Likewise.
* include/debug/vector
(vector::vector<_Iter>(_Iter, _Iter, const _Alloc&)): Use latter.

From-SVN: r260053

formatter.h (_Error_formatter::_M_function): New.

2018-05-08  François Dumont  <fdumont@gcc.gnu.org>

* include/debug/formatter.h (_Error_formatter::_M_function): New.
(_Error_formatter(const char*, unsigned int)): Adapt.
(_Error_formatter::_M_at): Rename in...
(_Error_formatter::_S_at): ...that and adapt.
* include/debug/macros.h (_GLIBCXX_DEBUG_VERIFY_AT_F): New.
(_GLIBCXX_DEBUG_VERIFY_AT, _GLIBCXX_DEBUG_VERIFY): Adapt.
* src/c++11/debug.cc (_Error_formatter::_M_error): Render _M_function
when available.

From-SVN: r260052

re PR c++/84588 (internal compiler error: Segmentation fault (contains_struct_check()))

/cp
2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/84588
* parser.c (cp_parser_parameter_declaration_list): When the
entire parameter-declaration-list is erroneous maybe call
abort_fully_implicit_template.

/testsuite
2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/84588
* g++.dg/cpp1y/pr84588.C: New.

From-SVN: r260050

re PR c++/85695 (if constexpr misevaluates typedefed type value)

PR c++/85695
* semantics.c (finish_if_stmt_cond): See through typedefs.

* g++.dg/cpp1z/constexpr-if22.C: New test.

From-SVN: r260049

extend.texi (PowerPC Built-in Functions): Rename this subsection.

gcc/ChangeLog:

2018-05-08  Kelvin Nilsen  <kelvin@gcc.gnu.org>

* doc/extend.texi (PowerPC Built-in Functions): Rename this
subsection.
(Basic PowerPC Built-in Functions): The new name of the
subsection previously known as "PowerPC Built-in Functions".
(Basic PowerPC Built-in Functions Available on all Configurations):
New subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.05): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.06): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.07): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 3.0): New
subsubsection.

From-SVN: r260048

re PR tree-optimization/85693 (Generation of SAD (Sum of Absolute Difference) instruction)

PR target/85693
* gcc.target/i386/pr85693.c: New test.

From-SVN: r260047

Make std::regex automata use non-debug vector in Debug Mode

* include/bits/regex_automaton.h (_NFA_base::_M_paren_stack, _NFA):
Use normal std::vector even in Debug Mode.

From-SVN: r260046

re PR target/85683 (GCC 8 stopped using RMW (Read Modify Write) instructions on x86[_64])

PR target/85683
* config/i386/i386.md: Add peepholes for mem {+,-,&,|,^}= x; mem != 0
after cmpelim optimization.

* gcc.target/i386/pr49095.c: Add -masm=att to dg-options.  Add
scan-assembler-times checking that except for [fh]*xor other functions
don't use any load instructions.

From-SVN: r260045

PR libstdc++/85672 #undef _GLIBCXX_USE_FLOAT128 when not supported

Restore the behaviour in GCC 8 and earlier where _GLIBCXX_USE_FLOAT128
is not defined when configure detects support is missing. This avoids
having three states where the macro is either 1, 0, or undefined.

PR libstdc++/85672
* include/Makefile.am [!ENABLE_FLOAT128]: Change c++config.h entry
to #undef _GLIBCXX_USE_FLOAT128 instead of defining it to zero.
* include/Makefile.in: Regenerate.
* include/bits/c++config (_GLIBCXX_USE_FLOAT128): Move definition
within conditional block.

From-SVN: r260043

config.gcc: Support "goldmont".

2018-05-08  Olga Makhotina  <olga.makhotina@intel.com>

gcc/

* config.gcc: Support "goldmont".
* config/i386/driver-i386.c (host_detect_local_cpu): Detect "goldmont".
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
PROCESSOR_GOLDMONT.
* config/i386/i386.c (m_GOLDMONT): Define.
(processor_target_table): Add "goldmont".
(PTA_GOLDMONT): Define.
(ix86_lea_outperforms): Add TARGET_GOLDMONT.
(get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT.
(fold_builtin_cpu): Add M_INTEL_GOLDMONT.
(fold_builtin_cpu): Add "goldmont".
(ix86_add_stmt_cost): Add TARGET_GOLDMONT.
(ix86_option_override_internal): Add "goldmont".
* config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT.
(processor_type): Add PROCESSOR_GOLDMONT.
* config/i386/i386.md: Add CPU "glm".
* config/i386/glm.md: New file.
* config/i386/x86-tune.def: Add m_GOLDMONT.
* doc/invoke.texi: Add goldmont as x86 -march=/-mtune= CPU type.

libgcc/
* config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT.
* config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont.

gcc/testsuite/

* gcc.target/i386/builtin_target.c: Test goldmont.
* gcc.target/i386/funcspec-56.inc: Tests for arch=goldmont and
arch=silvermont.

From-SVN: r260042

re PR target/85572 (faster code for absolute value of __v2di)

PR target/85572
* config/i386/i386.c (ix86_expand_sse2_abs): Handle E_V2DImode and
E_V4DImode.
* config/i386/sse.md (abs<mode>2): Use VI_AVX2 iterator instead of
VI1248_AVX512VL_AVX512BW.  Handle V2DImode and V4DImode if not
TARGET_AVX512VL using ix86_expand_sse2_abs.  Formatting fixes.

* g++.dg/other/sse2-pr85572-1.C: New test.
* g++.dg/other/sse2-pr85572-2.C: New test.
* g++.dg/other/sse4-pr85572-1.C: New test.
* g++.dg/other/avx2-pr85572-1.C: New test.

From-SVN: r260041

re PR target/85317 (missing constant propagation on _mm(256)_movemask_*)

PR target/85317
* config/i386/i386.c (ix86_fold_builtin): Handle
IX86_BUILTIN_{,P}MOVMSK{PS,PD,B}{,128,256}.

* gcc.target/i386/pr85317.c: New test.
* gcc.target/i386/avx2-vpmovmskb-2.c (avx2_test): Add asm volatile
optimization barrier to avoid optimizing away the expected insn.

From-SVN: r260040

re PR target/85480 (zero extension from xmm to zmm via _mm512_insert???x? not optimized)

PR target/85480
* config/i386/sse.md (ssequaterinsnmode): New mode attribute.
(*<extract_type>_vinsert<shuffletype><extract_suf>_0): New pattern.

* gcc.target/i386/avx512dq-pr85480-1.c: New test.
* gcc.target/i386/avx512dq-pr85480-2.c: New test.

From-SVN: r260039

Move C++ SVE tests to g++.target/aarch64/sve

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
* g++.dg/other/sve_const_pred_1.C: Rename to...
* g++.target/aarch64/sve/const_pred_1.C: ...this.  Remove aarch64
target selectors and explicit -march options.
* g++.dg/other/sve_const_pred_2.C: Rename to...
* g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise.
* g++.dg/other/sve_const_pred_3.C: Rename to...
* g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise.
* g++.dg/other/sve_const_pred_4.C: Rename to...
* g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise.
* g++.dg/other/sve_tls_2.C: Rename to...
* g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise.
* g++.dg/other/sve_vcond_1.C: Rename to...
* g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise.
* g++.dg/other/sve_vcond_1_run.C: Rename to...
* g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise.

From-SVN: r260038

Tighten condition in vect/pr85586.c (PR 85654)

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
PR testsuite/85586
* gcc.dg/vect/pr85586.c: Restrict LOOP VECTORIZED test to
!vect_no_align.

From-SVN: r260036

re PR c++/57429 (Dependent function call with one visible declaration, deleted)

2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/57429
* g++.dg/cpp0x/deleted14.C: New.

From-SVN: r260035

Backport of RISC-V support for libffi

* configure.host: Add RISC-V support.
* Makefile.am: Likewise.
* Makefile.in: Regenerate.
* src/riscv/ffi.c, src/riscv/ffitarget.h, src/riscv/sysv.S: New
files.

From-SVN: r260033

[arm] PR target/85658 Fix operator precedence errors in parsecpu.awk

There are a number of places in parsecpu.awk where I've managed to get
the operator precedence between ! and 'in' incorrect (! binds more
tightly).  In most cases this just makes a consistency test
ineffective, but in a few cases it means we fail to correctly diagnose
errors by the user (for example, when passing an invalid cpu or
architecture name to configure.  This patch fixes all the cases I
could find, based on searching for all uses of the two operators in
the same expression.  The tweak to the API of check_fpu is to bring it
into line with the other check functions - it now returns the result
rather than printing it directly.  The caller now does the printing,
in the same way that the chkarch and chkcpu commands do.

PR target/85658
* config/arm/parsecpu.awk (check_cpu): Fix operator precedence.
(check_arch): Likewise.
(check_fpu): Return the result rather than printing it.
(end arch): Fix operator precedence.
(end cpu): Likewise.
(END): Print the result from check_fpu.

From-SVN: r260032

[AArch64] Predicated SVE comparison folds

This patch adds SVE patterns that combine a PTRUE-predicated
comparison with a separate AND.  The main benefit is for
optimising ANDs with the loop predicate, as in the testcase.
However, one of the potential drawbacks is that it triggers
even for cases in which two naturally-parallel comparisons
are ANDed together.  Whether that's a win or a less will
depend on the schedule, but it has the potential to be a win
more often than a loss.

The combine patterns are undeniably ugly.  One way of getting
around them would be to allow 1->1 "splits" when combining
2 instructions, as well as 1->2 splits when combining more
than 2 instructions (although that wouldn't really be a split).
Another would be to have a way of defining target-specific
rtx simplifications.  branches/ARM/sve-branch has a prototype
implementation of that, but it would need some clean-up before being
ready to submit.  It would also be good to make it closer to the
match.pd style.

Until then, I think what the combine patterns are doing is the
"correct" implementation given the current infrastructure.

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* config/aarch64/aarch64-sve.md (*pred_cmp<cmp_op><mode>_combine)
(*pred_cmp<cmp_op><mode>, *fcm<cmp_op><mode>_and_combine)
(*fcmuo<mode>_and_combine, *fcm<cmp_op><mode>_and)
(*fcmuo<mode>_and): New patterns.

gcc/testsuite/
* gcc.target/aarch64/sve/vcond_6.c: Do not expect any ANDs.
XFAIL the BIC test.
* gcc.target/aarch64/sve/vcond_7.c: New test.
* gcc.target/aarch64/sve/vcond_7_run.c: Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r260031

re PR c++/70563 (SFINAE fails when trying invalid template instantiation)

2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/70563
* g++.dg/cpp0x/sfinae62.C: New.

From-SVN: r260030

[AArch64] Use UNSPEC_MERGE_PTRUE for comparisons

This patch rewrites the SVE comparison handling so that it uses
UNSPEC_MERGE_PTRUE for comparisons that are known to be predicated
on a PTRUE, for consistency with other patterns.  Specific unspecs
are then only needed for truly predicated floating-point comparisons,
such as those used in the expansion of UNEQ for flag_trapping_math.

The patch also makes sure that the comparison expanders attach
a REG_EQUAL note to instructions that use UNSPEC_MERGE_PTRUE,
so passes can use that as an alternative to the unspec pattern.
(This happens automatically for optabs.  The problem was that
this code emits instruction patterns directly.)

No specific benefit on its own, but it lays the groundwork for
the next patch.

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* config/aarch64/iterators.md (UNSPEC_COND_LO, UNSPEC_COND_LS)
(UNSPEC_COND_HI, UNSPEC_COND_HS, UNSPEC_COND_UO): Delete.
(SVE_INT_CMP, SVE_FP_CMP): New code iterators.
(cmp_op, sve_imm_con): New code attributes.
(SVE_COND_INT_CMP, imm_con): Delete.
(cmp_op): Remove above unspecs from int attribute.
* config/aarch64/aarch64-sve.md (*vec_cmp<cmp_op>_<mode>): Rename
to...
(*cmp<cmp_op><mode>): ...this.  Use UNSPEC_MERGE_PTRUE instead of
comparison-specific unspecs.
(*vec_cmp<cmp_op>_<mode>_ptest): Rename to...
(*cmp<cmp_op><mode>_ptest): ...this and adjust likewise.
(*vec_cmp<cmp_op>_<mode>_cc): Rename to...
(*cmp<cmp_op><mode>_cc): ...this and adjust likewise.
(*vec_fcm<cmp_op><mode>): Rename to...
(*fcm<cmp_op><mode>): ...this and adjust likewise.
(*vec_fcmuo<mode>): Rename to...
(*fcmuo<mode>): ...this and adjust likewise.
(*pred_fcm<cmp_op><mode>): New pattern.
* config/aarch64/aarch64.c (aarch64_emit_unop, aarch64_emit_binop)
(aarch64_emit_sve_ptrue_op, aarch64_emit_sve_ptrue_op_cc): New
functions.
(aarch64_unspec_cond_code): Remove handling of LTU, GTU, LEU, GEU
and UNORDERED.
(aarch64_gen_unspec_cond, aarch64_emit_unspec_cond): Delete.
(aarch64_emit_sve_predicated_cond): New function.
(aarch64_expand_sve_vec_cmp_int): Use aarch64_emit_sve_ptrue_op_cc.
(aarch64_emit_unspec_cond_or): Replace with...
(aarch64_emit_sve_or_conds): ...this new function.  Use
aarch64_emit_sve_ptrue_op for the individual comparisons and
aarch64_emit_binop to OR them together.
(aarch64_emit_inverted_unspec_cond): Replace with...
(aarch64_emit_sve_inverted_cond): ...this new function.  Use
aarch64_emit_sve_ptrue_op for the comparison and
aarch64_emit_unop to invert the result.
(aarch64_expand_sve_vec_cmp_float): Update after the above
changes.  Use aarch64_emit_sve_ptrue_op for native comparisons.

From-SVN: r260029

[AArch64] Tweak sve/vcond_6.c test

sve/vcond_6.c was effectively testing a three-input logical operation,
since the result of BINOP needed to be ANDed with the loop predicate
before loading src[i].  This patch makes it really test a binary
operation instead.  A later patch will add (and optimise) the
three-operand case.

2018-05-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
* gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally
load from src[i].

From-SVN: r260028

re PR c++/80691 (Narrowing conversion in {} allowed in a SFINAE context)

2018-05-08  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/80691
* g++.dg/cpp0x/narrowing1.C: New.

From-SVN: r260027

re PR bootstrap/85571 (non-bootstrap-debug miscompare with trunk)

2018-05-08  Richard Biener  <rguenther@suse.de>

PR bootstrap/85571
config/
* bootstrap-lto-noplugin.mk: Disable compare.
* bootstrap-lto.mk: Supply contrib/compare-lto for do-compare.

contrib/
* compare-lto: New script derived from compare-debug.

From-SVN: r260026

re PR tree-optimization/85588 (-fwrapv miscompilation)

2018-05-08  Richard Biener  <rguenther@suse.de>

PR middle-end/85588
* gcc.dg/torture/pr85574.c: Rename to...
* gcc.dg/torture/pr85588.c: ... this.

From-SVN: r260024

re PR fortran/54613 ([F08] Add FINDLOC plus support MAXLOC/MINLOC with KIND=/BACK=)

2018-05-08  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/54613
* check.c (gfc_check_minmaxloc): Remove error for BACK not being
implemented.  Use gfc_logical_4_kind for BACK.
* simplify.c (min_max_choose): Add optional argument back_val.
Handle it.
(simplify_minmaxloc_to_scalar): Add argument back_val. Pass
back_val to min_max_choose.
(simplify_minmaxloc_to_nodim): Likewise.
(simplify_minmaxloc_to_array): Likewise.
(gfc_simplify_minmaxloc): Add argument back, handle it.
Pass back_val to specific simplification functions.
(gfc_simplify_minloc): Remove ATTRIBUTE_UNUSED from argument back,
pass it on to gfc_simplify_minmaxloc.
(gfc_simplify_maxloc): Likewise.
* trans-intrinsic.c (gfc_conv_intrinsic_minmaxloc): Adjust
comment. If BACK is true, use greater or equal (or lesser or
equal) insteal of greater (or lesser). Mark the condition of
having found a value which exceeds the limit as unlikely.

2018-05-08  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/54613
* m4/iforeach-s.m4: Remove assertion that back is zero.
* m4/iforeach.m4: Likewise.  Remove leading 'do'
before implementation start.
* m4/ifunction-s.m4: Remove assertion that back is zero.
* m4/ifunction.m4: Likewise.  Remove for loop if HAVE_BACK_ARG
is defined.
* m4/maxloc0.m4: Reorganize loops. Split loops between >= and =,
depending if back is true.  Mark the condition of having
found a value which exceeds the limit as unlikely.
* m4/minloc0.m4: Likewise.
* m4/maxloc1.m4: Likewise.
* m4/minloc1.m4: Likewise.
* m4/maxloc1s.m4: Handle back argument.
* m4/minloc1s.m4: Likewise.
* m4/maxloc2s.m4: Remove assertion that back is zero.
Remove special handling of loop start. Handle back argument.
* m4/minloc2s.m4: Likewise.
* generated/iall_i1.c: Regenerated.
* generated/iall_i16.c: Regenerated.
* generated/iall_i2.c: Regenerated.
* generated/iall_i4.c: Regenerated.
* generated/iall_i8.c: Regenerated.
* generated/iany_i1.c: Regenerated.
* generated/iany_i16.c: Regenerated.
* generated/iany_i2.c: Regenerated.
* generated/iany_i4.c: Regenerated.
* generated/iany_i8.c: Regenerated.
* generated/iparity_i1.c: Regenerated.
* generated/iparity_i16.c: Regenerated.
* generated/iparity_i2.c: Regenerated.
* generated/iparity_i4.c: Regenerated.
* generated/iparity_i8.c: Regenerated.
* generated/maxloc0_16_i1.c: Regenerated.
* generated/maxloc0_16_i16.c: Regenerated.
* generated/maxloc0_16_i2.c: Regenerated.
* generated/maxloc0_16_i4.c: Regenerated.
* generated/maxloc0_16_i8.c: Regenerated.
* generated/maxloc0_16_r10.c: Regenerated.
* generated/maxloc0_16_r16.c: Regenerated.
* generated/maxloc0_16_r4.c: Regenerated.
* generated/maxloc0_16_r8.c: Regenerated.
* generated/maxloc0_16_s1.c: Regenerated.
* generated/maxloc0_16_s4.c: Regenerated.
* generated/maxloc0_4_i1.c: Regenerated.
* generated/maxloc0_4_i16.c: Regenerated.
* generated/maxloc0_4_i2.c: Regenerated.
* generated/maxloc0_4_i4.c: Regenerated.
* generated/maxloc0_4_i8.c: Regenerated.
* generated/maxloc0_4_r10.c: Regenerated.
* generated/maxloc0_4_r16.c: Regenerated.
* generated/maxloc0_4_r4.c: Regenerated.
* generated/maxloc0_4_r8.c: Regenerated.
* generated/maxloc0_4_s1.c: Regenerated.
* generated/maxloc0_4_s4.c: Regenerated.
* generated/maxloc0_8_i1.c: Regenerated.
* generated/maxloc0_8_i16.c: Regenerated.
* generated/maxloc0_8_i2.c: Regenerated.
* generated/maxloc0_8_i4.c: Regenerated.
* generated/maxloc0_8_i8.c: Regenerated.
* generated/maxloc0_8_r10.c: Regenerated.
* generated/maxloc0_8_r16.c: Regenerated.
* generated/maxloc0_8_r4.c: Regenerated.
* generated/maxloc0_8_r8.c: Regenerated.
* generated/maxloc0_8_s1.c: Regenerated.
* generated/maxloc0_8_s4.c: Regenerated.
* generated/maxloc1_16_i1.c: Regenerated.
* generated/maxloc1_16_i16.c: Regenerated.
* generated/maxloc1_16_i2.c: Regenerated.
* generated/maxloc1_16_i4.c: Regenerated.
* generated/maxloc1_16_i8.c: Regenerated.
* generated/maxloc1_16_r10.c: Regenerated.
* generated/maxloc1_16_r16.c: Regenerated.
* generated/maxloc1_16_r4.c: Regenerated.
* generated/maxloc1_16_r8.c: Regenerated.
* generated/maxloc1_16_s1.c: Regenerated.
* generated/maxloc1_16_s4.c: Regenerated.
* generated/maxloc1_4_i1.c: Regenerated.
* generated/maxloc1_4_i16.c: Regenerated.
* generated/maxloc1_4_i2.c: Regenerated.
* generated/maxloc1_4_i4.c: Regenerated.
* generated/maxloc1_4_i8.c: Regenerated.
* generated/maxloc1_4_r10.c: Regenerated.
* generated/maxloc1_4_r16.c: Regenerated.
* generated/maxloc1_4_r4.c: Regenerated.
* generated/maxloc1_4_r8.c: Regenerated.
* generated/maxloc1_4_s1.c: Regenerated.
* generated/maxloc1_4_s4.c: Regenerated.
* generated/maxloc1_8_i1.c: Regenerated.
* generated/maxloc1_8_i16.c: Regenerated.
* generated/maxloc1_8_i2.c: Regenerated.
* generated/maxloc1_8_i4.c: Regenerated.
* generated/maxloc1_8_i8.c: Regenerated.
* generated/maxloc1_8_r10.c: Regenerated.
* generated/maxloc1_8_r16.c: Regenerated.
* generated/maxloc1_8_r4.c: Regenerated.
* generated/maxloc1_8_r8.c: Regenerated.
* generated/maxloc1_8_s1.c: Regenerated.
* generated/maxloc1_8_s4.c: Regenerated.
* generated/maxloc2_16_s1.c: Regenerated.
* generated/maxloc2_16_s4.c: Regenerated.
* generated/maxloc2_4_s1.c: Regenerated.
* generated/maxloc2_4_s4.c: Regenerated.
* generated/maxloc2_8_s1.c: Regenerated.
* generated/maxloc2_8_s4.c: Regenerated.
* generated/maxval_i1.c: Regenerated.
* generated/maxval_i16.c: Regenerated.
* generated/maxval_i2.c: Regenerated.
* generated/maxval_i4.c: Regenerated.
* generated/maxval_i8.c: Regenerated.
* generated/maxval_r10.c: Regenerated.
* generated/maxval_r16.c: Regenerated.
* generated/maxval_r4.c: Regenerated.
* generated/maxval_r8.c: Regenerated.
* generated/minloc0_16_i1.c: Regenerated.
* generated/minloc0_16_i16.c: Regenerated.
* generated/minloc0_16_i2.c: Regenerated.
* generated/minloc0_16_i4.c: Regenerated.
* generated/minloc0_16_i8.c: Regenerated.
* generated/minloc0_16_r10.c: Regenerated.
* generated/minloc0_16_r16.c: Regenerated.
* generated/minloc0_16_r4.c: Regenerated.
* generated/minloc0_16_r8.c: Regenerated.
* generated/minloc0_16_s1.c: Regenerated.
* generated/minloc0_16_s4.c: Regenerated.
* generated/minloc0_4_i1.c: Regenerated.
* generated/minloc0_4_i16.c: Regenerated.
* generated/minloc0_4_i2.c: Regenerated.
* generated/minloc0_4_i4.c: Regenerated.
* generated/minloc0_4_i8.c: Regenerated.
* generated/minloc0_4_r10.c: Regenerated.
* generated/minloc0_4_r16.c: Regenerated.
* generated/minloc0_4_r4.c: Regenerated.
* generated/minloc0_4_r8.c: Regenerated.
* generated/minloc0_4_s1.c: Regenerated.
* generated/minloc0_4_s4.c: Regenerated.
* generated/minloc0_8_i1.c: Regenerated.
* generated/minloc0_8_i16.c: Regenerated.
* generated/minloc0_8_i2.c: Regenerated.
* generated/minloc0_8_i4.c: Regenerated.
* generated/minloc0_8_i8.c: Regenerated.
* generated/minloc0_8_r10.c: Regenerated.
* generated/minloc0_8_r16.c: Regenerated.
* generated/minloc0_8_r4.c: Regenerated.
* generated/minloc0_8_r8.c: Regenerated.
* generated/minloc0_8_s1.c: Regenerated.
* generated/minloc0_8_s4.c: Regenerated.
* generated/minloc1_16_i1.c: Regenerated.
* generated/minloc1_16_i16.c: Regenerated.
* generated/minloc1_16_i2.c: Regenerated.
* generated/minloc1_16_i4.c: Regenerated.
* generated/minloc1_16_i8.c: Regenerated.
* generated/minloc1_16_r10.c: Regenerated.
* generated/minloc1_16_r16.c: Regenerated.
* generated/minloc1_16_r4.c: Regenerated.
* generated/minloc1_16_r8.c: Regenerated.
* generated/minloc1_16_s1.c: Regenerated.
* generated/minloc1_16_s4.c: Regenerated.
* generated/minloc1_4_i1.c: Regenerated.
* generated/minloc1_4_i16.c: Regenerated.
* generated/minloc1_4_i2.c: Regenerated.
* generated/minloc1_4_i4.c: Regenerated.
* generated/minloc1_4_i8.c: Regenerated.
* generated/minloc1_4_r10.c: Regenerated.
* generated/minloc1_4_r16.c: Regenerated.
* generated/minloc1_4_r4.c: Regenerated.
* generated/minloc1_4_r8.c: Regenerated.
* generated/minloc1_4_s1.c: Regenerated.
* generated/minloc1_4_s4.c: Regenerated.
* generated/minloc1_8_i1.c: Regenerated.
* generated/minloc1_8_i16.c: Regenerated.
* generated/minloc1_8_i2.c: Regenerated.
* generated/minloc1_8_i4.c: Regenerated.
* generated/minloc1_8_i8.c: Regenerated.
* generated/minloc1_8_r10.c: Regenerated.
* generated/minloc1_8_r16.c: Regenerated.
* generated/minloc1_8_r4.c: Regenerated.
* generated/minloc1_8_r8.c: Regenerated.
* generated/minloc1_8_s1.c: Regenerated.
* generated/minloc1_8_s4.c: Regenerated.
* generated/minloc2_16_s1.c: Regenerated.
* generated/minloc2_16_s4.c: Regenerated.
* generated/minloc2_4_s1.c: Regenerated.
* generated/minloc2_4_s4.c: Regenerated.
* generated/minloc2_8_s1.c: Regenerated.
* generated/minloc2_8_s4.c: Regenerated.
* generated/minval_i1.c: Regenerated.
* generated/minval_i16.c: Regenerated.
* generated/minval_i2.c: Regenerated.
* generated/minval_i4.c: Regenerated.
* generated/minval_i8.c: Regenerated.
* generated/minval_r10.c: Regenerated.
* generated/minval_r16.c: Regenerated.
* generated/minval_r4.c: Regenerated.
* generated/minval_r8.c: Regenerated.
* generated/norm2_r10.c: Regenerated.
* generated/norm2_r16.c: Regenerated.
* generated/norm2_r4.c: Regenerated.
* generated/norm2_r8.c: Regenerated.
* generated/parity_l1.c: Regenerated.
* generated/parity_l16.c: Regenerated.
* generated/parity_l2.c: Regenerated.
* generated/parity_l4.c: Regenerated.
* generated/parity_l8.c: Regenerated.
* generated/product_c10.c: Regenerated.
* generated/product_c16.c: Regenerated.
* generated/product_c4.c: Regenerated.
* generated/product_c8.c: Regenerated.
* generated/product_i1.c: Regenerated.
* generated/product_i16.c: Regenerated.
* generated/product_i2.c: Regenerated.
* generated/product_i4.c: Regenerated.
* generated/product_i8.c: Regenerated.
* generated/product_r10.c: Regenerated.
* generated/product_r16.c: Regenerated.
* generated/product_r4.c: Regenerated.
* generated/product_r8.c: Regenerated.
* generated/sum_c10.c: Regenerated.
* generated/sum_c16.c: Regenerated.
* generated/sum_c4.c: Regenerated.
* generated/sum_c8.c: Regenerated.
* generated/sum_i1.c: Regenerated.
* generated/sum_i16.c: Regenerated.
* generated/sum_i2.c: Regenerated.
* generated/sum_i4.c: Regenerated.
* generated/sum_i8.c: Regenerated.
* generated/sum_r10.c: Regenerated.
* generated/sum_r16.c: Regenerated.
* generated/sum_r4.c: Regenerated.
* generated/sum_r8.c: Regenerated.

2018-05-08  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/54613
* gfortran.dg/minmaxloc_12.f90: New test case.
* gfortran.dg/minmaxloc_13.f90: New test case.

From-SVN: r260023

Daily bump.

From-SVN: r260021

PR c++/85646 - lambda visibility.

* decl2.c (determine_visibility): Don't mess with template arguments
from the containing scope.
(vague_linkage_p): Check DECL_ABSTRACT_P before looking at a 'tor
thunk.

From-SVN: r260017

[C++ PATCH] Kill -fno-for-scope

https://gcc.gnu.org/ml/gcc-patches/2018-05/msg00299.html
gcc/cp/
Remove fno-for-scope
* cp-tree.h (DECL_ERROR_REPORTED, DECL_DEAD_FOR_LOCAL)
(DECL_HAS_SHADOWED_FOR_VAR_P, DECL_SHADOWED_FOR_VAR)
(SET_DECL_SHADOWED_FOR_VAR): Delete.
(decl_shadowed_for_var_lookup, decl_shadowed_for_var_insert)
(check_for_out_of_scope_variable, init_shadowed_var_for_decl):
Don't declare.
* name-lookup.h (struct cp_binding_level): Remove
dead_vars_from_for field.
* cp-lang.c (cp_init_ts): Delete.
(LANG_HOOKS_INIT_TS): Override to cp_common_init_ts.
* cp-objcp-common.c (shadowed_var_for_decl): Delete.
(decl_shadowed_for_var_lookup, decl_shadowed_for_var_insert)
(init_shadowed_var_for_decl): Delete.
* decl.c (poplevel): Remove shadowed for var handling.
(cxx_init_decl_processing): Remove -ffor-scope deprecation.
* name-lookup.c (find_local_binding): Remove shadowed for var
handling.
(check_local_shadow): Likewise.
(check_for_out_of_scope_variable): Delete.
* parser.c (cp_parser_primary_expression): Remove shadowed for var
handling.
* pt.c (tsubst_decl): Remove DECL_DEAD_FOR_LOCAL setting.
* semantics.c (begin_for_scope): Always have a scope.
(begin_for_stmt, finish_for_stmt): Remove ARM-for scope handling.
(begin_range_for_stmt, finish_id_expression): Likewise.

gcc/
* doc/invoke.texi (C++ Dialect Options): Remove -ffor-scope.
* doc/extend.texi (Deprecated Features): Remove -fno-for-scope
(Backwards Compatibility): Likewise.

c-family/
* c.opt (ffor-scope): Remove functionality, issue warning.

gcc/objcp/
* objcp-lang.c (objcxx_init_ts): Don't call init_shadowed_var_for_decl.

gcc/testsuite/
* g++.dg/cpp0x/range-for10.C: Delete.
* g++.dg/ext/forscope1.C: Delete.
* g++.dg/ext/forscope2.C: Delete.
* g++.dg/template/for1.C: Delete.

From-SVN: r260015

PR c++/85618 - ICE with initialized VLA.

* tree.c (vla_type_p): New.
* typeck2.c (store_init_value, split_nonconstant_init_1): Check it
rather than array_of_runtime_bound_p.

From-SVN: r260012

Document -lstdc++fs requirement for std::filesystem

* doc/xml/manual/using.xml (table.cmd_options): Document that the
C++17 Filesystem implementation also needs -lstdc++fs.

From-SVN: r260011

scanner.c (preprocessor_line): Call linemap_add after a line directive that changes the current filename.

* scanner.c (preprocessor_line): Call linemap_add after a line
directive that changes the current filename.

* gfortran.dg/linefile.f90: New test.

From-SVN: r260010

PR libstdc++/85671 allow copy elision in path concatenation

By performing the /= operation on a named local variable instead of a
temporary the copy made for the return value can be elided.

PR libstdc++/85671
* include/bits/fs_path.h (operator/): Permit copy elision.
* include/experimental/bits/fs_path.h (operator/): Likewise.

From-SVN: r260009

Moar PR libstdc++/80506

2018-05-07  Edward Smith-Rowland  <3dw4rd@verizon.net>

Moar PR libstdc++/80506
* include/bits/random.tcc (gamma_distribution::__generate_impl()):
Fix magic number used in loop condition.

Actually put the file in.
Don't know what my problem is today...

From-SVN: r260008

config.host (x86_64-*-rtems*): Build crti.o and crtn.o.

2018-05-07  Amaan Cheval  <amaan.cheval@gmail.com>

* config.host (x86_64-*-rtems*): Build crti.o and crtn.o.

From-SVN: r260007

Moar PR libstdc++/80506

2018-05-07  Edward Smith-Rowland  <3dw4rd@verizon.net>

Moar PR libstdc++/80506
* include/bits/random.tcc (gamma_distribution::__generate_impl()):
Fix magic number used in loop condition.

From-SVN: r260004

Rollback bad commits!  Sorry!

From-SVN: r260003

Revert 20001.

From-SVN: r260002

Moar PR libstdc++/80506

2018-05-07  Edward Smith-Rowland  <3dw4rd@verizon.net>

Moar PR libstdc++/80506
* include/bits/random.tcc (gamma_distribution::__generate_impl()):
Fix magic number used in loop condition.

From-SVN: r260001

re PR bootstrap/85681 (r259995 breaks bootstrap on x86_64-*-freebsd)

2018-05-07  Luis Machado  <luis.machado@linaro.org>

PR bootstrap/85681
Revert:
2018-05-07  Luis Machado  <luis.machado@linaro.org>

* config/aarch64/aarch64-protos.h (cpu_prefetch_tune)
<prefetch_dynamic_strides>: New const bool field.
* config/aarch64/aarch64.c (generic_prefetch_tune): Update to include
prefetch_dynamic_strides.
(exynosm1_prefetch_tune): Likewise.
(thunderxt88_prefetch_tune): Likewise.
(thunderx_prefetch_tune): Likewise.
(thunderx2t99_prefetch_tune): Likewise.
(qdf24xx_prefetch_tune): Likewise. Set prefetch_dynamic_strides to false.
(aarch64_override_options_internal): Update to set
PARAM_PREFETCH_DYNAMIC_STRIDES.
* doc/invoke.texi (prefetch-dynamic-strides): Document new option.
* params.def (PARAM_PREFETCH_DYNAMIC_STRIDES): New.
* params.h (PARAM_PREFETCH_DYNAMIC_STRIDES): Define.
* tree-ssa-loop-prefetch.c (should_issue_prefetch_p): Account for
prefetch-dynamic-strides setting.

2018-05-07  Luis Machado  <luis.machado@linaro.org>

* config/aarch64/aarch64-protos.h (cpu_prefetch_tune)
<minimum_stride>: New const int field.
* config/aarch64/aarch64.c (generic_prefetch_tune): Update to include
minimum_stride field.
(exynosm1_prefetch_tune): Likewise.
(thunderxt88_prefetch_tune): Likewise.
(thunderx_prefetch_tune): Likewise.
(thunderx2t99_prefetch_tune): Likewise.
(qdf24xx_prefetch_tune): Likewise. Set minimum_stride to 2048.
(aarch64_override_options_internal): Update to set
PARAM_PREFETCH_MINIMUM_STRIDE.
* doc/invoke.texi (prefetch-minimum-stride): Document new option.
* params.def (PARAM_PREFETCH_MINIMUM_STRIDE): New.
* params.h (PARAM_PREFETCH_MINIMUM_STRIDE): Define.
* tree-ssa-loop-prefetch.c (should_issue_prefetch_p): Return false if
stride is constant and is below the minimum stride threshold.

From-SVN: r260000

Fix gcc/ChangeLog.

From-SVN: r259999

aarch64.c (qdf24xx_prefetch_tune): Set to 512.

2018-05-07  Luis Machado  <luis.machado@linaro.org>

* config/aarch64/aarch64.c (qdf24xx_prefetch_tune) <l2_cache_size>: Set
to 512.

From-SVN: r259998

Introduce prefetch-dynamic-strides option.

The following patch adds an option to control software prefetching of memory
references with non-constant/unknown strides.

Currently we prefetch these references if the pass thinks there is benefit to
doing so. But, since this is all based on heuristics, it's not always the case
that we end up with better performance.

For Falkor there is also the problem of conflicts with the hardware prefetcher,
so we need to be more conservative in terms of what we issue software prefetch
hints for.

This also aligns GCC with what LLVM does for Falkor.

Similarly to the previous patch, the defaults guarantee no change in behavior
for other targets and architectures.

2018-05-07  Luis Machado  <luis.machado@linaro.org>

gcc/
* config/aarch64/aarch64-protos.h (cpu_prefetch_tune)
<prefetch_dynamic_strides>: New const bool field.
* config/aarch64/aarch64.c (generic_prefetch_tune): Update to include
prefetch_dynamic_strides.
(exynosm1_prefetch_tune): Likewise.
(thunderxt88_prefetch_tune): Likewise.
(thunderx_prefetch_tune): Likewise.
(thunderx2t99_prefetch_tune): Likewise.
(qdf24xx_prefetch_tune): Likewise. Set prefetch_dynamic_strides to false.
(aarch64_override_options_internal): Update to set
PARAM_PREFETCH_DYNAMIC_STRIDES.
* doc/invoke.texi (prefetch-dynamic-strides): Document new option.
* params.def (PARAM_PREFETCH_DYNAMIC_STRIDES): New.
* params.h (PARAM_PREFETCH_DYNAMIC_STRIDES): Define.
* tree-ssa-loop-prefetch.c (should_issue_prefetch_p): Account for
prefetch-dynamic-strides setting.

From-SVN: r259996

Introduce prefetch-minimum stride option

This patch adds a new option to control the minimum stride, for a memory
reference, after which the loop prefetch pass may issue software prefetch
hints for. There are two motivations:

* Make the pass less aggressive, only issuing prefetch hints for bigger strides
that are more likely to benefit from prefetching. I've noticed a case in cpu2017
where we were issuing thousands of hints, for example.

* For processors that have a hardware prefetcher, like Falkor, it allows the
loop prefetch pass to defer prefetching of smaller (less than the threshold)
strides to the hardware prefetcher instead. This prevents conflicts between
the software prefetcher and the hardware prefetcher.

I've noticed considerable reduction in the number of prefetch hints and
slightly positive performance numbers. This aligns GCC and LLVM in terms of
prefetch behavior for Falkor.

The default settings should guarantee no changes for existing targets. Those
are free to tweak the settings as necessary.

2018-05-07  Luis Machado  <luis.machado@linaro.org>

Introduce option to limit software prefetching to known constant
strides above a specific threshold with the goal of preventing
conflicts with a hardware prefetcher.

gcc/
* config/aarch64/aarch64-protos.h (cpu_prefetch_tune)
<minimum_stride>: New const int field.
* config/aarch64/aarch64.c (generic_prefetch_tune): Update to include
minimum_stride field.
(exynosm1_prefetch_tune): Likewise.
(thunderxt88_prefetch_tune): Likewise.
(thunderx_prefetch_tune): Likewise.
(thunderx2t99_prefetch_tune): Likewise.
(qdf24xx_prefetch_tune): Likewise. Set minimum_stride to 2048.
(aarch64_override_options_internal): Update to set
PARAM_PREFETCH_MINIMUM_STRIDE.
* doc/invoke.texi (prefetch-minimum-stride): Document new option.
* params.def (PARAM_PREFETCH_MINIMUM_STRIDE): New.
* params.h (PARAM_PREFETCH_MINIMUM_STRIDE): Define.
* tree-ssa-loop-prefetch.c (should_issue_prefetch_p): Return false if
stride is constant and is below the minimum stride threshold.

From-SVN: r259995

[testsuite] gcc.dg/nextafter-2.c: Restrict to c99_runtime

2018-05-07  Christophe Lyon  <christophe.lyon@linaro.org>

* gcc.dg/nextafter-2.c: Add c99_runtime effective target
and options.

From-SVN: r259994

[openacc, testsuite] Allow installed testing of libgomp to find gomp-constants.h

2018-05-07  Tom de Vries  <tom@codesourcery.com>

PR testsuite/85677
* testsuite/lib/libgomp.exp (libgomp_init): Move inclusion of top-level
include directory in ALWAYS_CFLAGS out of $blddir != "" condition.

From-SVN: r259992

Daily bump.

From-SVN: r259986

re PR c++/85659 (ICE with inline assembly inside virtual function)

PR c++/85659
* cfgexpand.c (expand_asm_stmt): Don't create a temporary if
the type is addressable.  Don't force op into register if it has
BLKmode.

* g++.dg/ext/asm14.C: New test.
* g++.dg/ext/asm15.C: New test.
* g++.dg/ext/asm16.C: New test.

From-SVN: r259981

picdtr.c: Correct option -fPIE -mpic-data-is-text-relative.

2018-05-06  Michael Eager  <eager@eagercon.com>

* gcc.target/microblaze/others/picdtr.c: Correct option
 -fPIE -mpic-data-is-text-relative.

From-SVN: r259976

picdtr.c: Add test for -fPIE -mpic-data-is-text-relative.

2018-05-06  Andrew Sadek  <andrew.sadek.se@gmail.com>

* gcc.target/microblaze/others/picdtr.c: Add test for
 -fPIE -mpic-data-is-text-relative.

From-SVN: r259975

re PR fortran/85507 (ICE in gfc_dep_resolver, at fortran/dependency.c:2258)

gcc/fortran/ChangeLog:

2018-05-06  Andre Vehreschild  <vehre@gcc.gnu.org>

PR fortran/85507
* dependency.c (gfc_dep_resolver): Revert looking at coarray dimension
introduced by r259385.
* trans-intrinsic.c (conv_caf_send): Always report a dependency for
same variables in coarray assignments.

gcc/testsuite/ChangeLog:

2018-05-06  Andre Vehreschild  <vehre@gcc.gnu.org>

PR fortran/85507
* gfortran.dg/coarray_dependency_1.f90: New test.
* gfortran.dg/coarray_lib_comm_1.f90: Fix counting caf-expressions.

From-SVN: r259974

Daily bump.

From-SVN: r259973

PR other/77609: Let the assembler choose ELF section types for miscellaneous named sections

gcc/
PR other/77609
* varasm.c (default_section_type_flags): Set SECTION_NOTYPE for
any section for which we don't know a specific type it should have,
regardless of name.  Previously this was done only for the exact
names ".init_array", ".fini_array", and ".preinit_array".
(default_elf_asm_named_section): Add comment about
relationship with default_section_type_flags and SECTION_NOTYPE.
(get_section): Don't consider it a type conflict if one side has
SECTION_NOTYPE and the other doesn't, as long as neither has the
SECTION_BSS et al used in the default_section_type_flags logic.

From-SVN: r259969

[nvptx] Add workaround for subsequent bar.syncs

2018-05-05  Tom de Vries  <tom@codesourcery.com>

PR target/85653
* config/nvptx/nvptx.c (WORKAROUND_PTXJIT_BUG_3): Define.
(workaround_barsyncs): New function.
(nvptx_reorg): Use workaround_barsyncs.
* config/nvptx/nvptx.md (define_c_enum "unspecv"): Add UNSPECV_MEMBAR.
(define_expand "nvptx_membar_cta"): New define_expand.
(define_insn "*nvptx_membar_cta"): New insn.

From-SVN: r259967

cvt.c (ocp_convert): Early handle the special case of a null_ptr_cst_p expr converted to a...

2018-05-05  Paolo Carlini  <paolo.carlini@oracle.com>

* cvt.c (ocp_convert): Early handle the special case of a
null_ptr_cst_p expr converted to a NULLPTR_TYPE_P type.

From-SVN: r259966

Daily bump.

From-SVN: r259965

[BRIGFE] Fix handling of NOPs.

From-SVN: r259958

[BRIGFE] phsa-specific optimizations

Add flag -fassume-phsa that is on by default. If -fno-assume-phsa
is given, these optimizations are disabled.

With this flag, gccbrig can generate GENERIC that assumes we are
targeting a phsa-runtime based implementation, which allows us
to expose the work-item context accesses to retrieve WI IDs etc.
which helps optimizers.

First optimization that takes advantage of this is to get rid of
the setworkitemid calls whenever we have non-inlined calls that
use IDs internally.

Other optimizations added in this commit:

- expand absoluteid to similar level of simplicity as workitemid.
At the moment absoluteid is the best indexing ID to end up with
WG vectorization.
- propagate ID variables closer to their uses. This is mainly
to avoid known useless casts, which confuse at least scalar
evolution analysis.
- use signed long long for storing IDs. Unsigned integers have
defined wraparound semantics, which confuse at least scalar
evolution analysis, leading to unvectorizable WI loops.
- also refactor some BRIG function generation helpers to brig_function.
- no point in having the wi-loop as a for-loop. It's really
a do...while and SCEV can analyze it just fine still.
- add consts to ptrs etc. in BRIG builtin defs.
Improves optimization opportunities.
- add qualifiers to generated function parameters.
Const and restrict on the hidden local/private pointers,
the arg buffer and the context pointer help some optimizations.

From-SVN: r259957

[BRIGFE] skip multiple forward declarations of the same function

From-SVN: r259950

[BRIGFE] do not allow optimizations based on known C builtins

It can break inputs that have similarly named functions.

From-SVN: r259949

[BRIGFE] allow controlling strict aliasing from cmd line

From-SVN: r259948

cmd/go: on AIX, pass -X64 first when invoking ar

    Reviewed-on: https://go-review.googlesource.com/111535

From-SVN: r259946

[BRIGFE] The modulo in ID computation should not be needed.

The case where a dim is greater than the grid size doesn't seem
to be mentioned in the specs nor tested by PRM test suite.

From-SVN: r259944

[BRIGFE] Enable whole program optimizations

HSA assumes all program scope HSAIL symbols can be queried from
the host runtime API, thus cannot be removed by the IPA.

Getting some inlining happening in the finalized binary required:
* explicitly marking the 'prog' scope functions and the launcher
function "externally_visible" to avoid the inliner removing it
* also the host_def ptr is set to externally visible, otherwise
IPA assumes it's never set
* adding the 'inline' keyword to functions to enable inlining,
otherwise GCC defaults to replaceable functions (one can link
over the previous one) which cannot be inlined
* replacing all calls to declarations with calls to definitions to
enable the inliner to find the definition
* to fix missing hidden argument types in the generated functions.
These were ignored silently until GCC started to be able to
inline calls to such functions.
* do not gimplify before fixing the call targets. Otherwise the
calls get detached and the definitions are not found. The reason
why this happens is not clear, but gimplifying only after call
target decl->def conversion fixes this.

From-SVN: r259943

[BRIGFE] fix an alloca stack underflow

We didn't preserve additional space for the alloca frame pointers that
are needed to be saved in the alloca space.

Fixes libgomp.c++/target-6.C execution test.

From-SVN: r259942

* uk.po: Update.

From-SVN: r259938

re PR go/85630 (GCC 8.1.0: Filesystem pollution during build: .cache dir in $HOME)

PR go/85630
* Makefile.am (CHECK_ENV): Set GOCACHE.
(ECHO_ENV): Update for setting of GOCACHE.
* Makefile.in: Rebuild.

From-SVN: r259937

vsx-vector-6.h (foo): Add test for vec_max, vec_trunc.

gcc/testsuite/ChangeLog:

2018-05-04 Carl Love  <cel@us.ibm.com>
* gcc.target/powerpc/vsx-vector-6.h (foo): Add test for vec_max,
vec_trunc.
* gcc.target/powerpc/vsx-vector-6-le.c (dg-final): Update xvcmpeqdp,
xvcmpgtdp, xvcmpgedp counts. Add xxsel counts.
* gcc.target/powerpc/vsx-vector-6-be.c (dg-final): Update xvcmpgtdp,
xvcmpgedp counts. Add xxsel counts.

From-SVN: r259936

libgo: fix for unaligned read in go-unwind.c's read_encoded_value()

    Change code to work properly reading unaligned data on architectures
    that don't support unaliged reads. This fixes a regression (broke
    Solaris/sparc) introduced in https://golang.org/cl/90235.

    Reviewed-on: https://go-review.googlesource.com/111296

From-SVN: r259935

libffi PowerPC64 ELFv1 fp arg fixes

The ELFv1 ABI says: "Single precision floating point values are mapped
to the second word in a single doubleword" and also "Floating point
registers f1 through f13 are used consecutively to pass up to 13
floating point values, one member aggregates passed by value
containing a floating point value, and to pass complex floating point
values".

libffi wasn't expecting float args in the second word, and wasn't
passing one member aggregates in fp registers.  This patch fixes those
problems, making use of the existing ELFv2 homogeneous aggregate
support since a one element fp struct is a special case of an
homogeneous aggregate.

I've also set a flag when returning pointers that might be used one
day.  This is just a tidy since the ppc64 assembly support code
currently doesn't test FLAG_RETURNS_64BITS for integer types..

* src/powerpc/ffi_linux64.c (discover_homogeneous_aggregate):
Compile for ELFv1 too, handling single element aggregates.
(ffi_prep_cif_linux64_core): Call discover_homogeneous_aggregate
for ELFv1.  Set FLAG_RETURNS_64BITS for FFI_TYPE_POINTER return.
(ffi_prep_args64): Call discover_homogeneous_aggregate for ELFv1,
and handle single element structs containing float or double
as if the element wasn't wrapped in a struct.  Store floats in
second word of doubleword slot when big-endian.
(ffi_closure_helper_LINUX64): Similarly.

From-SVN: r259934

bb-reorder.c (sanitize_hot_paths): Release hot_bbs_to_check.

2018-05-04  Richard Biener  <rguenther@suse.de>

* bb-reorder.c (sanitize_hot_paths): Release hot_bbs_to_check.
* gimple-ssa-store-merging.c
(imm_store_chain_info::output_merged_store): Remove redundant create,
release split_store vector contents on failure.
* tree-vect-slp.c (vect_schedule_slp_instance): Avoid leaking
scalar stmt vector on cache hit.

From-SVN: r259932

rs6000: Remove Xilinx FP

This removes the special Xilinx FP support.  It was deprecated in
GCC 8.

After this patch all of TARGET_{DOUBLE,SINGLE}_FLOAT,
TARGET_{DF,SF}_INSN, and TARGET_{DF,SF}_FPR are replaced by
TARGET_HARD_FLOAT.  Also the fp_type attribute is deleted.

* common/config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
Xilinx FP support.
* config.gcc (powerpc-xilinx-eabi*): Remove.
* config/rs6000/predicates.md (easy_fp_constant): Remove Xilinx FP
support.
(fusion_addis_mem_combo_load): Ditto.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove Xilinx
FP support.
(rs6000_cpu_cpp_builtins): Ditto.
* config/rs6000/rs6000-linux.c
(rs6000_linux_float_exceptions_rounding_supported_p): Ditto.
* config/rs6000/rs6000-opts.h (enum fpu_type_t): Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove Xilinx FP
support.
(rs6000_setup_reg_addr_masks): Ditto.
(rs6000_init_hard_regno_mode_ok): Ditto.
(rs6000_option_override_internal): Ditto.
(legitimate_lo_sum_address_p): Ditto.
(rs6000_legitimize_address): Ditto.
(rs6000_legitimize_reload_address): Ditto.
(rs6000_legitimate_address_p): Ditto.
(abi_v4_pass_in_fpr): Ditto.
(setup_incoming_varargs): Ditto.
(rs6000_gimplify_va_arg): Ditto.
(rs6000_split_multireg_move): Ditto.
(rs6000_savres_strategy): Ditto.
(rs6000_emit_prologue_components): Ditto.
(rs6000_emit_epilogue_components): Ditto.
(rs6000_emit_prologue): Ditto.
(rs6000_emit_epilogue): Ditto.
(rs6000_elf_file_end): Ditto.
(rs6000_function_value): Ditto.
(rs6000_libcall_value): Ditto.
* config/rs6000/rs6000.h: Ditto.
(TARGET_MINMAX_SF, TARGET_MINMAX_DF): Delete, merge to ...
(TARGET_MINMAX): ... this.  New.
(TARGET_SF_FPR, TARGET_DF_FPR, TARGET_SF_INSN, TARGET_DF_INSN): Delete.
* config/rs6000/rs6000.md: Remove Xilinx FP support.
(*movsi_internal1_single): Delete.
* config/rs6000/rs6000.opt (msingle-float, mdouble-float, msimple-fpu,
mfpu=, mxilinx-fpu): Delete.
* config/rs6000/singlefp.h: Delete.
* config/rs6000/sysv4.h: Remove Xilinx FP support.
* config/rs6000/t-rs6000: Ditto.
* config/rs6000/t-xilinx: Delete.
* gcc/config/rs6000/titan.md: Adjust for fp_type removal.
* gcc/config/rs6000/vsx.md: Remove Xilinx FP support.
(VStype_simple): Delete.
(VSfptype_simple, VSfptype_mul, VSfptype_div, VSfptype_sqrt): Delete.
* config/rs6000/xfpu.h: Delete.
* config/rs6000/xfpu.md: Delete.
* config/rs6000/xilinx.h: Delete.
* config/rs6000/xilinx.opt: Delete.
* gcc/doc/invoke.texi (RS/6000 and PowerPC Options): Remove
-msingle-float, -mdouble-float, -msimple-fpu, -mfpu=, and -mxilinx-fpu.

From-SVN: r259929

PR libstdc++/85642 fix is_nothrow_default_constructible<optional<T>>

Add missing noexcept keyword to default constructor of each
_Optional_payload specialization.

PR libstdc++/85642 fix is_nothrow_default_constructible<optional<T>>
* include/std/optional (_Optional_payload): Add noexcept to default
constructor. Re-indent.
(_Optional_payload<_Tp, true, true, true>): Likewise. Add noexcept to
constructor for copying disengaged payloads.
(_Optional_payload<_Tp, true, false, true>): Likewise.
(_Optional_payload<_Tp, true, true, false>): Likewise.
(_Optional_payload<_Tp, true, false, false>): Likewise.
* testsuite/20_util/optional/cons/85642.cc: New.
* testsuite/20_util/optional/cons/value_neg.cc: Adjust dg-error lines.

From-SVN: r259928

[expand] Handle null target in expand_builtin_goacc_parlevel_id_size

2018-05-04  Tom de Vries  <tom@codesourcery.com>

PR libgomp/85639
* builtins.c (expand_builtin_goacc_parlevel_id_size): Handle null target
if ignore == 0.

From-SVN: r259927

re PR ada/85635 (typo in link.c for BSD platforms)

PR ada/85635
* link.c (BSD platforms): Add missing backslash.

From-SVN: r259925