Eddie Hung [Sat, 10 Aug 2019 00:05:56 +0000 (17:05 -0700)]
Add wreduce to synth_ice40 -dsp as well
Eddie Hung [Fri, 9 Aug 2019 23:23:32 +0000 (16:23 -0700)]
Another filter -> if
Eddie Hung [Fri, 9 Aug 2019 22:47:40 +0000 (15:47 -0700)]
Cleanup
Eddie Hung [Fri, 9 Aug 2019 22:19:33 +0000 (15:19 -0700)]
Pack partial-product adder DSP48E1 packing
Eddie Hung [Fri, 9 Aug 2019 21:27:08 +0000 (14:27 -0700)]
Fix check
Eddie Hung [Fri, 9 Aug 2019 21:14:28 +0000 (14:14 -0700)]
Eddie Hung [Thu, 8 Aug 2019 23:33:37 +0000 (16:33 -0700)]
Remove muxY and ffY for now
Eddie Hung [Thu, 8 Aug 2019 23:33:20 +0000 (16:33 -0700)]
Remove signed from ports in +/xilinx/dsp_map.v
Eddie Hung [Thu, 8 Aug 2019 19:56:05 +0000 (12:56 -0700)]
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
Eddie Hung [Thu, 8 Aug 2019 17:55:48 +0000 (10:55 -0700)]
Combine techmap calls
Eddie Hung [Thu, 8 Aug 2019 17:51:19 +0000 (10:51 -0700)]
Only pack registers if {A,B,P}REG = 0, do not pack $dffe
Eddie Hung [Thu, 8 Aug 2019 17:45:56 +0000 (10:45 -0700)]
Move xilinx_dsp to before alumacc
Eddie Hung [Thu, 8 Aug 2019 17:44:49 +0000 (10:44 -0700)]
Disable $dffe
Eddie Hung [Thu, 8 Aug 2019 17:44:35 +0000 (10:44 -0700)]
INMODE is 5 bits
Eddie Hung [Thu, 8 Aug 2019 17:44:26 +0000 (10:44 -0700)]
Fix copy-pasta typo
David Shah [Thu, 8 Aug 2019 14:18:59 +0000 (15:18 +0100)]
ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 14:14:09 +0000 (15:14 +0100)]
ecp5: Bring up to date with mul2dsp changes
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 10:40:09 +0000 (11:40 +0100)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
David Shah [Thu, 8 Aug 2019 10:39:35 +0000 (11:39 +0100)]
DSP48E1 sim model: add SIMD tests
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 10:32:43 +0000 (11:32 +0100)]
DSP48E1 model: test CE inputs
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 10:18:37 +0000 (11:18 +0100)]
DSP48E1 sim model: fix seq tests and add preadder tests
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 09:52:04 +0000 (10:52 +0100)]
DSP48E1 sim model: seq test working
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 09:26:40 +0000 (10:26 +0100)]
DSP48E1 sim model: Comb, no pre-adder, mode working
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 09:05:11 +0000 (10:05 +0100)]
[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 8 Aug 2019 08:31:34 +0000 (09:31 +0100)]
[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Wed, 7 Aug 2019 21:31:55 +0000 (14:31 -0700)]
Fix compile error
Eddie Hung [Wed, 7 Aug 2019 20:59:07 +0000 (13:59 -0700)]
Run "opt_expr -fine" instead of "wreduce" due to #1213
Eddie Hung [Wed, 7 Aug 2019 20:58:26 +0000 (13:58 -0700)]
Do not SigSpec::extract() beyond bounds
Eddie Hung [Wed, 7 Aug 2019 20:44:08 +0000 (13:44 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Wed, 7 Aug 2019 19:57:10 +0000 (12:57 -0700)]
Do not pack registers if (* keep *)
Eddie Hung [Wed, 7 Aug 2019 19:25:26 +0000 (12:25 -0700)]
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup
abc9: speedup by using using "clean" more efficiently
Eddie Hung [Tue, 6 Aug 2019 20:20:32 +0000 (13:20 -0700)]
Add comment
Eddie Hung [Tue, 6 Aug 2019 20:19:21 +0000 (13:19 -0700)]
Eddie Hung [Fri, 2 Aug 2019 05:30:10 +0000 (22:30 -0700)]
Add TODO
Eddie Hung [Fri, 2 Aug 2019 05:21:56 +0000 (22:21 -0700)]
Compute box_lookup just once
Eddie Hung [Fri, 2 Aug 2019 05:21:30 +0000 (22:21 -0700)]
Run "clean" on mapped_mod in its own design
Eddie Hung [Fri, 2 Aug 2019 05:21:14 +0000 (22:21 -0700)]
Run "clean -purge" on holes_module in its own design
David Shah [Wed, 7 Aug 2019 14:35:29 +0000 (15:35 +0100)]
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
ecp5: Make cells_sim.v consistent with nextpnr
David Shah [Wed, 7 Aug 2019 13:19:31 +0000 (14:19 +0100)]
ecp5: Make cells_sim.v consistent with nextpnr
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Wed, 7 Aug 2019 12:27:35 +0000 (14:27 +0200)]
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
wreduce/opt_expr: improve width reduction for $add and $sub cells
David Shah [Wed, 7 Aug 2019 12:09:12 +0000 (13:09 +0100)]
[wip] DSP48E1 sim model improvements
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Wed, 7 Aug 2019 10:31:32 +0000 (12:31 +0200)]
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Clifford Wolf [Wed, 7 Aug 2019 10:30:52 +0000 (12:30 +0200)]
Merge pull request #1249 from mmicko/anlogic_fix
anlogic : Fix alu mapping
Clifford Wolf [Wed, 7 Aug 2019 10:14:54 +0000 (12:14 +0200)]
Merge pull request #1252 from YosysHQ/clifford/fix1231
Fix handling of functions/tasks without top-level begin-end block
Clifford Wolf [Wed, 7 Aug 2019 10:14:41 +0000 (12:14 +0200)]
Merge pull request #1253 from YosysHQ/clifford/check
Be less aggressive with running design->check()
Clifford Wolf [Wed, 7 Aug 2019 10:13:50 +0000 (12:13 +0200)]
Merge pull request #1257 from YosysHQ/clifford/cellcosts
Redesign of cell cost API
David Shah [Wed, 7 Aug 2019 09:56:32 +0000 (10:56 +0100)]
Update CHANGELOG
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 7 Aug 2019 09:40:38 +0000 (10:40 +0100)]
Merge pull request #1241 from YosysHQ/clifford/jsonfix
Improved JSON attr/param encoding
Clifford Wolf [Wed, 7 Aug 2019 08:25:51 +0000 (10:25 +0200)]
Tweak default gate costs, cleanup "stat -tech cmos"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 6 Aug 2019 23:12:14 +0000 (01:12 +0200)]
Redesign of cell cost API
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Tue, 6 Aug 2019 22:40:30 +0000 (15:40 -0700)]
Add signed opt_expr tests
Eddie Hung [Tue, 6 Aug 2019 22:38:43 +0000 (15:38 -0700)]
Add signed test
Eddie Hung [Tue, 6 Aug 2019 22:25:50 +0000 (15:25 -0700)]
Move LSB-trimming functionality from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 22:25:11 +0000 (15:25 -0700)]
Add SigSpec::extract_end() convenience function
Eddie Hung [Tue, 6 Aug 2019 22:24:55 +0000 (15:24 -0700)]
Restore original SigSpec::extract()
Eddie Hung [Tue, 6 Aug 2019 22:24:49 +0000 (15:24 -0700)]
Move LSB tests from wreduce to opt_expr
Eddie Hung [Tue, 6 Aug 2019 21:50:00 +0000 (14:50 -0700)]
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
David Shah [Tue, 6 Aug 2019 18:05:35 +0000 (19:05 +0100)]
Merge pull request #1232 from YosysHQ/dave/write_gzip
Add support for writing gzip-compressed files
David Shah [Tue, 6 Aug 2019 17:47:18 +0000 (18:47 +0100)]
[wip] DSP48E1 sim model improvements
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Tue, 6 Aug 2019 17:21:37 +0000 (19:21 +0200)]
Be less aggressive with running design->check()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Wed, 31 Jul 2019 12:58:27 +0000 (13:58 +0100)]
Add test for writing gzip-compressed files
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Mon, 29 Jul 2019 08:28:31 +0000 (09:28 +0100)]
Add support for writing gzip-compressed files
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Tue, 6 Aug 2019 16:06:14 +0000 (18:06 +0200)]
Fix handling of functions/tasks without top-level begin-end block, fixes #1231
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 6 Aug 2019 13:18:18 +0000 (15:18 +0200)]
Merge pull request #1251 from YosysHQ/clifford/nmux
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
David Shah [Tue, 6 Aug 2019 12:23:42 +0000 (13:23 +0100)]
[wip] DSP48E1 sim model improvements
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Tue, 6 Aug 2019 02:47:55 +0000 (04:47 +0200)]
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Miodrag Milanovic [Sat, 3 Aug 2019 12:47:33 +0000 (14:47 +0200)]
anlogic : Fix alu mapping
whitequark [Sat, 3 Aug 2019 07:08:41 +0000 (07:08 +0000)]
Merge pull request #1242 from jfng/fix-proc_prune-partial
proc_prune: Promote partially redundant assignments.
Clifford Wolf [Fri, 2 Aug 2019 15:07:39 +0000 (17:07 +0200)]
Merge pull request #1238 from mmicko/vsbuild_fix
Visual Studio build fix
Clifford Wolf [Fri, 2 Aug 2019 14:37:57 +0000 (16:37 +0200)]
Merge pull request #1239 from mmicko/mingw_fix
Fix formatting for msys2 mingw build
Eddie Hung [Thu, 1 Aug 2019 22:13:18 +0000 (15:13 -0700)]
Add comment about supporting $dffe in ice40_dsp
Eddie Hung [Thu, 1 Aug 2019 22:10:43 +0000 (15:10 -0700)]
Pack P register properly
Eddie Hung [Thu, 1 Aug 2019 21:33:16 +0000 (14:33 -0700)]
Trim Y_WIDTH
Eddie Hung [Thu, 1 Aug 2019 21:29:00 +0000 (14:29 -0700)]
Add DSP_SIGNEDONLY back
Eddie Hung [Thu, 1 Aug 2019 20:20:34 +0000 (13:20 -0700)]
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
Eddie Hung [Thu, 1 Aug 2019 19:45:14 +0000 (12:45 -0700)]
Change $__softmul back to $mul
Eddie Hung [Thu, 1 Aug 2019 19:44:56 +0000 (12:44 -0700)]
Cope with sign extension in mul2dsp
Eddie Hung [Thu, 1 Aug 2019 19:17:14 +0000 (12:17 -0700)]
Revert "Do not do sign extension in techmap; let packer do it"
This reverts commit
595a8f032f1e9db385959f92a4a414a40de291fd.
Eddie Hung [Thu, 1 Aug 2019 19:02:16 +0000 (12:02 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Thu, 1 Aug 2019 17:01:43 +0000 (10:01 -0700)]
Fix B_WIDTH > DSP_B_MAXWIDTH case
Eddie Hung [Thu, 1 Aug 2019 17:00:49 +0000 (10:00 -0700)]
CO is sign extension only if signed multiplier
Eddie Hung [Thu, 1 Aug 2019 17:00:01 +0000 (10:00 -0700)]
Fix typo
Eddie Hung [Thu, 1 Aug 2019 16:38:55 +0000 (09:38 -0700)]
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
Miodrag Milanovic [Wed, 31 Jul 2019 16:02:27 +0000 (18:02 +0200)]
Fix linking issue for new mxe and pthread
Miodrag Milanovic [Wed, 31 Jul 2019 15:31:07 +0000 (17:31 +0200)]
Fix yosys linking for mxe
Miodrag Milanovic [Wed, 31 Jul 2019 15:30:48 +0000 (17:30 +0200)]
New mxe hacks needed to support
2ca237e
Miodrag Milanovic [Wed, 31 Jul 2019 09:49:48 +0000 (11:49 +0200)]
Fix formatting for msys2 mingw build using GetSize
Jean-François Nguyen [Wed, 31 Jul 2019 12:26:09 +0000 (14:26 +0200)]
proc_prune: Promote partially redundant assignments.
Clifford Wolf [Thu, 1 Aug 2019 10:48:22 +0000 (12:48 +0200)]
Update JSON front-end to process new attr/param encoding
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 1 Aug 2019 10:34:52 +0000 (12:34 +0200)]
Implement improved JSON attr/param encoding
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 31 Jul 2019 23:04:19 +0000 (16:04 -0700)]
Do not compute sign bit if result is zero
Eddie Hung [Wed, 31 Jul 2019 22:45:41 +0000 (15:45 -0700)]
For signed multipliers, compute sign bit separately...
Eddie Hung [Wed, 31 Jul 2019 22:45:15 +0000 (15:45 -0700)]
Restore old CO behaviour
Eddie Hung [Wed, 31 Jul 2019 19:18:03 +0000 (12:18 -0700)]
Helper: SigSpec::operator[] to accept negative indices
Jim Lawson [Wed, 31 Jul 2019 16:27:38 +0000 (09:27 -0700)]
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
Clifford Wolf [Wed, 31 Jul 2019 11:30:52 +0000 (13:30 +0200)]
Merge pull request #1233 from YosysHQ/clifford/defer
Call "read_verilog" with -defer from "read"
Miodrag Milanovic [Wed, 31 Jul 2019 07:10:24 +0000 (09:10 +0200)]
Visual Studio build fix
Jim Lawson [Tue, 30 Jul 2019 23:04:27 +0000 (16:04 -0700)]
Merge remote-tracking branch 'upstream/master'
Eddie Hung [Mon, 29 Jul 2019 23:05:44 +0000 (16:05 -0700)]
RST -> RSTBRST for RAMB8BWER
Eddie Hung [Mon, 29 Jul 2019 16:16:09 +0000 (09:16 -0700)]
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
verilog_lexer: Increase YY_BUF_SIZE to 65536