glsl: Use find_msb_uint to implement ir_unop_find_lsb

(X & -X) calculates a value with only the least significant bit of X
set.  Since there is only one bit set, the LSB is the MSB.

v2: Remove extra int() cast.  Suggested by Matt.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Extract ir_unop_find_msb implementation to a separate function

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Extract ir_unop_bitfield_reverse implementation to a separate function

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Use _mesa_bitcount to implement constant ir_unop_bit_count

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Delete spurious comment about mod not taking integer operands

This hasn't been true since we added support for GLSL 1.30.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Delete spurious comment about updating ir_expression::get_num_operands

This hasn't been necessary since 007f48815.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Do not generate comments or extra whitespace in expression files

The comments and whitespace can live in the Python code.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>

glsl: Just access the ir_expression_operation strings table directly

The operator_string functions gave us some protection against a
malformed table.  Now that the table is generated from the same data
that generates the enum, this is not a concern.  Just cut out the middle
man.

   text    data     bss     dec     hex filename
7531892  273992   28584 7834468  778b64 i965_dri-64bit-before.so
7531828  273992   28584 7834404  778b24 i965_dri-64bit-after.so

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Generate ir_expression_operation_strings.h from Python

'diff -ud' is clean.

v2: Massive rebase.

v3: With much help from José Fonseca, fix the SCons build.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>

glsl: Pull operator_strs out to its own file

No change except to the copyright symbol.  The next patch will generate
this file with Python, and Unicode + Python = pure rage.

v2: Massive rebase.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Generate the ir_last_* values

This ensures that they remain correct if the list is rearranged or new
opcodes are added.  I checked a diff of before and after to ensure that
each ir_last_ had the same value.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>

glsl: Generate ir_expression_operation.h from Python

There are differences in where end-of-line comments are placed, but
'diff -wud' is clean.

v2: Massive rebase.

v3: With much help from José Fonseca, fix SCons build.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>

anv: Rework pipeline caching

The original pipeline cache the Kristian wrote was based on a now-false
premise that the shaders can be stored in the pipeline cache.  The Vulkan
1.0 spec explicitly states that the pipeline cache object is transiant and
you are allowed to delete it after using it to create a pipeline with no
ill effects.  As nice as Kristian's design was, it doesn't jive with the
expectation provided by the Vulkan spec.

The new pipeline cache uses reference-counted anv_shader_bin objects that
are backed by a large state pool.  The cache itself is just a hash table
mapping keys hashes to anv_shader_bin objects.  This has the added
advantage of removing one more hand-rolled hash table from mesa.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97476
Acked-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>

anv: Add a struct for storing a compiled shader

This new anv_shader_bin struct stores the compiled kernel (as an anv_state)
as well as all of the metadata that is generated at shader compile time.
The struct is very similar to the old cache_entry struct except that it
is reference counted and stores the actual pipeline_bind_map.  Similarly to
cache_entry, much of the actual data is floating-size and stored after the
main struct.  Unlike cache_entry, which was storred in GPU-accessable
memory, the storage for anv_shader_bin kernels comes from a state pool.
The struct itself is reference-counted so that it can be used by multiple
pipelines at a time without fear of allocation issues.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Acked-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>

anv: Add pipeline_has_stage guards a few places

All of these worked before because they were depending on prog_data to be
null.  Soon, we won't be able to depend on a nice prog_data pointer and
it's nice to be more explicit anyway.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv: Remove unused fields from anv_pipeline_bind_map

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv/pipeline: Properly handle OOM during shader compilation

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv/allocator: Correctly set the number of buckets

The range from ANV_MIN_STATE_SIZE_LOG2 to ANV_MAX_STATE_SIZE_LOG2 should
be inclusive and we have asserts that ensure that you never try to allocate
a state larger than (1 << ANV_MAX_STATE_SIZE_LOG2).  However, without
adding 1 to the difference, we allocate 1 too few bucckts and so, even
though we have an assert, anything landing in the last bucket will fail to
allocate properly..

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv/pipeline: Fix bind maps for fragment output arrays

Found by inspection.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

anv/descriptor_set: memset anv_descriptor_set_layout

We hash this data structure so we can't afford to have uninitialized data
even if it is just structure padding.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

docs/helpwanted: fix GL3.txt/features.txt link

Fixes: f926cf5bd0ade3273b32 ("docs: Rename GL3.txt to features.txt")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
CC: Andreas Boll <andreas.boll.dev@gmail.com>

anv/wayland: fix assert typo

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

anv/meta: fix unreachable() typo

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

st/nine: fix unreachable() typo

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

glsl: fix unreachable() typo

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

get_reviewer.pl: fix mesa check

This script was broken for the last few days and I couldn't figure out why.
Turns out it was checking for the existence of a file that got renamed,
so rename it in here too.

Fixes: f926cf5bd0ade3273b32 ("docs: Rename GL3.txt to features.txt")
CC: Ian Romanick <ian.d.romanick@intel.com>
CC: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Rob Clark <robdclark@gmail.com>

glsl: Initialize outputs[] array in lower_blend_equation_advanced.

Caught by Coverity.  Likely fixes real issues if an output component
is not present.

CID: 1372278
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nvc0: fix indentation in nvc0_screen_init()

Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: check return value of nvc0_screen_resize_tls_area()

While we are at it, make it static and change the return values
policy to be consistent.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: make use of FAIL_SCREEN_INIT in nvc0_screen_create()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: always emit the NDV bit for OP_QUADOP

This silences a divergent error found with F1 2015.

Basically, the NDV bit has to be set when a FSWZ instruction is
inside divergent code, but it's not needed otherwise. The correct
fix should be to set it only in divergent code situations.

GM107 emitter already sets that bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

intel/blorp: Inline get_vs_entry_size into emit_urb_config

Topi asked to have the prefix removed because there's nothing gen7 about
it.  However, now that everything is in a single file, there is no good
reason to have it split out into a helper function anyway.  Let's just put
the contents in emit_urb_config and call it a day.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

swr: [rasterizer] add archrast instrumentation

Statistics measurement system

i915: Check return value of screen->image.loader->getBuffers

Ported from the i965 commit e7ab358e8186dd8651cf920d4db1500c60ccd2fc.

Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Cc: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

egl/android: remove config post-processing

No longer needed as of last commit, since we no longer add OPENGL to the
ClientAPIs thus, RenderType and Conformant don't have the desktop GL
bit set.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>

egl/dri2: check if the EGL API is valid before adding it to ClientAPIs

In the rather unlikely case that the API is considered invalid, don't
add it to the (supported) ClientAPIs bitmask.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
---
Strictly speaking we only need this in the Android case for OpenGL.
Adding it everywhere doesn't hurt us since the compiler will const
propagate and optimise/remove these.

egl/android: annotate static const data as such

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>

egl: treat EGL_OPENGL_API as invalid on Android

At the moment one can use OpenGL in eglBindAPI() only to clear the
EGL_OPENGL_BIT from RenderableType and Conformant for _each_ config.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>

nouveau: make color/depth bpp match for pre-nv10 chips

This avoids generating fbconfigs whose winsys framebuffers will be
incomplete (see nouveau_check_framebuffer_complete).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nouveau: always enable at least one RC

Experimentally, this is required for glxgears and others to display the
proper colors. This is also what the code used to do before the
referenced commit.

Fixes: c703658b396 (mesa: Drop _EnabledUnits.)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nouveau: allow NV3x's to be used with nouveau_vieux

NV34 and possibly other NV3x hardware has the capability of exposing the
NV25 graph class. This allows forcing nouveau_vieux to be used instead
of the gallium driver, primarily for testing purposes. (Among other
things, NV2x only ever came as AGP or inside an Xbox, never PCI/PCIe).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: undo overzealous enum usage

Commit 7413625ad3 flipped a few functions too many to use
pipe_shader_type. These functions actually take an integer that does not
correspond 1:1 with the enum.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

svga: fix a texture readback bug

Backing views/surfaces are used to handle the case when a resource is
bound both as a render target and as a sampler source (such as when
doing auto mipmap generation).

This patch fixes a bug where mapping a resource (to do a glReadPixels)
was reading the stale data in the original surface rather than the
backing surface which was rendered to.

We need to propagate the backing resource (which we rendered to) back
to the original resource before we read from it.  The problem was the
svga_propagate_rendertargets() function was examining the wrong surface
views.

This fixes the "poc9" test described in VMware bug 1686661.
Also tested with Piglit, Cinebench, Lightsmark, etc.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: move surface propagation code into new function

Put new svga_propagate_rendertargets() function where all the other
surface propagation code lives.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

mesa: fix format conversion bug in get_tex_rgba_uncompressed()

We need to set the need_convert flag with each loop iteration, not
just when the rgba pointer is null.

Bug reported by Markus Müller <mueller@imfusion.de> on mesa-users list.
Fixes new piglit arb_texture_float-get-tex3d test.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

radeonsi: add support for cull distances. (v1.1)

This should be all that is required for cull distances to work
on radeonsi.

v1.1: whitespace cleanup, add docs fix clipdist_mask usage.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

spirv: replace assert with unreachable

Fixes uninitialised warning for coord_components.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

isl/state: Add some asserts about format capabilities

This keeps invalid surface states from leaking through and potentially
hanging the GPU.  We shouldn't actually be hitting this on a regular basis,
but a helpful assert is better than a hang.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

intel/blorp: Add a format parameter to blorp_fast_clear

This allows us to use the actual render format as opposed to the texture
format.  I don't know that the hardware actually cares in the case of fast
clears, but it certainly seems more correct.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move blorp into src/intel/blorp

At this point, blorp is completely driver agnostic and can be safely moved
into its own folder.  Soon, we hope to start using it for doing blits in
the Vulkan driver.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Remove the remaining brw prefixes from the blorp.h API

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Use isl_format_get_depth_format for setting depth formats

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move the type_size function declartaions to brw_nir.h

Signed-of-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Move get_fast_clear_rect to blorp_clear.c

This has been the only caller since we deleted the meta fast clear code.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Roll brw_get_ccs_resolve_rect into blorp_ccs_resolve

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Get rid of most brw and mesa includes

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move the hiz_op enum to blorp

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Add a fast_clear_op enum

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Make blorp_addres::buffer a void*

The Vulkan driver doesn't use libdrm so we don't want to bake that in.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Get rid of brw_context

This commit switches all of blorp from taking a brw_context to taking a
blorp_context and, where useful, a void *batch.  In the GL driver, we only
have one active batch at a time so the brw_context *is* the batch but in
Vulkan, batch will point to the anv_cmd_buffer in which we are building
instructions.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Take a blorp_context in compile_nir_shader

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/meta_util: Take an isl_device in get_fast_clear_rect

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Add an "exec" function pointer to blorp_context

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Remove some i965-isms from genX_blorp_exec.h

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Move the guts of brw_blorp_exec into genX_blorp_exec.c

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Pull the guts of blorp_exec into a driver-agnostic header

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp/exec: Refactor to use a new blorp_batch struct

This gets rid of brw_context throughout the core of the state setup code.
Instead, it is replaced with blorp_batch which contains a pointer to the
blorp_context and a void* that the driver can use for its own blorp data.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Add a helper for allocating binding tables and surface states

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Use BT_INDEX enums for setting up the binding table

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Shorten binding table index enum names

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp/genX: Add a blorp_surface_reloc helper

Previously, we passed the buffer address (as per the latest offset from the
kernel) to ISL to use when it filled out the surface state.  We then called
drm_intel_bo_emit_reloc() to add the relocation to the list.  The newly
added blorp_surface_reloc helper adds the relocation to the list and then
writes the buffer address directly into the surface state.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Use blorp_address in brw_blorp_surface instead of bo+offset

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Pull emit_surface_state into genX_blorp_exec.c

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Add driver mocs settings to the context

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp/genX: Move emit_urb_config into another helper

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Use gen6_upload_urb

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/gen6: Refactor gen6_upload_urb

This splits it into two functions very similar to gen7_upload_urb.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp/genX: Pull emit_3dstate_multisample into a helper

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp/genX: Add helpers for allocating various bits of state

This pulls most of the brw-specific bits into helpers with generic names.
Later, those will become the driver hooks for generic code.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Expose the shader cache through function pointers

This sanitizes blorp's access to the i965 driver's shader cache by patching
it through the blorp_context.  When we start using blorp in Vulkan, we will
simply have to implement such a caching interface in the Vulkan driver.

Note: In my first attempt at this, I simplified it down to a single
upload_shader entrypoint and implemented the caching inside of blorp.  This
doesn't work, however, because the i965 driver will, on occation, dump its
entire cache and start over.  When this happens, blorp needs to be able to
recompile its shaders and re-upload them.  It's easiest to just expose the
caching interface.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>

i965/blorp: Add a blorp_context struct and init/finish funcs

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

android: intel: Flatten the makefile structure

Android porting of commit bebc1a1 "intel: Flatten the makefile structure"

Automake approach was followed, by moving makefiles a level up,
naming them Android.genxml.mk and Android.isl.mk,
performing the necessary adjustments to the paths,
adding src/intel/Android.mk and fixing mesa top level makefile.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

clover: Use device cap to query pointer size instead of hardcoded 32bits

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97513
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

gallium: add cap to export device pointer size

v2: document the new cap
v3: fix 80 char limit in screen.rst

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

svga: s/unsigned/enum pipe_shader_type/

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

i965/hsw: Enable ARB_ES3_1_compatibility extension

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

r600g: Clean up defined magic numbers for TGSI opcodes

Small code clean up that removes magic numbers where a TGSI
opcode has been defined.

No functional change expected as each opcode is unsupported on
the respective hardware.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: James Harvey <lothmordor@gmail.com>

r600g: Avoid duplicated initialization of TGSI_OPCODE_DFMA

As reported by Clang, TGSI_OPCODE_DFMA (defined magic number 118) is
currently initialized twice for Cayman and Evergreen.

When Jan Vesely added double precision FMA opcode it did make sense
to locate it immediately after TGSI_OPCODE_DMAD, although this is
out of order.

This change cleans up the prior magic number definition and ensures
any later reordering of this struct will not create problems.

Prior change was:

  commit 015e2e0fce3eea7884f8df275c2fadc35143a324
  Author: Jan Vesely <jan.vesely@rutgers.edu>
  Date:   Sat Jul 2 16:14:54 2016 -0400

      r600g: Add double precision FMA ops

      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96782
Fixes: 54c4d525da7c7fc1e103d7a3e6db015abb132d5d ("r600g: Enable FMA on chips that support it")
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Tested-by: James Harvey <lothmordor@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: James Harvey <lothmordor@gmail.com>

i915g: Fix typo in i915_translate_instruction()

Noticed this error in a debug message whilst reviewing
https://bugs.freedesktop.org/show_bug.cgi?id=97477

This patch doesn't go towards fixing that bug, but at
least may clarify future debug output.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: Handle discards while in control flow.

I missed this while adding loop support because the discard test inside a
loop was crashing before, anyway.  Fixes piglit glsl-fs-discard-04.

vc4: Mark when we add discards while lowering blend state.

nir: Update shader info when adding discards

vc4 is about to start using the shader info field to set up discard
handling.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

swr: [rasterier core] fix GetRasterizerFunc selection

Only rasterize scissor edges if one or more scissor/viewport
rects are not hottile aligned.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] whitespace cleanup

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer jitter] reimplement SCATTERPS

Implement SCATTERPS as a dynamic loop based on mask set bits
instead of a static compile time loop.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] upper left rule for scissors

Fixes upper left rule for scissors and viewport/scissor macrotile alignment.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer scripts] undef DEFINE_KNOB after usage

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] minor cleanup to thread initialization

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] remove KNOB_MAX_THREADS

Use dynamic memory allocation for per-thread data

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] track guardbands per viewport rect

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>