Clifford Wolf [Thu, 17 Jul 2014 11:13:21 +0000 (13:13 +0200)]
Added support for constant bit- or part-select for memory writes
Clifford Wolf [Thu, 17 Jul 2014 10:12:04 +0000 (12:12 +0200)]
Improved opt_reduce handling of mem wr_en mux bits
Clifford Wolf [Thu, 17 Jul 2014 10:10:57 +0000 (12:10 +0200)]
Fixed RTLIL::SigSpec::append_bit() for appending constants
Clifford Wolf [Thu, 17 Jul 2014 06:59:07 +0000 (08:59 +0200)]
Added support for "blackbox" attribute to iopadmap
Clifford Wolf [Thu, 17 Jul 2014 06:58:51 +0000 (08:58 +0200)]
Added support for "blackbox" attribute to flatten/techmap
Clifford Wolf [Wed, 16 Jul 2014 16:12:46 +0000 (18:12 +0200)]
Added "inout" ports support to read_liberty
Clifford Wolf [Wed, 16 Jul 2014 16:12:16 +0000 (18:12 +0200)]
Set blackbox attribute in "read_liberty -lib"
Clifford Wolf [Wed, 16 Jul 2014 16:02:28 +0000 (18:02 +0200)]
Fixed spelling of "direction" in read_liberty messages
Clifford Wolf [Wed, 16 Jul 2014 12:15:33 +0000 (14:15 +0200)]
Merged new $mem/$memwr WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 11:46:27 +0000 (13:46 +0200)]
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 11:37:41 +0000 (13:37 +0200)]
improved opt_reduce for $mem/$memwr WR_EN multiplexers
Clifford Wolf [Wed, 16 Jul 2014 10:23:47 +0000 (12:23 +0200)]
changes in verilog frontend for new $mem/$memwr WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 10:13:13 +0000 (12:13 +0200)]
Changes to "memory" pass for new $memwr/$mem WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 09:46:40 +0000 (11:46 +0200)]
Updated simlib to new $mem/$memwr interface
Clifford Wolf [Wed, 16 Jul 2014 09:38:02 +0000 (11:38 +0200)]
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf [Wed, 16 Jul 2014 08:03:07 +0000 (10:03 +0200)]
Added note to "make test": use git checkout of iverilog
Clifford Wolf [Sat, 12 Jul 2014 08:02:39 +0000 (10:02 +0200)]
Added passing of various options to vhdl2verilog
Clifford Wolf [Fri, 11 Jul 2014 11:10:51 +0000 (13:10 +0200)]
Use "verilog -sv" to parse .sv files
Clifford Wolf [Fri, 11 Jul 2014 11:05:53 +0000 (13:05 +0200)]
Fixed processing of initial values for block-local variables
Clifford Wolf [Sat, 5 Jul 2014 09:17:40 +0000 (11:17 +0200)]
now ignore init attributes on non-register wires in sat command
Clifford Wolf [Wed, 2 Jul 2014 04:27:04 +0000 (06:27 +0200)]
fixed parsing of constant with comment between size and value
Clifford Wolf [Wed, 2 Jul 2014 04:16:31 +0000 (06:16 +0200)]
small changes in presentation
Clifford Wolf [Sun, 29 Jun 2014 07:27:03 +0000 (09:27 +0200)]
Tiny fix in presentation
Clifford Wolf [Sun, 29 Jun 2014 07:14:49 +0000 (09:14 +0200)]
Progress in presentation
Clifford Wolf [Sat, 28 Jun 2014 10:11:42 +0000 (12:11 +0200)]
Added links to some liberty files to README
Clifford Wolf [Thu, 26 Jun 2014 20:05:39 +0000 (22:05 +0200)]
Progress in presentation
Clifford Wolf [Wed, 25 Jun 2014 08:05:36 +0000 (10:05 +0200)]
Fixed handling of mixed real/int ternary expressions
Clifford Wolf [Tue, 24 Jun 2014 13:08:48 +0000 (15:08 +0200)]
More found_real-related fixes to AstNode::detectSignWidthWorker
Clifford Wolf [Sun, 22 Jun 2014 10:50:29 +0000 (12:50 +0200)]
Progress in presentation
Clifford Wolf [Sat, 21 Jun 2014 19:43:04 +0000 (21:43 +0200)]
Little steps in realmath test bench
Clifford Wolf [Sat, 21 Jun 2014 19:41:13 +0000 (21:41 +0200)]
fixed signdness detection for expressions with reals
Clifford Wolf [Sat, 21 Jun 2014 19:13:18 +0000 (21:13 +0200)]
fixed typo
Clifford Wolf [Sat, 21 Jun 2014 14:33:33 +0000 (16:33 +0200)]
Progress in presentation
Clifford Wolf [Thu, 19 Jun 2014 10:29:29 +0000 (12:29 +0200)]
Do not create $dffsr cells with no-op resets in proc_dff
Clifford Wolf [Tue, 17 Jun 2014 19:49:59 +0000 (21:49 +0200)]
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf [Tue, 17 Jun 2014 19:39:25 +0000 (21:39 +0200)]
Added AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf [Tue, 17 Jun 2014 10:47:51 +0000 (12:47 +0200)]
Improved handling of relational op of real values
Clifford Wolf [Mon, 16 Jun 2014 13:21:08 +0000 (15:21 +0200)]
Little steps in realmath test bench
Clifford Wolf [Mon, 16 Jun 2014 13:12:24 +0000 (15:12 +0200)]
Improved ternary support for real values
Clifford Wolf [Mon, 16 Jun 2014 13:05:37 +0000 (15:05 +0200)]
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
Clifford Wolf [Mon, 16 Jun 2014 13:02:40 +0000 (15:02 +0200)]
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
Clifford Wolf [Mon, 16 Jun 2014 13:00:57 +0000 (15:00 +0200)]
Added found_real feature to AstNode::detectSignWidth
Clifford Wolf [Sun, 15 Jun 2014 09:51:51 +0000 (11:51 +0200)]
Added more calls to "hierarchy" to README file
Clifford Wolf [Sun, 15 Jun 2014 07:39:22 +0000 (09:39 +0200)]
Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)
Clifford Wolf [Sun, 15 Jun 2014 07:31:03 +0000 (09:31 +0200)]
Added tests/realmath to "make test"
Clifford Wolf [Sun, 15 Jun 2014 07:27:09 +0000 (09:27 +0200)]
Improved AstNode::realAsConst for large numbers
Clifford Wolf [Sun, 15 Jun 2014 06:48:41 +0000 (08:48 +0200)]
Improved realmath test bench
Clifford Wolf [Sun, 15 Jun 2014 06:48:17 +0000 (08:48 +0200)]
Improved parsing of large integer constants
Clifford Wolf [Sun, 15 Jun 2014 06:38:31 +0000 (08:38 +0200)]
Improved AstNode::asReal for large integers
Clifford Wolf [Sat, 14 Jun 2014 18:38:40 +0000 (20:38 +0200)]
improved realmath test bench
Clifford Wolf [Sat, 14 Jun 2014 18:38:05 +0000 (20:38 +0200)]
improved (fixed) conversion of real values to bit vectors
Clifford Wolf [Sat, 14 Jun 2014 17:56:22 +0000 (19:56 +0200)]
progress in realmath test bench
Clifford Wolf [Sat, 14 Jun 2014 17:33:58 +0000 (19:33 +0200)]
Fixed relational operators for const real expressions
Clifford Wolf [Sat, 14 Jun 2014 17:24:01 +0000 (19:24 +0200)]
added first draft of real math testcase generator
Clifford Wolf [Sat, 14 Jun 2014 14:42:30 +0000 (16:42 +0200)]
Progress in presentation
Clifford Wolf [Sat, 14 Jun 2014 14:19:32 +0000 (16:19 +0200)]
Added %D and %c select commands
Clifford Wolf [Sat, 14 Jun 2014 11:36:23 +0000 (13:36 +0200)]
Added support for math functions
Clifford Wolf [Sat, 14 Jun 2014 10:01:17 +0000 (12:01 +0200)]
Added realexpr.v test case
Clifford Wolf [Sat, 14 Jun 2014 10:00:47 +0000 (12:00 +0200)]
Added handling of real-valued parameters/localparams
Clifford Wolf [Sat, 14 Jun 2014 09:27:05 +0000 (11:27 +0200)]
Implemented more real arithmetic
Clifford Wolf [Sat, 14 Jun 2014 06:51:22 +0000 (08:51 +0200)]
Implemented basic real arithmetic
Clifford Wolf [Sat, 14 Jun 2014 05:44:19 +0000 (07:44 +0200)]
Added real->int convertion in ast genrtlil
Clifford Wolf [Fri, 13 Jun 2014 09:29:23 +0000 (11:29 +0200)]
Added Verilog lexer and parser support for real values
Clifford Wolf [Thu, 12 Jun 2014 09:54:20 +0000 (11:54 +0200)]
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
Clifford Wolf [Sun, 8 Jun 2014 13:31:27 +0000 (15:31 +0200)]
Now we are in Yoys 0.3.0+ development
Clifford Wolf [Sun, 8 Jun 2014 13:28:36 +0000 (15:28 +0200)]
Tagging Yosys 0.3.0
Clifford Wolf [Sun, 8 Jun 2014 08:12:39 +0000 (10:12 +0200)]
Updated ABC to
7600ffb9340c
Clifford Wolf [Sat, 7 Jun 2014 10:18:00 +0000 (12:18 +0200)]
added tests for new verilog features
Clifford Wolf [Sat, 7 Jun 2014 10:17:06 +0000 (12:17 +0200)]
fixed cell array handling of positional arguments
Clifford Wolf [Sat, 7 Jun 2014 09:48:50 +0000 (11:48 +0200)]
Add support for cell arrays
Clifford Wolf [Sat, 7 Jun 2014 08:47:53 +0000 (10:47 +0200)]
Added support for repeat stmt in const functions
Clifford Wolf [Fri, 6 Jun 2014 22:02:05 +0000 (00:02 +0200)]
further improved const function support
Clifford Wolf [Fri, 6 Jun 2014 21:05:01 +0000 (23:05 +0200)]
made the generate..endgenrate keywords optional
Clifford Wolf [Fri, 6 Jun 2014 20:55:02 +0000 (22:55 +0200)]
improved const function support
Clifford Wolf [Fri, 6 Jun 2014 19:29:23 +0000 (21:29 +0200)]
fix functions with no block (but single statement, loop, etc.)
Clifford Wolf [Fri, 6 Jun 2014 15:47:20 +0000 (17:47 +0200)]
Added tests/simple/repwhile.v
Clifford Wolf [Fri, 6 Jun 2014 15:40:45 +0000 (17:40 +0200)]
improved ast simplify of const functions
Clifford Wolf [Fri, 6 Jun 2014 15:40:04 +0000 (17:40 +0200)]
added while and repeat support to verilog parser
Clifford Wolf [Wed, 4 Jun 2014 07:10:50 +0000 (09:10 +0200)]
Improved error message for options after front-end filename arguments
Clifford Wolf [Tue, 3 Jun 2014 07:23:31 +0000 (09:23 +0200)]
added tee cmd
Clifford Wolf [Sun, 1 Jun 2014 09:32:27 +0000 (11:32 +0200)]
Fixed log messages in memory_dff
Clifford Wolf [Thu, 29 May 2014 09:03:15 +0000 (11:03 +0200)]
Updated ABC to rev
fa4404b395f0
Clifford Wolf [Thu, 29 May 2014 08:26:55 +0000 (10:26 +0200)]
Merge pull request #36 from hansiglaser/master
Various changes merged
Johann Glaser [Wed, 28 May 2014 16:05:38 +0000 (18:05 +0200)]
added log_header to miter and expose pass, show cell type for exposed ports
Johann Glaser [Wed, 28 May 2014 14:50:13 +0000 (16:50 +0200)]
new flags -ignore_miss_func and -ignore_miss_dir for read_liberty
Johann Glaser [Mon, 26 May 2014 15:13:41 +0000 (17:13 +0200)]
be more verbose when techmap yielded processes
Clifford Wolf [Mon, 12 May 2014 10:45:47 +0000 (12:45 +0200)]
Fixed bug in opt_reduce (see vloghammer issue_044)
Clifford Wolf [Sat, 10 May 2014 14:22:56 +0000 (16:22 +0200)]
fixed syntax error in dot file created by "show" command
Clifford Wolf [Fri, 9 May 2014 16:24:13 +0000 (18:24 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Fri, 9 May 2014 16:23:21 +0000 (18:23 +0200)]
Updated ABC to
67c84cdd49e4
Clifford Wolf [Tue, 6 May 2014 12:42:04 +0000 (14:42 +0200)]
Progress in presentation
Clifford Wolf [Tue, 6 May 2014 11:48:25 +0000 (13:48 +0200)]
Improved ezsat stand-alone tests
Clifford Wolf [Sat, 3 May 2014 10:55:56 +0000 (12:55 +0200)]
workaround for OpenBSD 'stdout' implementation
Clifford Wolf [Fri, 2 May 2014 11:22:26 +0000 (13:22 +0200)]
workaround for OpenBSD 'stdin' implementation
Clifford Wolf [Fri, 2 May 2014 11:18:43 +0000 (13:18 +0200)]
Merge pull request #35 from bentley/dox
Typos and grammar fixes through chapter 4.
Anthony J. Bentley [Fri, 2 May 2014 09:08:40 +0000 (03:08 -0600)]
Typos and grammar fixes through chapter 4.
Clifford Wolf [Sun, 20 Apr 2014 12:28:23 +0000 (14:28 +0200)]
Fixed clang -Wdeprecated-register warnings
Clifford Wolf [Sun, 20 Apr 2014 12:22:11 +0000 (14:22 +0200)]
Replaced depricated %name-prefix= bison directive
Clifford Wolf [Sun, 20 Apr 2014 12:17:40 +0000 (14:17 +0200)]
minisat compile fix
Clifford Wolf [Fri, 18 Apr 2014 08:19:46 +0000 (10:19 +0200)]
Updated README