gem5.git
18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Wed, 12 Jul 2006 21:21:25 +0000 (17:21 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/test.py:
    Hand merge.

--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2

18 years agoBe sure to include the EIO sources as well so we can run regression tests.
Kevin Lim [Wed, 12 Jul 2006 21:20:01 +0000 (17:20 -0400)]
Be sure to include the EIO sources as well so we can run regression tests.

src/SConscript:
    It's no longer "ALPHA_ISA".  I don't think we meant to leave out the EIO sources.

--HG--
extra : convert_revision : 1ca63ffb571d9021f1ced0bf0df1816b0b798edc

18 years agoSerialization changes to make O3CPU consistent with the other models.
Kevin Lim [Wed, 12 Jul 2006 21:18:34 +0000 (17:18 -0400)]
Serialization changes to make O3CPU consistent with the other models.

src/cpu/o3/commit_impl.hh:
    Always set instruction.  This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
    Change serialization so it matches other CPU's output.  Also fix up some indexing.

--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534

18 years agoInitial try of consolidating configuration files so they can be shared more easily...
Kevin Lim [Wed, 12 Jul 2006 21:17:17 +0000 (17:17 -0400)]
Initial try of consolidating configuration files so they can be shared more easily, especially across regression tests and simple examples.

configs/test/fs.py:
    Pull a lot of the default options out of the config file now that they are in the Python objects themselves.  Also merge this file with the single_fs.py, allowing one file to be used for both.  Previously they differed only by the system they instantiated.
configs/test/test.py:
    Initial stab at consolidating configuration files so they aren't redundant between the regression tests and the simple examples.

--HG--
extra : convert_revision : e8ae3de5a6d8864831f21089d4fdb8ec690e4731

18 years agoPush more default options to the Python object level as they are rarely changed....
Kevin Lim [Wed, 12 Jul 2006 21:16:00 +0000 (17:16 -0400)]
Push more default options to the Python object level as they are rarely changed.  These are the changes that Steve was working on.

src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
    Push more default options to the Python object level as they are rarely changed.

--HG--
extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb

18 years agoUpdates for serialization. As long as the tickEvent doesn't need to be serialized...
Kevin Lim [Wed, 12 Jul 2006 21:11:57 +0000 (17:11 -0400)]
Updates for serialization.  As long as the tickEvent doesn't need to be serialized (I don't believe it does because we drain all CPUs prior to checkpointing), it should be feasible to start up from other CPU's checkpoints.

src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
    Updates for serialization.

--HG--
extra : convert_revision : 0f150de75d4bc833e4c9b83568e7fd22688d5727

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Wed, 12 Jul 2006 19:25:34 +0000 (15:25 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

src/cpu/o3/fetch_impl.hh:
    Hand merge.

--HG--
extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74

18 years agoTrack the PC of the cache data stored in fetch so it doesn't access memory multiple...
Kevin Lim [Wed, 12 Jul 2006 19:24:27 +0000 (15:24 -0400)]
Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch.

--HG--
extra : convert_revision : 00b160b255e998cf99286bcc21894110c7642624

18 years agoAdd --pdb
Nathan Binkert [Wed, 12 Jul 2006 19:21:23 +0000 (15:21 -0400)]
Add --pdb

src/python/m5/main.py:
    Add a command line option to invoke pdb on your script

--HG--
extra : convert_revision : ef5a2860bd3f6e479fa80eccaae0cb5541a20b50

18 years agoMerge m5.eecs.umich.edu:/bk/newmem
Nathan Binkert [Wed, 12 Jul 2006 19:19:08 +0000 (15:19 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/research/m5/current

--HG--
extra : convert_revision : 842a23da034c40c75364b76ca75de076da776ac6

18 years agoFix __file__ for scripts
Nathan Binkert [Wed, 12 Jul 2006 19:18:49 +0000 (15:18 -0400)]
Fix __file__ for scripts

src/python/m5/main.py:
    set __file__ to the script, not the m5 binary.

--HG--
extra : convert_revision : a0bbd059d2fd321ae8ff68225abc8a7bb5c410ed

18 years agoAdd a cache version of FS (should really make this an option in original)
Ron Dreslinski [Tue, 11 Jul 2006 20:03:42 +0000 (16:03 -0400)]
Add a cache version of FS (should really make this an option in original)

Now to work on caches in FS, first steps:
1) LL/SC support (Top Level Cache Hooks)
2) Snooping in the bus (CSHR's for DMA Invalidates)

--HG--
extra : convert_revision : b4e7984712f7dcd42649070c5ca538c87461e179

18 years agoMerge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski [Tue, 11 Jul 2006 19:42:49 +0000 (15:42 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 3be1aa4892aa8bbd458bdc5538bbcbd6c1ebe299

18 years agoFix ordering issue with squashed Icache Fetches and Static data in packet.
Ron Dreslinski [Tue, 11 Jul 2006 19:42:31 +0000 (15:42 -0400)]
Fix ordering issue with squashed Icache Fetches and Static data in packet.

Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).

src/cpu/o3/fetch_impl.hh:
    Fix ordering issue with squashed Icache Fetches and Static data in packet.

--HG--
extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Tue, 11 Jul 2006 17:43:30 +0000 (13:43 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : c565fd7cebaa4058ba510b3db50a9c76bf301228

18 years agoFix option parsing.
Nathan Binkert [Tue, 11 Jul 2006 15:28:59 +0000 (11:28 -0400)]
Fix option parsing.

src/python/m5/main.py:
    Don't allow interspersed arguments, it messes things up

--HG--
extra : convert_revision : 8f1bcf4391f570741d92bf5420879862a48f6016

18 years agoMigrate most of main() and and all option parsing to python
Nathan Binkert [Tue, 11 Jul 2006 03:00:13 +0000 (23:00 -0400)]
Migrate most of main() and and all option parsing to python

configs/test/fs.py:
configs/test/test.py:
    update for the new way that m5 deals with options
src/python/SConscript:
    Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the
    python stuff.
src/python/m5/__init__.py:
    redo the way options work.
    Move them all to main.py
src/sim/main.cc:
    Migrate more functionality for main() into python.
    Namely option parsing
src/python/m5/attrdict.py:
    A dictionary object that overrides attribute access to
    do item access.
src/python/m5/main.py:
    The new location for M5's option parsing, and the main()
    routine to set up the simulation.

--HG--
extra : convert_revision : c86b87a9f508bde1994088e23fd470c7753ee4c1

18 years agoMerge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski [Mon, 10 Jul 2006 21:19:54 +0000 (17:19 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : c811eb9eacc480b14862f8074af80c56ec1e07f1

18 years agoSome fixes so that MSHR's are matched and we don't issue overlapping requests with...
Ron Dreslinski [Mon, 10 Jul 2006 21:16:15 +0000 (17:16 -0400)]
Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu

src/mem/cache/base_cache.cc:
    If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
    Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
    Actually save the address, otherwise we can't match MSHR's

--HG--
extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8

18 years agoMinor fixes.
Kevin Lim [Mon, 10 Jul 2006 20:31:42 +0000 (16:31 -0400)]
Minor fixes.

src/cpu/checker/thread_context.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
    Change functions to match Korey's changes.
src/cpu/ozone/lw_back_end.hh:
    Fix compile error.

--HG--
extra : convert_revision : fb11ac2d6db3a75c1cdbad2c1c02f921ad7344a6

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Mon, 10 Jul 2006 19:41:35 +0000 (15:41 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0e4c7684879b8552908e0b64a00b4824de807244

18 years agoSome minor cleanups.
Kevin Lim [Mon, 10 Jul 2006 19:41:28 +0000 (15:41 -0400)]
Some minor cleanups.

src/cpu/SConscript:
    Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
    Remove old code.
src/cpu/o3/commit_impl.hh:
    Remove old unused code.

--HG--
extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390

18 years agoAdd parameters for backwards and forwards sizes for time buffers.
Kevin Lim [Mon, 10 Jul 2006 19:40:28 +0000 (15:40 -0400)]
Add parameters for backwards and forwards sizes for time buffers.

src/base/timebuf.hh:
    Add a function to return the size of the time buffer.

--HG--
extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4

18 years agoUpdate config for a system with an L2
Ron Dreslinski [Mon, 10 Jul 2006 16:42:35 +0000 (12:42 -0400)]
Update config for a system with an L2

--HG--
extra : convert_revision : c73a532ad6ad8d5115bda81fa778a4b97fbab713

18 years agoFix offset calculation. Now L2's work with timing&atomic.
Ron Dreslinski [Mon, 10 Jul 2006 16:35:18 +0000 (12:35 -0400)]
Fix offset calculation.  Now L2's work with timing&atomic.

src/mem/packet.hh:
    Offset is based on packet, not request.

--HG--
extra : convert_revision : d85af5838370541328ca35072c612d8198020625

18 years agoUpdate FS configs to use cpu connectors for ports
Ron Dreslinski [Mon, 10 Jul 2006 16:07:21 +0000 (12:07 -0400)]
Update FS configs to use cpu connectors for ports

--HG--
extra : convert_revision : 1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4

18 years agoFix cpu in full system to match SE.
Ron Dreslinski [Mon, 10 Jul 2006 16:03:13 +0000 (12:03 -0400)]
Fix cpu in full system to match SE.

--HG--
extra : convert_revision : 95e422221ff5bab6104925d50a8882d31729b0f5

18 years agoMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Korey Sewell [Fri, 7 Jul 2006 23:02:12 +0000 (19:02 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b

18 years agoSupport for recent port changes.
Kevin Lim [Fri, 7 Jul 2006 22:24:13 +0000 (18:24 -0400)]
Support for recent port changes.

src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
    Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
    Support Ron's recent port changes.  Also support handling faults in SE.

--HG--
extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891

18 years agoSupport Ron's changes for hooking up ports.
Kevin Lim [Fri, 7 Jul 2006 21:33:24 +0000 (17:33 -0400)]
Support Ron's changes for hooking up ports.

src/cpu/checker/cpu.hh:
    Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
    Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
    Add ports to the parameters.

--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918

18 years agoFix for bug when draining and a memory access is outstanding.
Kevin Lim [Fri, 7 Jul 2006 20:48:44 +0000 (16:48 -0400)]
Fix for bug when draining and a memory access is outstanding.

--HG--
extra : convert_revision : 1af782cf023ae74c2a3ff9f7aefcea880bc87936

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Fri, 7 Jul 2006 20:47:28 +0000 (16:47 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : e8933f852352164f4e50444f94cc6ee260e06766

18 years agoTake the name of the checkpoint directory in when calling checkpoint() or restoreChec...
Kevin Lim [Fri, 7 Jul 2006 20:46:08 +0000 (16:46 -0400)]
Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint().

src/sim/main.cc:
src/sim/serialize.cc:
src/sim/serialize.hh:
    Take in the directory name when checkpointing.

--HG--
extra : convert_revision : 040e828622480f1051e2156f4439e24864c38d45

18 years agoMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Korey Sewell [Fri, 7 Jul 2006 20:19:13 +0000 (16:19 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : be8b295ebf54a7c6bf720a20ab6aa9f02aee8060

18 years agoFix address range calculation. Still need bus to handle snoop ranges.
Ron Dreslinski [Fri, 7 Jul 2006 20:02:22 +0000 (16:02 -0400)]
Fix address range calculation.  Still need bus to handle snoop ranges.
On the way towards multi-level caches (L2)

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Fix address range calculation.  Still need bus to handle snoop ranges.

--HG--
extra : convert_revision : 800078d88aab5e563f4a9bb599f91cd44f36e625

18 years agoMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Korey Sewell [Fri, 7 Jul 2006 19:58:22 +0000 (15:58 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : f97469b7d19c82deb3d068f80546d729757c25e3

18 years agoMinor fix for SMT Hello Worlds to finish correctly.
Korey Sewell [Fri, 7 Jul 2006 19:58:03 +0000 (15:58 -0400)]
Minor fix for SMT Hello Worlds to finish correctly.
Still, there is a problem with the LSQ and indexing out of range in the buffer.
I havent nailed down the fix yet, but it's coming ...

src/cpu/o3/commit_impl.hh:
    add space to DPRINT
src/cpu/o3/cpu.cc:
    add newline to DPRINT
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
    Each thread needs it's own squashedSeqNum for the case where they are both squashing at the same time and they dont
    write over each other's squash number.

--HG--
extra : convert_revision : 2155421a8b5b20e4544eea3d3c53d3e715465fa6

18 years agoSwitch out fixes for CPUs.
Kevin Lim [Fri, 7 Jul 2006 19:38:15 +0000 (15:38 -0400)]
Switch out fixes for CPUs.

src/cpu/o3/cpu.cc:
    Fix up keeping proper state when switched out and drained.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Keep track of the event we use to schedule fetch initially and upon resume.  We may have to cancel the event if the CPU is switched out.

--HG--
extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c

18 years agoRemove hack now that ports work properly
Ron Dreslinski [Fri, 7 Jul 2006 19:16:41 +0000 (15:16 -0400)]
Remove hack now that ports work properly

--HG--
extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d

18 years agoUpdate cpus to use the getPort function to use a connector object to connect the...
Ron Dreslinski [Fri, 7 Jul 2006 19:15:11 +0000 (15:15 -0400)]
Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory

configs/test/test.py:
    Update to use new cpu getPort functionality
src/cpu/base.cc:
    Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
    Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
    Make sure the cache recognizes all port names

--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61

18 years agoMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Korey Sewell [Fri, 7 Jul 2006 08:07:00 +0000 (04:07 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 90717b492139428e0c48be35a6bda45960c61086

18 years agoFix so that O3CPU doesnt segfault on exit.
Korey Sewell [Fri, 7 Jul 2006 08:06:26 +0000 (04:06 -0400)]
Fix so that O3CPU doesnt segfault on exit.
Major thing was to not execute commit if there are no active threads in CPU.

src/cpu/o3/alpha/thread_context.hh:
    call deallocate instead of deallocateContext
src/cpu/o3/commit_impl.hh:
    dont run commit stage if there are no instructions
src/cpu/o3/cpu.cc:
    add deallocate event, deactivateThread function, and edit deallocateContext.
src/cpu/o3/cpu.hh:
    add deallocate event and add optional delay to deallocateContext
src/cpu/o3/thread_context.hh:
    optional delay for deallocate
src/cpu/o3/thread_context_impl.hh:
    edit DPRINTFs to say Thread Context instead of Alpha TC
src/cpu/thread_context.hh:
    optional delay
src/sim/syscall_emul.hh:
    name stuff

--HG--
extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Fri, 7 Jul 2006 03:20:44 +0000 (23:20 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 942c43e2fdd68cde7aaaba5e88a667f80feab162

18 years agoBe sure to call resume after restoring from a checkpoint.
Kevin Lim [Fri, 7 Jul 2006 03:16:22 +0000 (23:16 -0400)]
Be sure to call resume after restoring from a checkpoint.

--HG--
extra : convert_revision : 4d672917038779a23f4ce7eb5d4e3039c1f5d726

18 years agoSupport serializing and unserializing in the O3 CPU. Also a few small fixes for...
Kevin Lim [Fri, 7 Jul 2006 03:13:38 +0000 (23:13 -0400)]
Support serializing and unserializing in the O3 CPU.  Also a few small fixes for draining/switching CPUs.

src/cpu/o3/commit_impl.hh:
    Fix to clear drainPending variable on call to resume.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Support serializing and unserializing in the O3 CPU.
src/cpu/o3/lsq_impl.hh:
    Be sure to say we have no stores to write back if the active thread list is empty.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Slightly change how SimpleThread is used to copy from other ThreadContexts.

--HG--
extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121

18 years agoFix the O3CPU to support the multi-pass method for checking if the system has fully...
Kevin Lim [Thu, 6 Jul 2006 21:57:20 +0000 (17:57 -0400)]
Fix the O3CPU to support the multi-pass method for checking if the system has fully drained.

src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Return a value so that the CPU can instantly return from draining if the pipeline is already drained.
src/cpu/o3/cpu.cc:
    Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained.

--HG--
extra : convert_revision : d8ef6b811644ea67c8b40c4719273fa224105811

18 years agoVarious serialization changes to make it possible for the O3CPU to checkpoint.
Kevin Lim [Thu, 6 Jul 2006 21:53:26 +0000 (17:53 -0400)]
Various serialization changes to make it possible for the O3CPU to checkpoint.

src/arch/alpha/regfile.hh:
    Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
    Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Push common serialization code to ThreadState level.  Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
    Move common serialization code into ThreadState.

--HG--
extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b

18 years agoTiming cache works for hello world test.
Ron Dreslinski [Thu, 6 Jul 2006 20:52:05 +0000 (16:52 -0400)]
Timing cache works for hello world test.
Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))

src/cpu/simple/timing.cc:
    Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
    Handle marking MSHR's in service
    Add support for getting CSHR's
src/mem/cache/base_cache.hh:
    Make these functions visible at the base cache level
src/mem/cache/cache.hh:
    make the functions virtual
src/mem/cache/cache_impl.hh:
    Rename the function to make sense
src/mem/packet.hh:
    Accidentally clearing the needsResponse field when sending a response back.

--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Thu, 6 Jul 2006 20:51:50 +0000 (16:51 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 7c7fc8a2f9579d443786e86dbcf906b355de69fc

18 years agoTwo minor FS compile fixes.
Kevin Lim [Thu, 6 Jul 2006 20:26:44 +0000 (16:26 -0400)]
Two minor FS compile fixes.

src/dev/tsunami_pchip.hh:
    Need ULL() for 32-bit hosts.
src/sim/pseudo_inst.cc:
    Forgot to remove sampler include from here.

--HG--
extra : convert_revision : 6ab6bdc721290167b4c2b78da3d28a4992eb24d5

18 years agoFixes for draining.
Kevin Lim [Thu, 6 Jul 2006 20:06:00 +0000 (16:06 -0400)]
Fixes for draining.

src/cpu/simple/timing.cc:
    Update for changed return values.
src/python/m5/__init__.py:
    Loop in order to make sure all objects are really drained.  Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus).

    The only case we know every object is actually drained is if they all return immediately that they are drained.

--HG--
extra : convert_revision : 80057a1d6d30381bd0b67b23549bd202f447c5cb

18 years agoMerge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski [Thu, 6 Jul 2006 19:16:15 +0000 (15:16 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 507eefde3514c35ca8420408cc89590d83cc6fc6

18 years agoNow timing reads work in single level of cache with simple cpu
Ron Dreslinski [Thu, 6 Jul 2006 19:15:37 +0000 (15:15 -0400)]
Now timing reads work in single level of cache with simple cpu

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
    Changes to handle timing reads in Simple CPU (blocking buffers)

--HG--
extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Thu, 6 Jul 2006 18:54:09 +0000 (14:54 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0c4fbbe0826358a6a58f844bec34ce830ffd4ced

18 years agoMerge zizzer:/bk/newmem
Ali Saidi [Thu, 6 Jul 2006 18:41:09 +0000 (14:41 -0400)]
Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 4669e87d29fa3e0ca9009f6b9dce72113220d7bc

18 years agoAdd default responder to bus
Ali Saidi [Thu, 6 Jul 2006 18:41:01 +0000 (14:41 -0400)]
Add default responder to bus
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset

configs/test/fs.py:
    Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
    Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
    change naming for pio port
    break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
    removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
    add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
    remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
    bus:dev:func and interrupt
src/dev/sinic.cc:
    remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
    add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    add idea of default responder to bus
src/python/m5/objects/Pci.py:
    add config port for pci devices
    add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)

--HG--
extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Thu, 6 Jul 2006 17:59:13 +0000 (13:59 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 00f8eecf99c771ae8943ed1d3a652bfbcfe1c6bc

18 years agoSupport for draining, and the new method of switching out. Now switching out happens...
Kevin Lim [Thu, 6 Jul 2006 17:59:02 +0000 (13:59 -0400)]
Support for draining, and the new method of switching out.  Now switching out happens after the pipeline has been drained, deferring the three way handshake to the normal drain mechanism.  The calls of switchOut() and takeOverFrom() both take action immediately.

src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Support for draining, new method of switching out.

--HG--
extra : convert_revision : 05bf8b271ec85b3e2c675c3bed6c42aeba21f465

18 years agoChange the return value of drain. False means the object wasn't able to drain yet.
Kevin Lim [Thu, 6 Jul 2006 17:57:21 +0000 (13:57 -0400)]
Change the return value of drain.  False means the object wasn't able to drain yet.

src/python/m5/config.py:
    Invert the return value.
src/sim/sim_object.cc:
    Invert the return value of drain.
src/sim/sim_object.hh:
    Change the return value of drain.

--HG--
extra : convert_revision : 41bb122c6f29302d8b3815d7bd6a2ea8fba64df9

18 years agoHad to add this because for some reason gcc wasnt recognizing "THE_ISA == ALPHA_ISA...
Korey Sewell [Thu, 6 Jul 2006 16:29:34 +0000 (12:29 -0400)]
Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALPHA_ISA"... wierd but OK

--HG--
extra : convert_revision : f847d6c01212e32200a319c16596b8e1c1d15c7d

18 years agoMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Korey Sewell [Thu, 6 Jul 2006 16:19:29 +0000 (12:19 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 2f08ea52ef54118d42aa590c0d86aa0cc7988713

18 years agoUse O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific...
Korey Sewell [Thu, 6 Jul 2006 16:18:55 +0000 (12:18 -0400)]
Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.

src/cpu/cpu_models.py:
    Use O3DynInst
src/cpu/o3/dyn_inst.hh:
    declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
    take out O3 forward declarations here and include header file to keep this file clean

--HG--
extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0

18 years agomore steps toward O3 SMT
Korey Sewell [Thu, 6 Jul 2006 15:25:44 +0000 (11:25 -0400)]
more steps toward O3 SMT

src/arch/mips/isa/formats/fp.isa:
    Adjust for newmem
src/cpu/cpu_models.py:
    Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
    take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
    open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
    Add O3DynInst
src/cpu/o3/dyn_inst.hh:
    Use to get ISA-specific O3DynInst

--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe

18 years agoFor now using the checkpoint or switchcpu pseudo instructions will return control...
Kevin Lim [Thu, 6 Jul 2006 03:38:11 +0000 (23:38 -0400)]
For now using the checkpoint or switchcpu pseudo instructions will return control to Python, returning the cause to be the instruction name.  The user's script must then interpret the reason for exiting the simulation loop and handle the action accordingly.  This may change in the future.

src/sim/pseudo_inst.cc:
    Exit sim loop with a specific string to indicate to Python what caused the exit.  The user's script needs to interpret the exit events and handle them as desired.

--HG--
extra : convert_revision : 8eb4a42285dacb3ada3a791173c605b5acb78598

18 years agoRemove sampler and serializer. Now they are handled through C++ interacting with...
Kevin Lim [Thu, 6 Jul 2006 01:14:36 +0000 (21:14 -0400)]
Remove sampler and serializer.  Now they are handled through C++ interacting with Python.

src/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/sim/pseudo_inst.cc:
    Remove sampler.
src/sim/sim_object.cc:
    Remove serializer.

--HG--
extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008

18 years agoRename quiesce to drain to avoid confusion with the pseudo instruction.
Kevin Lim [Wed, 5 Jul 2006 21:59:33 +0000 (17:59 -0400)]
Rename quiesce to drain to avoid confusion with the pseudo instruction.

src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/python/m5/__init__.py:
src/python/m5/config.py:
src/sim/main.cc:
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_object.cc:
src/sim/sim_object.hh:
    Rename quiesce to drain.

--HG--
extra : convert_revision : fc3244a3934812e1edb8050f1f51f30382baf774

18 years agoChecker ignores any faults that occur in syscall emulation mode for now.
Kevin Lim [Wed, 5 Jul 2006 21:25:37 +0000 (17:25 -0400)]
Checker ignores any faults that occur in syscall emulation mode for now.

src/cpu/checker/cpu_impl.hh:
    The only fault we handle in SE causes troubles when invoked with the Checker.  This is because it changes state within the process, and not the checker, so the state isn't correct when the main CPU calls invoke.  It's safe to just ignore the fault in the Checker and continue.

--HG--
extra : convert_revision : 5000d763a75009c7a6011646a6790ac5b23df6bb

18 years agoFix up some merge problems.
Kevin Lim [Wed, 5 Jul 2006 20:54:24 +0000 (16:54 -0400)]
Fix up some merge problems.

src/base/traceflags.py:
    Remove BaseCPU traceflag.
src/cpu/o3/alpha/params.hh:
    Move non-Alpha specific parameters out of this params class.
src/cpu/o3/params.hh:
    Move non-Alpha specific params into this params class.

--HG--
extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Wed, 5 Jul 2006 20:08:18 +0000 (16:08 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

src/base/traceflags.py:
src/cpu/SConscript:
    Hand merge.
src/cpu/o3/alpha/params.hh:
    Hand merge.  This needs to get changed.

--HG--
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Wed, 5 Jul 2006 20:01:38 +0000 (16:01 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : f5b6daa2d512f38153246fc9a39cc6560d939ebc

18 years agoNeed to change state upon quiescing.
Kevin Lim [Wed, 5 Jul 2006 19:57:02 +0000 (15:57 -0400)]
Need to change state upon quiescing.

--HG--
extra : convert_revision : 25e3b0a463a0191cab9290665409d0abca6a179a

18 years agoAlphabetize traceflags, rename FullCPUAll flag to O3CPUAll.
Kevin Lim [Wed, 5 Jul 2006 19:55:45 +0000 (15:55 -0400)]
Alphabetize traceflags, rename FullCPUAll flag to O3CPUAll.

--HG--
extra : convert_revision : f558966154376223674c82d513afc2dad6591426

18 years agoSplit off files that are shared across the O3 and Ozone models.
Kevin Lim [Wed, 5 Jul 2006 19:53:22 +0000 (15:53 -0400)]
Split off files that are shared across the O3 and Ozone models.

--HG--
extra : convert_revision : 023e84660d5cee5162d39548f87e5ca8ec68115f

18 years agoAdd some different parameters. The main change is that the writeback count is now...
Kevin Lim [Wed, 5 Jul 2006 19:51:36 +0000 (15:51 -0400)]
Add some different parameters.  The main change is that the writeback count is now limited so that it doesn't overflow the buffer.

src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
    Add in dispatchWidth, wbWidth, wbDepth parameters.  wbDepth is the number of cycles of wbWidth instructions that can be buffered.
src/cpu/o3/iew.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.  The IQ must make sure with the IEW stage that it can issue instructions prior to issuing.
src/cpu/o3/iew_impl.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.
src/cpu/o3/inst_queue_impl.hh:
    IQ needs to check with the IEW to make sure it can issue instructions, and increments the IEW wb counter each time there is an outstanding instruction that will writeback.
src/cpu/o3/lsq_unit_impl.hh:
    Be sure to decrement the writeback counter if there's a squashed load that returned.
src/python/m5/objects/AlphaO3CPU.py:
    Change the parameters to include dispatch width, writeback width, and writeback depth.

--HG--
extra : convert_revision : 31c8cc495273e3c481b79055562fc40f71291fc4

18 years agoFix some unset values in the request in the timing CPU.
Ron Dreslinski [Wed, 5 Jul 2006 19:13:27 +0000 (15:13 -0400)]
Fix some unset values in the request in the timing CPU.
Properly implement the MSHR allocate function.

src/cpu/simple/timing.cc:
    Set the thread context in the CPU.

    Need to do this properly, currently I just set it to Cpu=0 Thread=0.  This will just cause all the stats in the cache based on these to just yield totals and not a distribution.
src/mem/cache/miss/mshr.cc:
    Properly implement the allocate function for the MSHR.

--HG--
extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e

18 years agoMerge ktlim@zamp:/z/ktlim2/clean/newmem-merge
Kevin Lim [Wed, 5 Jul 2006 17:22:46 +0000 (13:22 -0400)]
Merge ktlim@zamp:/z/ktlim2/clean/newmem-merge
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 20e45bec8c3911a6389a89e2d193aa1de867c89e

18 years agoFix for FS O3CPU compile ... missing forward class declaration/header file after...
Korey Sewell [Mon, 3 Jul 2006 16:19:35 +0000 (12:19 -0400)]
Fix for FS O3CPU compile ... missing forward class declaration/header file after files got split for ISA-independence

src/cpu/o3/alpha/thread_context.hh:
    Use 'this' when accessing cpu
src/cpu/o3/cpu.hh:
    add numActiveThreds function
src/cpu/o3/thread_context.hh:
    forward class declarations
src/cpu/o3/thread_context_impl.hh:
    add quiesce event header file
src/cpu/thread_context.hh:
    add exit() function to thread context (read comments in file)
src/sim/syscall_emul.cc:
    adjust exitFunc syscall

--HG--
extra : convert_revision : 323dc871e2b4f4ee5036be388ceb6634cd85a83e

18 years agoAdded hook to check for SMT workloads. SMT is identified by adding a semicolon between
Korey Sewell [Mon, 3 Jul 2006 05:10:19 +0000 (01:10 -0400)]
Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
the workloads.

Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" -i="file1;file2"

I think I am a novice python magician now!!!!....

configs/test/test.py:
    Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
    the workloads.

    Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" --input="file1;file2"
    (btw, We are back to working for this double hello world case)

    I am a novice python magician now!!!!....

--HG--
extra : convert_revision : b55e10dce33f5a9dc4c78f90409ec0912bad4292

18 years agotypo ... change 'single_thread' to 'round_robin_policy'
Korey Sewell [Mon, 3 Jul 2006 03:27:13 +0000 (23:27 -0400)]
typo ... change 'single_thread' to 'round_robin_policy'

--HG--
extra : convert_revision : a4a5cb90557f786d42c6178bc6e268312c5ecbee

18 years agoFix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Korey Sewell [Mon, 3 Jul 2006 03:11:24 +0000 (23:11 -0400)]
Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)

Edit Test3 for newmem

src/base/traceflags.py:
    Add O3CPU flag
src/cpu/base.cc:
    for some reason adding a BaseCPU flag doesnt work so just go back to old way...
src/cpu/o3/alpha/cpu_builder.cc:
    Determine number threads by workload size instead of solely by parameter.

    Default SMT fetch policy to RoundRobin if it's not specified in Config file
src/cpu/o3/commit.hh:
    only use nextNPC for !ALPHA
src/cpu/o3/commit_impl.hh:
    add FetchTrapPending as condition for commit
src/cpu/o3/cpu.cc:
    panic if active threads is more than Impl::MaxThreads
src/cpu/o3/fetch.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
    name stuff
src/cpu/o3/fetch_impl.hh:
    fatal if try to use SMT branch count, that's unimplemented right now
src/python/m5/config.py:
    make it clearer that a parameter is not valid within a configuration class

--HG--
extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34

18 years agotraceflag stuff
Korey Sewell [Sat, 1 Jul 2006 23:02:43 +0000 (19:02 -0400)]
traceflag stuff

src/base/traceflags.py:
    add BaseCPU flag, O3CPUAll flag grouping
src/cpu/base.cc:
    Use BaseCPU flag instead of FullCPU flag

--HG--
extra : convert_revision : 32f737a2f58eb936634799f1f809e07cbba90179

18 years agofix cpu builder to build the correct name...
Korey Sewell [Sat, 1 Jul 2006 22:52:02 +0000 (18:52 -0400)]
fix cpu builder to build the correct name...

add activateThread event and functions

src/cpu/o3/alpha/cpu_builder.cc:
    Have CPU builder build a DerivO3CPU not a DerivAlphaO3CPU
src/cpu/o3/cpu.cc:
    add activateThread Event

    add activateThread function

    adjust activateContext to schedule a thread to activate within the
    CPU instead of activating thread right away. This will lead to stages
    trying to use threads that  arent ready yet and wasting execution time & possibly
    performance.
src/cpu/o3/cpu.hh:
    add activateThread Event

    add activateThread function

    add schedule/descheculed activate thread event

--HG--
extra : convert_revision : 236d30dc160910507ad36f7f527ab185ed38dc04

18 years agoMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Korey Sewell [Sat, 1 Jul 2006 00:51:07 +0000 (20:51 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 3c1405d8b4831c6240e02ba65a72043ca55f4a46

18 years agonow O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu...
Korey Sewell [Sat, 1 Jul 2006 00:49:31 +0000 (20:49 -0400)]
now O3CPU is totally independent of the ISA... all alpha specific  stuff is the cpu/o3/alpha directory

src/cpu/o3/alpha/cpu.cc:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/impl.hh:
    filenames
src/cpu/o3/alpha/thread_context.hh:
    public
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use O3CPUImpl ... not Alpha
src/cpu/o3/checker_builder.cc:
    filename

--HG--
extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69

18 years agoMake O3CPU model independent of the ISA
Korey Sewell [Fri, 30 Jun 2006 23:52:08 +0000 (19:52 -0400)]
Make O3CPU model independent of the ISA

Use O3CPU when building instead of AlphaO3CPU.

I could use some better python magic in the cpu_models.py file!

AUTHORS:
    add middle initial
SConstruct:
    change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
    edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
    change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...

    Actually, some Python expertise could be used here. The 'env' variable is not
    passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use isa_specific.hh
src/sim/process.cc:
    only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
    alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
    move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
    Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
    include paths
src/cpu/o3/alpha/impl.hh:
    include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
    set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
    add O3CPU class
src/cpu/o3/SConscript:
    include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
    NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
    new home of AlphaTC
src/cpu/o3/isa_specific.hh:
    includes ISA specific files
src/cpu/o3/params.hh:
    base o3 params
src/cpu/o3/thread_context.hh:
    base o3 thread context
src/cpu/o3/thread_context_impl.hh:
    base o3 thead context impl

--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e

18 years agoAtomicSimpleCPU with a cache now runs the hello world! test program.
Ron Dreslinski [Fri, 30 Jun 2006 21:21:58 +0000 (17:21 -0400)]
AtomicSimpleCPU with a cache now runs the hello world! test program.
Need to clean up a bunch of flags/hacks in the code.  Then onto Timming mode.

Functional accesses also work properly, although not exactly how we wanted them.  I'll need to clean that up as well.

src/cpu/simple/atomic.cc:
    Atomic CPU needs to set thread context so stats work in cache.  Temporarily just use CPU=0 ThreadID=0
src/mem/cache/cache_impl.hh:
    Need to return success/failure properly still
    Physical memory object doesn't assert SATISFIED anymore, need to remove that flag
src/mem/cache/tags/lru.cc:
    Doesn't work if the REQ doesn't set it's ASID.  Temporary fix use 0 always

--HG--
extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050

18 years agoFirst pass, now compiles with current head of tree.
Ron Dreslinski [Fri, 30 Jun 2006 20:25:35 +0000 (16:25 -0400)]
First pass, now compiles with current head of tree.
Compile and initialization work, still working on functionality.

src/mem/cache/base_cache.cc:
    Temp fix for cpu's use of getPort functionality.  CPU's will need to be ported to the new connector objects.
    Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
    Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
    fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
    Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
    Update for newmem

--HG--
extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb

18 years agoFix the packet data allocation methods. Small fixes from changesets after my initial...
Ron Dreslinski [Fri, 30 Jun 2006 15:34:27 +0000 (11:34 -0400)]
Fix the packet data allocation methods.  Small fixes from changesets after my initial work.

This now compiles.

src/mem/cache/base_cache.cc:
    Fix getPort function that changed
src/mem/cache/base_cache.hh:
    Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
    Fix virtual function declerations
src/mem/cache/cache_builder.cc:
    Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
    Properly allocate data in packet

--HG--
extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48

18 years agoMerge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski [Fri, 30 Jun 2006 14:25:50 +0000 (10:25 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 6eefb4a3ee472f2f2c86ed823c70fc9e5625818f

18 years agoAll files compile in the mem directory except cache_builder
Ron Dreslinski [Fri, 30 Jun 2006 14:25:25 +0000 (10:25 -0400)]
All files compile in the mem directory except cache_builder

Missing some functionality (like split caches and copy support)

src/SConscript:
    Typo
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.hh:
src/mem/request.hh:
    Fix so it compiles

--HG--
extra : convert_revision : 0d87d84f6e9445bab655c0cb0f8541bbf6eab904

18 years agoMerge ktlim@zizzer:/bk/newmem
Kevin Lim [Fri, 30 Jun 2006 01:38:16 +0000 (21:38 -0400)]
Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0756f7f1f63fae472e0ef1d20e9eb38e56de78c8

18 years agoRemove function that no longer can be used. We should figure out if we want to allow...
Kevin Lim [Fri, 30 Jun 2006 01:34:01 +0000 (21:34 -0400)]
Remove function that no longer can be used.  We should figure out if we want to allow the m5checkpoint pseudoinstruction or not.

src/sim/pseudo_inst.cc:
    Remove the setup function from Checkpoint.  I'm not sure what we want to do with this pseudoinst.
src/sim/serialize.hh:
    Remove setup function.

--HG--
extra : convert_revision : 5ff494d816e2d8a7fe65a3d13037608003388d8f

18 years agoMerge ktlim@zamp:/z/ktlim2/clean/newmem-merge
Kevin Lim [Thu, 29 Jun 2006 23:45:53 +0000 (19:45 -0400)]
Merge ktlim@zamp:/z/ktlim2/clean/newmem-merge
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 9e21cdbb4fce8d9eb5f92780b720c42c44b6dd57

18 years agoVarious fixes for the CPU models to support the features that have been moved to...
Kevin Lim [Thu, 29 Jun 2006 23:45:24 +0000 (19:45 -0400)]
Various fixes for the CPU models to support the features that have been moved to python.

src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/simple/atomic.hh:
    Switching out no longer takes a sampler.
src/cpu/simple/atomic.cc:
    Fix up switching out.  Also fix up serialization; the nameOut() was messing up the ordering.
src/cpu/simple/timing.cc:
    Add in quiesce, fix up serialization.
src/cpu/simple/timing.hh:
    Add in queisce, fix up serialization.

--HG--
extra : convert_revision : 9d59d53bdf269d4d82fb119e5ae7c8a5d475880b

18 years agoAdd in support for quiescing the system, taking checkpoints, restoring from checkpoin...
Kevin Lim [Thu, 29 Jun 2006 23:40:12 +0000 (19:40 -0400)]
Add in support for quiescing the system, taking checkpoints, restoring from checkpoints, changing memory modes, and switching CPUs.

Key new functions that can be called on the m5 object at the python interpreter:
doQuiesce(root) - A helper function that quiesces the object passed in and all of its children.
resume(root) - Another helper function that tells the object and all of its children that the quiesce is over.
checkpoint(root) - Takes a checkpoint of the system.  Checkpoint directory must be set before hand.
setCheckpointDir(name) - Sets the checkpoint directory.
restoreCheckpoint(root) - Restores the values from the checkpoint located in the checkpoint directory.
changeToAtomic(system) - Changes the system and all of its children to atomic memory mode.
changeToTiming(system) - Changes the system and all of its children to timing memory mode.
switchCpus(list) - Takes in a list of tuples, where each tuple is a pair of (old CPU, new CPU).  Quiesces the old CPUs, and then switches over to the new CPUs.

src/SConscript:
    Remove serializer, replaced by python code.
src/python/m5/__init__.py:
    Updates to support quiescing, checkpointing, changing memory modes, and switching CPUs.
src/python/m5/config.py:
    Several functions defined on the SimObject for quiescing, changing timing modes, and switching CPUs
src/sim/main.cc:
    Add some extra functions that are exported to python through SWIG.
src/sim/serialize.cc:
    Change serialization around a bit.  Now it is controlled through Python, so there's no need for SerializeEvents or SerializeParams.

    Also add in a new unserializeAll() function that loads a checkpoint and handles unserializing all objects.
src/sim/serialize.hh:
    Add unserializeAll function and a setCheckpointName function.
src/sim/sim_events.cc:
    Add process() function for CountedQuiesceEvent, which calls exitSimLoop() once its counter reaches 0.
src/sim/sim_events.hh:
    Add in a CountedQuiesceEvent, which is used when the system is preparing to quiesce.  Any objects that can't be quiesced immediately are given a pointer to a CountedQuiesceEvent.  The event has its counter set via Python, and as objects finish quiescing they call process() on the event.  Eventually the event causes the simulation to stop once all objects have quiesced.
src/sim/sim_object.cc:
    Add a few functions for quiescing, checkpointing, and changing memory modes.
src/sim/sim_object.hh:
    Add a state variable to all SimObjects that tracks both the timing mode of the object and the quiesce state of the object.  Currently this isn't serialized, and I'm not sure it needs to be so long as the timing mode starts up the same after a checkpoint.

--HG--
extra : convert_revision : a8c738d3911c68d5a7caf7de24d732dcc62cfb61

18 years agoUpdate the readme to point people to m5.eecs.umich.edu
Ali Saidi [Thu, 29 Jun 2006 20:52:47 +0000 (16:52 -0400)]
Update the readme to point people to m5.eecs.umich.edu
start a new release section in RELEASE_NOTES
add AUTHORS file that still needs work

README:
    Update the readme to point people to m5.eecs.umich.edu
RELEASE_NOTES:
    start a new release section

--HG--
extra : convert_revision : 4c51e4255aecb67b10f18337428e5af114759d2e

18 years agoStill missing prefetch and tags directories as well as cache builder.
Ron Dreslinski [Thu, 29 Jun 2006 20:07:19 +0000 (16:07 -0400)]
Still missing prefetch and tags directories as well as cache builder.
Some implementation details were left blank still, need to fill them in.

src/SConscript:
    Reorder build to compile all files first
src/mem/cache/cache.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
    More changesets pulled, now compiles everything in /miss directory and in the root directory
src/mem/packet.hh:
    Add some more support, need to clean some of it out once everything is working

--HG--
extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800

18 years agoMore Changes, working towards cache.cc compiling. Headers cleaned up.
Ron Dreslinski [Wed, 28 Jun 2006 21:28:33 +0000 (17:28 -0400)]
More Changes, working towards cache.cc compiling.  Headers cleaned up.

src/mem/cache/cache_blk.hh:
    Remove XC

--HG--
extra : convert_revision : aa2c43e4412ebb93165e12f693d5126983cfd0dc

18 years agoBacking in more changsets, getting closer to compile
Ron Dreslinski [Wed, 28 Jun 2006 18:35:00 +0000 (14:35 -0400)]
Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on

src/SConscript:
    Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
    Backing in more changsets, getting closer to compile

--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed

18 years agoWas having difficulty with merging the cache, reverted to an early version and will...
Ron Dreslinski [Wed, 28 Jun 2006 15:02:14 +0000 (11:02 -0400)]
Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon.

src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
    Trying to merge
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/prefetch/ghb_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.cc:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher.hh:
src/mem/cache/tags/base_tags.cc:
src/mem/cache/tags/base_tags.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/repl/gen.cc:
src/mem/cache/tags/repl/gen.hh:
src/mem/cache/tags/repl/repl.cc:
src/mem/cache/tags/repl/repl.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_blk.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
    Pulling an early version of the cache into the tree due to merging issues.  Will apply patches and push.

--HG--
extra : convert_revision : 3276e5fb9a6272681a1690babf2b586dd0e1f380