binutils-gdb.git
8 years agoPass relocations to Target::do_calls_non_split.
Cary Coutant [Fri, 11 Dec 2015 22:20:41 +0000 (14:20 -0800)]
Pass relocations to Target::do_calls_non_split.

gold/
* target.h (Target::calls_non_split): Add prelocs, reloc_count
parameters.
(Target::do_calls_non_split): Likewise.
* target.cc (Target::do_calls_non_split): Likewise.
* reloc.cc (Sized_relobj_file::split_stack_adjust_reltype): Adjust
call to Target::calls_non_split.

* i386.cc (Target_i386::do_calls_non_split): Add prelocs, reloc_count
parameters.
* powerpc.cc (Target_powerpc::do_calls_non_split): Likewise.
* x86_64.cc (Target_x86_64::do_calls_non_split): Likewise.

8 years agoMake output views accessible to Target during do_relocate().
Cary Coutant [Fri, 11 Dec 2015 22:01:22 +0000 (14:01 -0800)]
Make output views accessible to Target during do_relocate().

gold/
* object.cc (Sized_relobj_file::Sized_relobj_file): Initialize
output_views_.
* object.h (Object::get_output_view): New function.
(Object::do_get_output_view): New function.
(Sized_relobj_file::do_get_output_view): New function.
(Sized_relobj_file::output_views_): New data member.
* reloc.cc: (Sized_relobj_file::do_relocate): Store pointer to
output views in class object.
(Sized_relobj_file::do_get_output_view): New function.

8 years agoRemove gdb.base/coremaker2.c
Yao Qi [Fri, 11 Dec 2015 16:21:09 +0000 (16:21 +0000)]
Remove gdb.base/coremaker2.c

I happen to find that coremaker2.c isn't used in the testsuite (if I
don't miss anything).  I don't believe it until I see this ChangeLog
entry,

1999-11-18  Fred Fish  <fnf@cygnus.com>

        * gdb.base/coremaker2.c: Add sample program for generating
        cores that is more self contained than coremaker.c.  Eventually
        I'll add more code to this and tie it into the testsuite.

looks Fred didn't "tie it into testsuite" later.

gdb/testsuite:

2015-12-11  Yao Qi  <yao.qi@linaro.org>

* gdb.base/coremaker2.c: Remove.

8 years agoUnderstand arm breakpoints in aarch64_breakpoint_at
Yao Qi [Fri, 11 Dec 2015 11:19:52 +0000 (11:19 +0000)]
Understand arm breakpoints in aarch64_breakpoint_at

AArch64 GDBserver can debug ARM program, and it should recognize
various arm breakpoint instructions.  This patch should be included
in 17b1509a.

gdb/gdbserver:

2015-12-11  Yao Qi  <yao.qi@linaro.org>

* linux-aarch64-low.c (aarch64_breakpoint_at): Call
arm_breakpoint_at if the process is 32-bit.

8 years agoUse arm_eabi_breakpoint on aarch32
Yao Qi [Fri, 11 Dec 2015 11:19:52 +0000 (11:19 +0000)]
Use arm_eabi_breakpoint on aarch32

Nowdays, GDBserver chooses arm breakpoint instructions by checking
macro __ARM_EABI__.  When aarch64 GDBserver debugs arm program,
arm_eabi_breakpoint is still needed, but __ARM_EABI__ isn't defined
in aarch64 compiler.  This causes GDBserver chooses the wrong
breakpoint instruction for arm program.  This patch fixes it.

gdb/gdbserver:

2015-12-11  Yao Qi  <yao.qi@linaro.org>

* linux-aarch32-low.c [__aarch64__]: Use arm_abi_breakpoint
arm breakpoint.

8 years ago[AArch64][Patch 5/5] Add instruction PSB CSYNC
Matthew Wahab [Fri, 11 Dec 2015 10:22:40 +0000 (10:22 +0000)]
[AArch64][Patch 5/5] Add instruction PSB CSYNC

The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.

A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
(parse_barrier_psb): New.
(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
(md_begin): Set up aarch64_hint_opt_hsh.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/system-2.d: Enable the statistical profiling
extension.  Update the expected output.
* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
* gas/aarch64/system.d: Update the expected output.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): Add "csync".
(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_feature_stat_profile): New.
(STAT_PROFILE): New.
(aarch64_opcode_table): Add "psb".
(AARCH64_OPERANDS): Add "BARRIER_PSB".

Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09

8 years ago[AArch64][Patch 4/5] Support HINT aliases taking operands.
Matthew Wahab [Fri, 11 Dec 2015 10:11:27 +0000 (10:11 +0000)]
[AArch64][Patch 4/5] Support HINT aliases taking operands.

The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64.h (aarch64_hint_options): Declare.
(aarch64_opnd_info): Add field hint_option.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-asm.c (aarch64_ins_hint): New.
* aarch64-asm.h (aarch64_ins_hint): Declare.
* aarch64-dis.c (aarch64_ext_hint): New.
* aarch64-dis.h (aarch64_ext_hint): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): New.
* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.

Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287

8 years ago[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
Matthew Wahab [Fri, 11 Dec 2015 09:56:07 +0000 (09:56 +0000)]
[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.

The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. The HINT instruction currently has 8
aliases, which is the maximum number allowed. This patch raises to 16
the limit on the number of aliases an instruction can have.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.

Change-Id: I131044bf6e0fe0940a9e7478d9bf52137748907d

8 years ago[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
Matthew Wahab [Fri, 11 Dec 2015 09:52:11 +0000 (09:52 +0000)]
[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.

The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
pmscr_el2.
(aarch64_sys_reg_supported_p): Add architecture feature tests for
the new registers.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
system registers.
* gas/aarch64/sysreg-2.d: Enable the statistical profiling
extension and update the expected output.

Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb

8 years ago[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
Matthew Wahab [Fri, 11 Dec 2015 09:30:26 +0000 (09:30 +0000)]
[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.

The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.

The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.

This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* config/tc-aarch64.c (aarch64_features): Add "profile".
* doc/c-aarch64.texi (AArch64 Extensions): Add "profile".

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64.h (AARCH64_FEATURE_PROFILE): New.

Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699

8 years agoAutomatic date update in version.in
GDB Administrator [Fri, 11 Dec 2015 00:00:13 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agold -r doesn't need plugin for slim lto object
H.J. Lu [Thu, 10 Dec 2015 20:35:35 +0000 (12:35 -0800)]
ld -r doesn't need plugin for slim lto object

Plugin isn't required on slim lto object for relocatable link.

bfd/

PR ld/19317
* linker.c (_bfd_generic_link_add_one_symbol): Don't complain
plugin needed to handle slim lto object for relocatable link.

ld/testsuite/

PR ld/19317
* ld-plugin/lto.exp (lto_no_fat): New.
(lto_link_tests): Add a test for PR ld/19317.
(lto_run_tests): Likewise.
(run_ld_link_tests): Likewise.

8 years agoFix regression revealed by corethreads.exp
Antoine Tremblay [Thu, 10 Dec 2015 19:43:48 +0000 (14:43 -0500)]
Fix regression revealed by corethreads.exp

This patch fixes a regression introduced by:
https://sourceware.org/ml/gdb-patches/2015-12/msg00192.html

We can't use thread_from_lwp with core files.  As mentioned in a comment,
td_ta_map_lwp2thr uses ps_get_thread_area, but we can't use that
currently on core targets, as it uses ptrace directly.

Use directly record_thread instead.

This fixes :
PASS -> FAIL: gdb.threads/corethreads.exp: thread0 found
PASS -> FAIL: gdb.threads/corethreads.exp: thread1 found

gdb/ChangeLog:

* linux-thread-db.c (find_new_threads_callback): Use record_thread.

8 years agold -r doesn't need plugin for slim lto object
H.J. Lu [Thu, 10 Dec 2015 19:28:48 +0000 (11:28 -0800)]
ld -r doesn't need plugin for slim lto object

Plugin isn't required on slim lto object for relocatable link.

PR ld/19317
* symtab.cc (Symbol_table::add_from_relobj): Don't complain
plugin needed to handle slim lto object for relocatable link.

8 years ago[gdb/doc] Explain that there's always a thread
Pedro Alves [Thu, 10 Dec 2015 17:47:57 +0000 (17:47 +0000)]
[gdb/doc] Explain that there's always a thread

This warning is a few years out of date -- there's always a thread
nowadays.

gdb/doc/ChangeLog:

* gdb.texinfo (Threads): Replace warning with explanation
about single-threaded programs.

8 years ago[Aarch64] Support ARMv8.2 AT instructions
Matthew Wahab [Thu, 10 Dec 2015 16:58:51 +0000 (16:58 +0000)]
[Aarch64] Support ARMv8.2 AT instructions

ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".

Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4

8 years ago[gdb/doc] Remove references to no-longer-supported systems
Pedro Alves [Thu, 10 Dec 2015 11:43:19 +0000 (11:43 +0000)]
[gdb/doc] Remove references to no-longer-supported systems

HP-UX and SGI/IRIX are no longer supported.  Remove references
throughout.

AFAICS from the sources, "catch fork" seems to be supported in
multiple Unix systems -- just remove the "only works on xxx" remarks.

Update the list of supported shared library types.

gdb/doc/ChangeLog:

* gdb.texinfo (Threads): Remove mention of SGI.
(Forks): Remove mention of HP-UX.
(Breakpoints): Remove mention of HP-UX.
(Set Watchpoints) <hardware watchpoints>: Don't mention HP-UX.
Reword in terms of architectures.
(Set Catchpoints) <catch exec, catch fork, catch vfork>: Don't
mention supported systems.
(Convenience Vars): Don't mention HP-UX.
(Jumping): Remove mention of HP-UX in comment.
(Files) <shared libraries>: Update supported shared library types
list.  Remove mention of HP-UX.
(Native): Remove HP-UX subsection.
(SVR4 Process Information): Remove mention of HP-UX.

8 years agoRemove "spaces" references from gdb.multi/base.exp
Pedro Alves [Thu, 10 Dec 2015 16:49:32 +0000 (16:49 +0000)]
Remove "spaces" references from gdb.multi/base.exp

I think these references to "spaces" came from the original multi-exec
submission that exposed "symbol spaces" to the user and had a
different UI, and then survived a global find/replace.

gdb/testsuite/ChangeLog:
2015-12-10  Pedro Alves  <palves@redhat.com>

* gdb.multi/base.exp: Remove stale "spaces" references.

8 years ago[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
Matthew Wahab [Thu, 10 Dec 2015 16:38:44 +0000 (16:38 +0000)]
[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.

ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
architectural support for system register.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
* gas/aarch64/sysreg-2.s: Add uses of dc instruction.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
(aarch64_sys_ins_reg_supported_p): New.

Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053

8 years ago[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
Matthew Wahab [Thu, 10 Dec 2015 16:31:35 +0000 (16:31 +0000)]
[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.

ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.

The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
(aarch64_sys_ins_reg_has_xt): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
with aarch64_sys_ins_reg_has_xt.
(aarch64_ext_sysins_op): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
(F_HASXT): New.
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
(aarch64_sys_regs_dc): Likewise.
(aarch64_sys_regs_at): Likewise.
(aarch64_sys_regs_tlbi): Likewise.
(aarch64_sys_ins_reg_has_xt): New.

Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819

8 years agoStop using nowarnings in gdb/testsuite/gdb.multi/
Pedro Alves [Thu, 10 Dec 2015 16:21:06 +0000 (16:21 +0000)]
Stop using nowarnings in gdb/testsuite/gdb.multi/

Several of the gdb.multi tests use the "nowarnings" option to suppress
warnings.  The warnings in question all come from missing headers,
like e.g.:

 src/gdb/testsuite/gdb.multi/multi-arch-exec.c:28:3: warning: incompatible implicit declaration of built-in function 'exit' [enabled by default]
    exit (1);
    ^

There's no point in trying to avoid to include standard headers.  In
gdb.base/hangout.c's case, it's even dangerous, as that file calls
printf.  In order to compile a call to a variatic function correctly,
a declaration must be visible.

gdb/testsuite/ChangeLog:
2015-12-10  Pedro Alves  <palves@redhat.com>

* gdb.multi/base.exp: Don't use nowarnings.
* gdb.multi/bkpt-multi-exec.exp: Don't use nowarnings.
* gdb.multi/hangout.c: Include stdio.h.
* gdb.multi/hello.c: Include stdlib.h.
* gdb.multi/multi-arch-exec.c: Include stdlib.h.
* gdb.multi/multi-arch-exec.exp: Don't use nowarnings.
* gdb.multi/multi-arch.exp: Don't use nowarnings.

8 years agold: Fix LTO for MinGW targets
Kwok Cheung Yeung [Thu, 10 Dec 2015 16:11:07 +0000 (16:11 +0000)]
ld: Fix LTO for MinGW targets

When creating a dummy BFD for an IR file, the output BFD is used as
a template for the new BFD, when it needs to be the input BFD passed
into the function when not dealing with a BFD plugin.

On most targets this is not an issue as the input and output formats
are the same anyway, but on MinGW targets, there are two variant
formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are
similar but not interchangeable here.

PR ld/18199
* plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the
template when calling bfd_create if it does not use the BFD
plugin target vector.

8 years ago[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.
Matthew Wahab [Thu, 10 Dec 2015 16:01:29 +0000 (16:01 +0000)]
[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.

ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for
this bit to binutils, following the same basic pattern as for
PSTATE.PAN. The new control bit is only available when -march=armv8.2-a
is specified.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/uao-directive.d: New.
* gas/aarch64/uao.d: New.
* gas/aarch64/uao.s: New.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-opc.c (aarch64_sys_regs): Add "uao".
(aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
(aarch64_pstatefields): Add "uao".
(aarch64_pstatefield_supported_p): Add checks for "uao".

Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896

8 years agogas: documentation for the SPARC %dN and %qN fp registers notation
Jose E. Marchesi [Thu, 10 Dec 2015 16:01:35 +0000 (11:01 -0500)]
gas: documentation for the SPARC %dN and %qN fp registers notation

gas/ChangeLog:

2015-12-10  Jose E. Marchesi  <jose.marchesi@oracle.com>

* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
for floating-point registers.

8 years agoRemove support for thread events without PTRACE_EVENT_CLONE in GDB
Antoine Tremblay [Thu, 10 Dec 2015 15:44:08 +0000 (10:44 -0500)]
Remove support for thread events without PTRACE_EVENT_CLONE in GDB

Before, on systems that did not support PTRACE_EVENT_CLONE, both GDB and
GDBServer coordinated with libthread_db.so to insert breakpoints at magic
locations in libpthread.so, in order to break at thread creation and
thread death.

Support for thread events was removed from GDBServer as patch:
https://sourceware.org/ml/gdb-patches/2015-11/msg00466.html

This patch removes support for thread events in GDB.

No regressions found on Ubuntu 14.04 x86_64.

gdb/ChangeLog:

* breakpoint.c (remove_thread_event_breakpoints): Remove.
* breakpoint.h (remove_thread_event_breakpoints): Remove
declaration.
* linux-nat.c (in_pid_list_p): Remove.
(lin_lwp_attach_lwp): Remove.
* linux-nat.h (lin_lwp_attach_lwp): Remove declaration.
* linux-thread-db.c (thread_db_use_events): Remove.
(struct thread_db_info) <td_create_bp_addr>: Remove.
<td_death_bp_addr>: Likewise.
<td_ta_event_addr_p>: Likewise.
<td_ta_set_event_p>: Likewise.
<td_ta_clear_event_p>: Likewise.
<td_ta_event_getmsg_p>: Likewise.
<td_thr_event_enable_p>: Likewise.
(attach_thread): Likewise.
(detach_thread): Likewise.
(have_threads_callback): Likewise.
(have_threads): Likewise.
(enable_thread_event): Likewise.
(enable_thread_event_reporting): Likewise.
(try_thread_db_load_1): Remove td_ta_event_addr, td_ta_set_event,
td_ta_clear_event, td_ta_event_getmsg, td_thr_event_enable
initializations.
(try_thread_db_load_1): Remove enable_thread_event_reporting call.
(disable_thread_event_reporting): Remove.
(record_thread): Adapt to thread_db_use_event removal.
(detach_thread): Remove.
(thread_db_detach): Adapt to thread_db_use_event removal.
(check_event): Remove.
(thread_db_wait): Adapt to thread events support removal.
(thread_db_mourn_inferior): Likewise.
(find_new_threads_callback): Likewise.
(find_new_threads_once): Likewise.
(thread_db_update_thread_list): Likewise.

8 years ago[AArch64][PATCH 2/2] Add RAS system registers.
Matthew Wahab [Thu, 10 Dec 2015 14:09:03 +0000 (14:09 +0000)]
[AArch64][PATCH 2/2] Add RAS system registers.

The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.

The new registers are:
    erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
    erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
    vdisr_el2.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/sysreg-2.d: Add tests for new registers.
* gas/aarch64/sysreg-2.s: Likewise.  Also replace some spaces with
tabs.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
(aarch64_sys_reg_supported_p): Add architecture feature tests for
new registers.

Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74

8 years ago[AArch64][PATCH 1/2] Add support for RAS instruction ESB.
Matthew Wahab [Thu, 10 Dec 2015 14:05:01 +0000 (14:05 +0000)]
[AArch64][PATCH 1/2] Add support for RAS instruction ESB.

The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.

This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.

Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64.h (AARCH64_FEATURE_RAS): New.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_feature_ras): New.
(RAS): New.
(aarch64_opcode_table): Add "esb".

Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf

8 years ago[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
Matthew Wahab [Thu, 10 Dec 2015 13:58:21 +0000 (13:58 +0000)]
[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.

ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.

This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.

include/opcode
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
AARCH64_FEATURE_V8_1.
(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
AARCH64_FEATURE_V8_1.

Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431

8 years ago[gdb/doc] Stack, Examining the Stack: Reorder menu
Pedro Alves [Thu, 10 Dec 2015 11:39:58 +0000 (11:39 +0000)]
[gdb/doc] Stack, Examining the Stack: Reorder menu

Commit fc58fa65d454 (gdb/doc: Restructure frame command documentation)
reordered the sections in the 'Examining the Stack' chapter, but
missed updating the menu:

src/gdb/doc/gdb.texinfo:6968: warning: node next `Backtrace' in menu `Frame Filter Management' and in sectioning `Selection' differ
src/gdb/doc/gdb.texinfo:7167: warning: node prev `Selection' in menu `Frame Filter Management' and in sectioning `Backtrace' differ
src/gdb/doc/gdb.texinfo:7252: warning: node `Frame Filter Management' is next for `Frame Info' in sectioning but not in menu
src/gdb/doc/gdb.texinfo:7317: warning: node `Selection' is next for `Frame Filter Management' in menu but not in sectioning
src/gdb/doc/gdb.texinfo:7317: warning: node prev `Frame Filter Management' in menu `Backtrace' and in sectioning `Frame Info' differ

gdb/doc/ChangeLog:
2015-12-10  Pedro Alves  <palves@redhat.com>

* gdb.texinfo (Stack): Reorder menu.

8 years agogdb: Handle multiple base address in debug_ranges data.
Andrew Burgess [Fri, 16 Oct 2015 08:08:19 +0000 (10:08 +0200)]
gdb: Handle multiple base address in debug_ranges data.

It is possible to use multiple base addresses within a single address
range series, within the .debug_ranges section.  The following is a
simplified example for 32-bit addresses:

  .section ".debug_ranges"
  .4byte 0xffffffff
  .4byte BASE_1
  .4byte START_OFFSET_1
  .4byte END_OFFSET_1
  .4byte START_OFFSET_2
  .4byte END_OFFSET_2
  .4byte 0xffffffff
  .4byte BASE_2
  .4byte START_OFFSET_3
  .4byte END_OFFSET_3
  .4byte 0
  .4byte 0

In this example START/END 1 and 2 are relative to BASE_1, while
START/END 3 are relative to BASE_2.

Currently gdb does not correctly parse this DWARF, resulting in
corrupted address range information.  This commit fixes this issue, and
adds a new test to cover this case.

In order to support testing of this feature extensions were made to the
testsuite dwarf assembler, additional functionality was added to the
.debug_line generation function, and a new function for generating the
.debug_ranges section was added.

gdb/ChangeLog:

* dwarf2read.c (dwarf2_ranges_read): Unify and fix base address
reading code.

gdb/testsuite/ChangeLog:

* gdb.dwarf2/dw2-ranges-base.c: New file.
* gdb.dwarf2/dw2-ranges-base.exp: New file.
* lib/dwarf.exp (namespace eval Dwarf): Add new variables to
support additional line table, and debug ranges generation.
(Dwarf::ranges): New function, generate .debug_ranges.
(Dwarf::lines): Support generating simple line table programs.
(Dwarf::assemble): Initialise new namespace variables.

8 years agoarc/gas: Accept, but ignore, dummy arguments.
Andrew Burgess [Wed, 9 Dec 2015 19:13:54 +0000 (19:13 +0000)]
arc/gas: Accept, but ignore, dummy arguments.

There's a set of legacy command line arguments that the arc assembler
still accepts, however, these arguments not longer have any effect on
the assembler.

Currently we return false from md_parse_option for all of these
arguments, with the result that the assembler terminates with an error
message.

We should return true indicating that the argument has been accepted,
even though we ignore it.

gas/ChangeLog:

* config/tc-arc.c (md_parse_option): Return 1 in order to accept
dummy arguments.

8 years agoFix GOT address computations in initial PLT entries for nios2.
Sandra Loosemore [Thu, 10 Dec 2015 00:13:58 +0000 (16:13 -0800)]
Fix GOT address computations in initial PLT entries for nios2.

2015-12-09  Sandra Loosemore  <sandra@codesourcery.com>

bfd/
* elf32-nios2.c (nios2_elf32_finish_dynamic_sections): Correct
%hiadj/%lo computations for _GLOBAL_OFFSET_TABLE_ in initial
PLT entries.  Assert alignment requirements.

8 years agoAutomatic date update in version.in
GDB Administrator [Thu, 10 Dec 2015 00:00:12 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agodwarf2loc.c: Perform a pointer to address conversion for DWARF_VALUE_MEMORY.
Kevin Buettner [Wed, 25 Nov 2015 04:53:13 +0000 (21:53 -0700)]
dwarf2loc.c: Perform a pointer to address conversion for DWARF_VALUE_MEMORY.

This patch fixes the following failures for rl78-elf:

FAIL: gdb.base/vla-datatypes.exp: print int_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_int_vla
FAIL: gdb.base/vla-datatypes.exp: print double_vla
FAIL: gdb.base/vla-datatypes.exp: print float_vla
FAIL: gdb.base/vla-datatypes.exp: print long_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_long_vla
FAIL: gdb.base/vla-datatypes.exp: print char_vla
FAIL: gdb.base/vla-datatypes.exp: print short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_char_vla
FAIL: gdb.base/vla-datatypes.exp: print foo_vla
FAIL: gdb.base/vla-datatypes.exp: print bar_vla
FAIL: gdb.base/vla-datatypes.exp: print vla_struct_object
FAIL: gdb.base/vla-datatypes.exp: print vla_union_object
FAIL: gdb.base/vla-ptr.exp: print td_vla
FAIL: gdb.mi/mi-vla-c99.exp: evaluate complete vla

The first failure in this bunch occurs due to printing an incorrect
result for a variable length array:

    print int_vla
    $1 = {-1, -1, -1, -1, -1}

The result should actually be this:

    $1 = {0, 2, 4, 6, 8}

When I started examining this bug, I found that printing an
individual array element worked correctly.  E.g. "print int_vla[2]"
resulted in 4 being printed.  I have not looked closely to see why
this is the case.

I found that evaluation of the location expression for int_vla was
causing problems.  This is the relevant DWARF entry for int_vla:

<2><15a>: Abbrev Number: 10 (DW_TAG_variable)
    <15b>   DW_AT_name        : (indirect string, offset: 0xbf): int_vla
    <15f>   DW_AT_decl_file   : 1
    <160>   DW_AT_decl_line   : 35
    <161>   DW_AT_type        : <0x393>
    <165>   DW_AT_location    : 4 byte block: 86 7a 94 2  (DW_OP_breg22 (r22): -6; DW_OP_deref_size: 2)

I found that DW_OP_breg22 was providing a correct result.
DW_OP_deref_size was fetching the correct value from memory.  However,
the value being fetched should be considered a pointer.
DW_OP_deref_size zero extends the fetched value prior to pushing
it onto the evaluation stack.  (The DWARF-4 document specifies this
action; so GDB is faithfully implementing the DWARF-4 specification.)

However, zero extending the pointer is not sufficient for converting
that value to an address for rl78 and (perhaps) other architectures
which define a `pointer_to_address' method.  (I suspect that m32c
would have the same problem.)

Ideally, we would perform the pointer to address conversion in
DW_OP_deref_size.  We don't, however, know the type of the object
that the address refers to in DW_OP_deref_size.  I can't think
of a way to infer the type at that point in the code.

Before proceeding, I should note that there are two other DWARF
operations that could be used in place of DW_OP_deref_size.  One of
these is DW_OP_GNU_deref_type.  Current GDB implements this operation,
but as is obvious from the name, it is non-standard DWARF.  The other
operation is DW_OP_xderef_size.  Even though it's part of DWARF-2
through DWARF-4 specifications, it's not presently implemented in GDB.
Present day GCC does not output dwarf expressions containing this
operation either.  [Of the two, I like DW_OP_GNU_deref_type better.
Using it avoids the need to specify an "address space identifier".
(GCC, GDB, and other non-free tools all need to agree on the meanings
of these identifiers.)]

Back to the bug analysis...

The closest consumer of the DW_OP_deref_size result is the
DWARF_VALUE_MEMORY case in dwarf2_evaluate_loc_desc_full.  At that
location, we do know the object type to which the address is intended
to refer.  I added code to perform a pointer to address conversion at
this location.  (See the patch.)

I do have some misgivings regarding this patch.  As noted earlier, it
would really be better to perform the pointer to address conversion in
DW_OP_deref_size.  I can't, however, think of a way to make this work.
Changing GCC to output one of the other aforementioned operations might
be preferable but, as noted earlier, these solutions have problems as
well.  Long term, I think it'd be good to have something like
DW_OP_GNU_deref_type become part of the standard.  If that can't or
won't happen, we'll need to implement DW_OP_xderef_size.

But until that happens, this patch will work for expressions in which
DW_OP_deref_size occurs last.  It should even work for dereferences
followed by adding an offset.  I don't think it'll work for more than
one dereference in the same expression.

gdb/ChangeLog:

* dwarf2loc.c (dwarf2_evaluate_loc_desc_full): Perform a pointer
to address conversion for DWARF_VALUE_MEMORY.

8 years agogdb.base/async.exp: Handle "asynchronous execution not supported"
Kevin Buettner [Tue, 8 Dec 2015 06:07:29 +0000 (23:07 -0700)]
gdb.base/async.exp: Handle "asynchronous execution not supported"

This change eliminates some failures on simulator targets and makes
the test run a bit quicker too - without this change, we have to wait
for timeouts.

gdb/testsuite/ChangeLog:

* gdb.base/async.exp (proc test_background): Add case
for asynchronous execution not supported.

8 years agoImplement Intel OSPKE instructions
H.J. Lu [Wed, 9 Dec 2015 16:01:57 +0000 (08:01 -0800)]
Implement Intel OSPKE instructions

This patch implements Intel OSPKE instructions documented in Intel64
and IA-32 Architectures Software Developer’s Manual Volume 2, September
2015.

gas/testsuite/

* gas/i386/i386.exp: Run ospke and x86-64-ospke.
* gas/i386/ospke.d: New file.
* gas/i386/ospke.s: Likewise.
* gas/i386/x86-64-ospke.d: Likewise.

opcodes/

* i386-dis.c (MOD_0F01_REG_5): New.
(RM_0F01_REG_5): Likewise.
(reg_table): Use MOD_0F01_REG_5.
(mod_table): Add MOD_0F01_REG_5.
(rm_table): Add RM_0F01_REG_5.
* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
(cpu_flags): Add CpuOSPKE.
* i386-opc.h (CpuOSPKE): New.
(i386_cpu_flags): Add cpuospke.
* i386-opc.tbl: Add rdpkru and wrpkru instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.

8 years agogas/ELF: slightly relax elf/file*.d expectations
Jan Beulich [Wed, 9 Dec 2015 13:35:07 +0000 (14:35 +0100)]
gas/ELF: slightly relax elf/file*.d expectations

Despite the re-ordering done for the file symbols, some targets manage
to put section symbols ahead of it.

8 years agovarobj zero-padded hexadecimal format
Luis Machado [Wed, 9 Dec 2015 12:56:27 +0000 (10:56 -0200)]
varobj zero-padded hexadecimal format

This set of patches add support for the zero-padded hexadecimal format for
varobj's, defined as "zero-hexadecimal".  We currently only support regular
non-zero-padded hexadecimal.

Talking with IDE developers, they would like to have this option that is
already available to GDB's print/x commands, in the CLI, as 'z'.

gdb/ChangeLog:

2015-12-09  Luis Machado  <lgustavo@codesourcery.com>

* gdb/mi/mi-cmd-var.c (mi_parse_format): Handle new "zero-hexadecimal"
format.
* gdb/varobj.c (varobj_format_string): Add "zero-hexadecimal" entry.
(format_code): Add 'z' entry.
(varobj_set_display_format): Handle FORMAT_ZHEXADECIMAL.
* gdb/varobj.h (varobj_display_formats) <FORMAT_ZHEXADECIMAL>: New enum
field.
* NEWS: Add new note to MI changes citing the new zero-hexadecimal
format for -var-set-format.

gdb/doc/ChangeLog:

2015-12-09  Luis Machado  <lgustavo@codesourcery.com>

* gdb.texinfo (GDB/MI Variable Objects): Update text to mention
-var-set-format's new zero-hexadecimal format.

gdb/testsuite/ChangeLog:

2015-12-09  Luis Machado  <lgustavo@codesourcery.com>

* gdb.mi/mi-var-display.exp: Add new checks for the zero-hexadecimal
  format and change test names to make them unique.

8 years agosparc: support %dN and %qN syntax for FP registers.
Jose E. Marchesi [Wed, 9 Dec 2015 12:32:52 +0000 (07:32 -0500)]
sparc: support %dN and %qN syntax for FP registers.

The SPARC Refence Manual documents the %dN and %qN syntax to
refer to double and quad-precision floating-point registers,
respectively.  See OSA2015 Appendix C, Assembly Language Syntax,
C1.1 Register Names.

This patch adds support for these names to GAS.  This eases the
porting of software from Solaris to GNU/Linux, as these register
names have been supported by the Solaris linker for a long time
and many assembler require that support.

gas/ChangeLog:

2015-12-09  Jose E. Marchesi  <jose.marchesi@oracle.com>

* config/tc-sparc.c (sparc_ip): Support %dN and %qN notation for
double and quad-precision floating-point registers.

8 years agoFix wrong output of x87 registers due to truncation to double on amd64
Ruslan Kabatsayev [Wed, 9 Dec 2015 12:17:40 +0000 (12:17 +0000)]
Fix wrong output of x87 registers due to truncation to double on amd64

When `info float` is used on an AMD64 system, GDB prints
floating-point values of x87 registers with raw contents like
0x361a867a8e0527397ce0 or 0xc4f988454a1ddd3cfdab wrongly.

This happens due to truncation to double, after which the former
becomes 0.0, and the latter becomes negative infinity.  This is caused
by failed detection of x86-64 host, which results in setting
gdb_host_{float,double,long_double}_format to zeros.

This commit fixes this misdetection, and adds a test to make sure
future commits don't introduce a regression here.

gdb/ChangeLog:
2015-12-09  Ruslan Kabatsayev  <b7.10110111@gmail.com>

PR gdb/18702
* configure.host: Fix detection of x86_64 host when setting
floatformats.

gdb/testsuite/ChangeLog:
2015-12-09  Ruslan Kabatsayev  <b7.10110111@gmail.com>
    Pedro Alves  <pedro@redhat.com>

PR gdb/18702
Add checking of floatformats setup on x86_64 hosts.
* gdb.arch/i386-float.S (main): Load bigval and smallval.
(smallval, bigval): New labels/constants.
* gdb.arch/i386-float.exp: Use with_test_prefix and test "info
float" after loading bigval and smallval.

8 years agoFix compile time warning building RX target.
Nick Clifton [Wed, 9 Dec 2015 12:01:19 +0000 (12:01 +0000)]
Fix compile time warning building RX target.

8 years ago[GOLD] PowerPC style fix
Alan Modra [Wed, 9 Dec 2015 00:00:18 +0000 (10:30 +1030)]
[GOLD] PowerPC style fix

* powerpc.cc (Target_powerpc::Relocate::relocate): New constant
d_offset.  Use throughout.
(Target_powerpc::relocate_relocs): Likewise.

8 years ago[GOLD] Edit PowerPC64 ELFv2 function entry code
Alan Modra [Tue, 8 Dec 2015 23:48:44 +0000 (10:18 +1030)]
[GOLD] Edit PowerPC64 ELFv2 function entry code

In an fixed position executable, the entry code does not need to be
PIC and can thus lose a dependency on r12.

* powerpc.cc (Target_powerpc::Relocate::relocate): Edit ELFv2
entry code.
(Target_powerpc::relocate_relocs): Edit relocs to suit.

8 years ago[GOLD] Relocate::relocate() params
Alan Modra [Tue, 8 Dec 2015 23:48:30 +0000 (10:18 +1030)]
[GOLD] Relocate::relocate() params

Some linker code editing needs to change multiple insns.  In some
cases multiple relocations are involved and it is not sufficient to
make the changes independently as relocations are processed, because
doing so might lead to a partial edit.  So in order to safely edit we
need all the relocations available in relocate().  Also, to emit
edited relocs corresponding to the edited code sequence we need some
way to pass information from relocate() to relocate_relocs(),
particularly if the edit depends on insns.  We can't modify input
relocs in relocate() as they are mmapped PROT_READ, nor it is
particularly clean to write relocs to the output at that stage.  So
add a Relocatable_relocs* field to relinfo to mark edited relocs.

Given that relocate is passed the raw reloc pointer, it makes sense to
remove the rel/rela parameter and r_type too.  However, that means the
mips relocate() needs to know whether SHT_REL or SHT_RELA relocs are
being processed.  So add a rel_type for mips, which also has the
benefit of removing relocate() overloading there.

This patch adds the infrastructure without making use of it.

Note that relinfo->rr will be NULL if not outputting relocations.

* object.h (struct Relocate_info): Add "rr".
* reloc.h (Relocatable_relocs::set_strategy): New accessor.
* reloc.cc (Sized_relobj_file::do_relocate_sections): Init
relinfo.rr for relocate_section and relocate_relocs.
* powerpc.cc (relocate): Add rel_type and preloc parameters.
Delete rela and r_type params, instead recalculate these from
preloc.
(relocate_relocs): Delete Relocatable_relocs* param, instead
use relinfo->rr.
* aarch64.cc: Likewise.
* arm.cc: Likewise.
* i386.cc: Likewise.
* mips.cc: Likewise.
* s390.cc: Likewise.
* sparc.cc: Likewise.
* target.h: Likewise.
* tilegx.cc: Likewise.
* x86_64.cc: Likewise.
* testsuite/testfile.cc: Likewise.
* target-reloc.h (relocate_section): Adjust to suit.
(apply_relocation, relocate_relocs): Likewise.

8 years agoAutomatic date update in version.in
GDB Administrator [Wed, 9 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agoFix static analysis warning about undefined bheaviour.
Nick Clifton [Tue, 8 Dec 2015 09:49:49 +0000 (09:49 +0000)]
Fix static analysis warning about undefined bheaviour.

PR binutils/19310
* dwarf.c (display_debug_frames): Recode range test to avoid
undefined behaviour.

8 years agogas: consistently emit diagnostics for non-zero data emission to .bss/.struct
Jan Beulich [Tue, 8 Dec 2015 09:14:49 +0000 (10:14 +0100)]
gas: consistently emit diagnostics for non-zero data emission to .bss/.struct

8 years agogas: don't get confused by .asci{i,z} after .struct
Jan Beulich [Tue, 8 Dec 2015 09:12:54 +0000 (10:12 +0100)]
gas: don't get confused by .asci{i,z} after .struct

While not allowed, this certainly shouldn't result in confusing the
programmer (by skipping lines in unexpected ways): Without returning,
demand_empty_rest_of_line() (at the end of the function) will demand
the _next_ line to be empty, and without the conditional we would
ignore the next line.

8 years agoELF: don't re-order SHF_FILE symbols
Jan Beulich [Tue, 8 Dec 2015 09:11:58 +0000 (10:11 +0100)]
ELF: don't re-order SHF_FILE symbols

.file directives may be used to identify the scope of local symbols,
the purpose of which gets subverted when re-ordering them. Only allow
the first of them to be moved to the first position.

8 years agoDOCO: Enhance the menu to select function overloads with signatures
Pierre-Marie de Rodat [Thu, 3 Sep 2015 15:34:58 +0000 (17:34 +0200)]
DOCO: Enhance the menu to select function overloads with signatures

gdb/ChangeLog:

* NEWS: Announce this enhancement and the corresponding new
option.

gdb/doc/ChangeLog:

* gdb.texinfo (Ada Mode Into): Move overloading support
description to its own node.
(Overloading support for Ada): New node.

8 years agorl78: relaxation fixes
DJ Delorie [Tue, 8 Dec 2015 06:29:25 +0000 (01:29 -0500)]
rl78: relaxation fixes

Various fixes to linker relaxation.  In general, we need to support
relaxing every branch, even if we don't relax it in the assembler,
so we can optionally defer relaxation to the linker.

* elf32-rl78.c (rl78_offset_for_reloc): Add more relocs.
(rl78_elf_relax_section): Add bc/bz/bnc/bnz/bh/bnh.  Fix reloc
choices.

* config/rl78-parse.y: Make all branches relaxable via
rl78_linkrelax_branch().
* config/tc-rl78.c (rl78_linkrelax_branch): Mark all relaxable
branches with relocs.
(options): Add OPTION_NORELAX.
(md_longopts): Add -mnorelax.
(md_parse_option): Support OPTION_NORELAX.
(op_type_T): Add bh, sk, call, and br.
(rl78_opcode_type): Likewise.
(rl78_relax_frag): Fix not-relaxing logic.  Add sk.
(md_convert_frag): Fix relocation handling.
(tc_gen_reloc): Strip relax relocs when not linker relaxing.
(md_apply_fix): Defer overflow handling for anything that needs a
PLT, to the linker.
* config/tc-rl78.h (TC_FORCE_RELOCATION): Force all relocations to
the linker when linker relaxing.
* doc/c-rl78.texi (norelax): Add.

8 years agorx: Fix p_vaddr reconstruction logic.
DJ Delorie [Tue, 8 Dec 2015 06:15:58 +0000 (01:15 -0500)]
rx: Fix p_vaddr reconstruction logic.

* elf32-rx.c (rx_elf_object_p): Ignore empty and nobits sections.

8 years agorl78: Enable MULU for all ISAs.
DJ Delorie [Tue, 8 Dec 2015 03:33:39 +0000 (22:33 -0500)]
rl78: Enable MULU for all ISAs.

Unlike other mul/div opcodes, MULU is available on all variants
of the RL78.

* rl78-decode.opc: Enable MULU for all ISAs.
* rl78-decode.c: Regenerate.

8 years agoAutomatic date update in version.in
GDB Administrator [Tue, 8 Dec 2015 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agold: relax alignment requirements of compressed .debug_* section checks
Jan Beulich [Mon, 7 Dec 2015 16:52:25 +0000 (17:52 +0100)]
ld: relax alignment requirements of compressed .debug_* section checks

This fixes a failure of the gabinormal linking test on some distros
(where e.g. crt1.o has a .debug_aranges section with larger alignment).

8 years agoSupport Z0 packet in AArch64 multi-arch debugging
Yao Qi [Mon, 7 Dec 2015 15:56:31 +0000 (15:56 +0000)]
Support Z0 packet in AArch64 multi-arch debugging

In commit 6085d6f6, Z0 packet is disabled in aarch64 GDBserver if
the inferior is 32-bit or there may be multiple inferiors, because
Z0 packet isn't supported for arm then.  Recently, Z0 packet
is supported in arm target, so we don't have such limitation in
aarch64 GDBserver, that is to say, aarch64 GDBserver can use Z0
packet in multi-arch/multi-inferior debugging when the inferior's
arch is arm.

Part of this patch is to revert 6085d6f6, and the rest of the patch
is to move some breakpoint related arm_* functions into
linux-aarch32-low.c in order to share them between arm and aarch64.

This patch is regression tested on aarch64-linux for debugging both
aarch64 programs and arm programs respectively.

gdb/gdbserver:

2015-12-07  Yao Qi  <yao.qi@linaro.org>

* configure.srv: Append arm.o to srv_tgtobj for
aarch64*-*-linux* target.
* linux-aarch32-low.c (arm_abi_breakpoint): New macro.  Moved
from linux-arm-low.c.
(arm_eabi_breakpoint, arm_breakpoint): Likewise.
(arm_breakpoint_len, thumb_breakpoint): Likewise.
(thumb_breakpoint_len, thumb2_breakpoint): Likewise.
(thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode, arm_breakpoint_at): Likewise.
(arm_breakpoint_kinds): Likewise.
(arm_breakpoint_kind_from_pc): Likewise.
(arm_sw_breakpoint_from_kind): Likewise.
(arm_breakpoint_kind_from_current_state): Likewise.
* linux-aarch32-low.h (arm_breakpoint_kind_from_pc): Declare.
(arm_sw_breakpoint_from_kind): Declare.
(arm_breakpoint_kind_from_current_state): Declare.
(arm_breakpoint_at): Declare.
* linux-aarch64-low.c (aarch64_sw_breakpoint_from_kind): Call
arm_sw_breakpoint_from_kind if process is 32-bit.
(aarch64_breakpoint_kind_from_pc): New function.
(aarch64_breakpoint_kind_from_current_state): New function.
(the_low_target): Initialize fields breakpoint_kind_from_pc
and breakpoint_kind_from_current_state.
* linux-arm-low.c (arm_breakpoint_kinds): Move to
linux-aarch32-low.c.
(arm_abi_breakpoint, arm_eabi_breakpoint): Likewise.
(arm_breakpoint, arm_breakpoint_len): Likewise.
(thumb_breakpoint, thumb_breakpoint_len): Likewise.
(thumb2_breakpoint, thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode): Likewise.
(arm_breakpoint_at): Likewise.
(arm_breakpoint_kind_from_pc): Likewise.
(arm_sw_breakpoint_from_kind): Likewise.
(arm_breakpoint_kind_from_current_state): Likewise.

Revert:
2015-08-04  Yao Qi  <yao.qi@linaro.org>

* linux-aarch64-low.c (aarch64_supports_z_point_type): Return
0 for Z_PACKET_SW_BP if it may be used in multi-arch debugging.
* server.c (extended_protocol): Remove "static".
* server.h (extended_protocol): Declare it.

8 years agooops - accidentally omittde from previous delta.
Nick Clifton [Mon, 7 Dec 2015 14:44:46 +0000 (14:44 +0000)]
oops - accidentally omittde from previous delta.

8 years agoFix relaxation in RX linker when --no-keep-memory is specified.
Nick Clifton [Mon, 7 Dec 2015 14:43:47 +0000 (14:43 +0000)]
Fix relaxation in RX linker when --no-keep-memory is specified.

* elf32-rx.c (elf32_rx_relax_delete_bytes): Add extra parameter -
the start of the relocs for the section.  Delete code to load in
the relocs.
(elf32_rx_relax_section): Do not free the loaded relocs.

8 years agoEnhance the menu to select function overloads with signatures
Pierre-Marie de Rodat [Thu, 3 Sep 2015 15:34:58 +0000 (17:34 +0200)]
Enhance the menu to select function overloads with signatures

So far, trying to evaluate an expression involving a function call for
which GDB could find multiple function candidates outputs a menu so that
the user can select the one to run.  For instance, with the two
following functions:

    type New_Integer is new Integer;

    function F (I : Integer) return Boolean;
    function F (I : New_Integer) return Boolean;

Then we get the following GDB session:

    (gdb) print f(1)
    Multiple matches for f
    [0] cancel
    [1] foo.f at foo.adb:23
    [2] foo.f at foo.adb.28
    >

While the source location information is sufficient in order to
determine which one to select, one has to look for them in source files,
which is not convenient.

This commit tunes this menu in order to also include the list of formal
and return types (if any) in each entry.  The above then becomes:

    (gdb) print f(1)
    Multiple matches for f
    [0] cancel
    [1] foo.f (integer) return boolean at foo.adb:23
    [2] foo.f (foo.new_integer) return boolean at foo.adb.28
    >

Since this output is more verbose than previously, this change also
introduces an option (set/show ada print-signatures) to get the original
output.

gdb/ChangeLog:

* ada-lang.c (print_signatures): New.
(ada_print_symbol_signature): New.
(user_select_syms): Add signatures to the output of candidate
symbols using ada_print_symbol_signature.
(_initialize_ada_language): Add a "set/show ada
print-signatures" boolean option.

gdb/testsuite/ChangeLog:

* gdb.ada/fun_overload_menu.exp: New testcase.
* gdb.ada/fun_overload_menu/foo.adb: New testcase.

Tested on x86_64-linux, no regression.

8 years agoAdd myself as a write-after-approval GDB maintainer
Andreas Arnez [Mon, 7 Dec 2015 09:43:39 +0000 (10:43 +0100)]
Add myself as a write-after-approval GDB maintainer

gdb/ChangeLog:

* MAINTAINERS (Write After Approval): Add Andreas Arnez.

8 years agoAdd support for MSP430 F5 hardware multiply.
Nick Clifton [Mon, 7 Dec 2015 10:19:19 +0000 (10:19 +0000)]
Add support for MSP430 F5 hardware multiply.

* msp430-sim.c (sim_open): Check for needed memory at address
0x500 not 0x200.
(get_op): Add support for F5 hardware multiply addresses.
(put_op): Likewise.

8 years agoPowerPC ifunc with local symbols
Alan Modra [Mon, 7 Dec 2015 03:22:01 +0000 (13:52 +1030)]
PowerPC ifunc with local symbols

This fixes some cases where the linker would incorrectly error on plt
relocs to local ifunc symbols.  I've also tidied plt and ifunc
handling for ppc64, where check_relocs was allowing for the
possibility of plt calls via addr14/addr24 relocs but relocate_section
was not.

* elf32-ppc.c (ppc_elf_check_relocs): Don't error on local ifunc
plt call.  Wrap long lines.
(ppc_elf_relocate_section): Wrap long lines.
* elf64-ppc.c (ppc64_elf_check_relocs): Don't error on local ifunc
plt calls.  Move __tls_get_addr checks later.  Don't create plt
for addr14/addr24 relocs.
(ppc64_elf_gc_sweep_hook): Adjust to suit check_relocs changes.
(ppc64_elf_relocate_section): Correct local ifunc handling for
PLT64, PLT32 and PLT16 relocs.

8 years agoPR19323 memory allocation greater than 4G
Alan Modra [Mon, 7 Dec 2015 03:11:36 +0000 (13:41 +1030)]
PR19323 memory allocation greater than 4G

On 32-bit targets, memory requested for program/section headers on a
fuzzed binary can wrap to 0.  A bfd_alloc of zero bytes actually
returns a one byte allocation rather than a NULL pointer.  This then
leads to buffer overflows.

Making this check unconditional triggers an extremely annoying gcc-5
warning.

PR19323
* elfcode.h (elf_object_p): Check for ridiculous e_shnum and
e_phnum values.

8 years ago[GOLD] R_PPC64_ENTRY support
Alan Modra [Mon, 7 Dec 2015 02:45:24 +0000 (13:15 +1030)]
[GOLD] R_PPC64_ENTRY support

elfcpp/
* powerpc.h (R_PPC64_ENTRY): Define.
gold/
* powerpc.cc (add_2_2_12, ld_2_12, lis_2): Define.
(Target_powerpc::Scan::local, global): Handle R_PPC64_ENTRY.
(Target_powerpc::Relocate::relocate): Edit code at R_PPC64_ENTRY.

8 years agoR_PPC64_ENTRY
Alan Modra [Mon, 7 Dec 2015 02:44:53 +0000 (13:14 +1030)]
R_PPC64_ENTRY

Add a new relocation that marks large-model entry code, for edit back
to medium-model.

include/elf/
* ppc64.h (R_PPC64_ENTRY): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_ENTRY): New.
* elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add
entry for R_PPC64_ENTRY.
(LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define.
(ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY.
(ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY.  Use
new insn defines.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.

8 years agotc-ppc.c md_apply_fix tidy
Alan Modra [Mon, 7 Dec 2015 02:44:35 +0000 (13:14 +1030)]
tc-ppc.c md_apply_fix tidy

* config/tc-ppc.c (md_apply_fix): Localize variables.  Reduce casts.

8 years agoReorder some power9 insns
Alan Modra [Mon, 7 Dec 2015 02:44:05 +0000 (13:14 +1030)]
Reorder some power9 insns

The idea being to put instructions that have the same encoding adjacent
to each other.

* opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
major opcode/xop.

8 years agobfd: Mark sh5*-*-* and sh64*-*-* targets as obsolete.
Kaz Kojima [Mon, 7 Dec 2015 00:58:37 +0000 (09:58 +0900)]
bfd: Mark sh5*-*-* and sh64*-*-* targets as obsolete.

8 years agoAutomatic date update in version.in
GDB Administrator [Mon, 7 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agoReplace remaining references to i386-nat with x86-nat instead.
Joel Brobecker [Sun, 6 Dec 2015 17:38:24 +0000 (18:38 +0100)]
Replace remaining references to i386-nat with x86-nat instead.

i386-nat.[hc] got renamed to x86-nat.[hc] a while back, but somehow
3 references to the old file name remained past the renaming. This
fixes all of them.

gdb/ChangeLog (with Mike Stump <mikestump@comcast.net>):

        * Makefile.in (TAGS): Replace i386-nat.h by x86-nat.h.
        * x86-nat.c: Replace remaining references to i386-nat
        by reference to x86-nat instead.

8 years agoAutomatic date update in version.in
GDB Administrator [Sun, 6 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agoDocument the GDB 7.10.1 release in gdb/ChangeLog
Joel Brobecker [Sat, 5 Dec 2015 15:29:09 +0000 (16:29 +0100)]
Document the GDB 7.10.1 release in gdb/ChangeLog

gdb/ChangeLog:

GDB 7.10.1 released.

8 years agogdbserver: set ptrace flags after creating inferiors
Josh Stone [Fri, 4 Dec 2015 21:28:07 +0000 (13:28 -0800)]
gdbserver: set ptrace flags after creating inferiors

Rename target_ops.arch_setup to .post_create_inferior.  In the Linux
hook, continue calling the low arch setup, then also set ptrace flags.
This corrects the possibility of running without flags, demonstrated by
a new test that would fail to catch a fork before.

gdb/gdbserver/ChangeLog:

2015-12-04  Josh Stone  <jistone@redhat.com>

* target.h (struct target_ops) <arch_setup>: Rename to ...
(struct target_ops) <post_create_inferior>: ... this.
(target_arch_setup): Rename to ...
(target_post_create_inferior): ... this, calling post_create_inferior.
* server.c (start_inferior): Update target_arch_setup calls to
target_post_create_inferior.
* linux-low.c (linux_low_ptrace_options): Forward declare.
(linux_arch_setup): Update its comment for general use.
(linux_post_create_inferior): New, run arch_setup and setup ptrace.
(struct linux_target_ops): Use linux_post_create_inferior.
* lynx-low.c (struct lynx_target_ops): Update arch_setup stub comment
to post_create_inferior.
* nto-low.c (struct nto_target_ops): Likewise.
* spu-low.c (struct spu_target_ops): Likewise.
* win32-low.c (struct win32_target_ops): Likewise.

gdb/testsuite/ChangeLog:

2015-12-04  Josh Stone  <jistone@redhat.com>

* gdb.base/catch-fork-static.exp: New.

8 years agoAutomatic date update in version.in
GDB Administrator [Sat, 5 Dec 2015 00:00:07 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agoOptimize R_386_GOT32/R_386_GOT32X only if addend is 0
H.J. Lu [Fri, 4 Dec 2015 16:43:45 +0000 (08:43 -0800)]
Optimize R_386_GOT32/R_386_GOT32X only if addend is 0

Linker can't optimize R_386_GOT32 and R_386_GOT32X relocations if addend
isn't 0.  It isn't valid to convert

movl foo@GOT+1(%ecx), %eax

to

leal foo@GOTOFF+1(%ecx), %eax

nor to convert

movq foo@GOTPCREL+1(%rip), %rax

to

leaq foo(%rip), %rax

for x86-64.  We should check if addend is 0 before optimizing R_386_GOT32
and R_386_GOT32X relocations.  Testcases are added for i386 and x86-64.

bfd/

* elf32-i386.c (elf_i386_convert_load): Skip if addend isn't 0.
(elf_i386_relocate_section): Skip R_386_GOT32X optimization if
addend isn't 0.

ld/testsuite/

* ld-i386/i386.exp: Run mov2a, mov2b and mov3.
* ld-i386/mov2.s: New file.
* ld-i386/mov2a.d: Likewise.
* ld-i386/mov2b.d: Likewise.
* ld-i386/mov3.d: Likewise.
* ld-i386/mov3.s: Likewise.
* ld-x86-64/mov2.s: Likewise.
* ld-x86-64/mov2a.d: Likewise.
* ld-x86-64/mov2b.d: Likewise.
* ld-x86-64/mov2c.d: Likewise.
* ld-x86-64/mov2d.d: Likewise.
* ld-x86-64/x86-64.exp: Run mov2a, mov2b, mov2c and mov2d.

8 years agoFix GAS testsuite failures for COFF/PE based ARM targets.
Nick Clifton [Fri, 4 Dec 2015 15:07:10 +0000 (15:07 +0000)]
Fix GAS testsuite failures for COFF/PE based ARM targets.

PR gas/19276
gas * config/tc-arm.h (SUB_SEGMENT_ALIGN): Do not define for COFF/PE
targets.

testsuite * gas/arm/align64.d: Skip for COFF/PE targets.
* gas/arm/bundle-lock.d: Adjust for COFF/PE targets.

8 years agoRemove useless loop in elf.c
Tristan Gingold [Thu, 3 Dec 2015 10:57:29 +0000 (11:57 +0100)]
Remove useless loop in elf.c

8 years agoFix failures in the GAS testsuite for the ARC architecture.
Claudiu Zissulescu [Fri, 4 Dec 2015 10:49:57 +0000 (10:49 +0000)]
Fix failures in the GAS testsuite for the ARC architecture.

gas * config/tc-arc.c (arc_option): Sets all internal gas options when
parsing .cpu directive.
(declare_register_set): Declare all 64 registers.
(md_section_align): Refactor.
(md_pcrel_from_section): Remove assert.
(pseudo_operand_match): Fix pseudo operand match.
(find_reloc): Use flags filed, extend matching.
* config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
relocation.

testsuite * gas/arc/bic.d: Update test.
* gas/arc/add_s-err.s: New file.
* gas/arc/cpu-warn1.s: Likewise.
* gas/arc/pcl-relocs.d: Likewise.
* gas/arc/pcl-relocs.s: Likewise.
* gas/arc/pcrel-relocs.d: Likewise.
* gas/arc/pcrel-relocs.s: Likewise.
* gas/arc/pic-relocs.d: Likewise.
* gas/arc/pic-relocs.s: Likewise.
* gas/arc/plt-relocs.d: Likewise.
* gas/arc/plt-relocs.s: Likewise.
* gas/arc/pseudos.d: Likewise.
* gas/arc/pseudos.s: Likewise.
* gas/arc/sda-relocs.d: Likewise.
* gas/arc/sda-relocs.s: Likewise.
* gas/arc/sda-relocs2.d: Likewise.
* gas/arc/sda-relocs2.s: Likewise.
* gas/arc/tls-relocs.d: Likewise.
* gas/arc/tls-relocs.s: Likewise.

opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].

opcodes * arc-dis.c (special_flag_p): Match full mnemonic.
* arc-opc.c (print_insn_arc): Check section size to read
appropriate number of bytes. Fix printing.
* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
arguments.

8 years agoAutomatic date update in version.in
GDB Administrator [Fri, 4 Dec 2015 00:00:12 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agoTake addend into account when making GOT entries for local symbols.
Vladimir Radosavljevic [Thu, 3 Dec 2015 23:29:17 +0000 (15:29 -0800)]
Take addend into account when making GOT entries for local symbols.

gold/
* object.cc (Sized_relobj::do_for_all_local_got_entries): Use
Local_got_entry_key for searching in local_got_offsets_.
* object.h (class Local_got_entry_key): New class.
(Relobj::local_has_got_offset): New overloaded method.
(Relobj::local_got_offset): Likewise.
(Relobj::set_local_got_offset): Likewise.
(Relobj::do_local_has_got_offset): Add addend argument.
(Relobj::do_local_got_offset): Likewise.
(Relobj::do_set_local_got_offset): Likewise.
(Sized_relobj::do_local_has_got_offset): Add addend argument, and use
Local_got_entry_key for searching through local_got_offsets_.
(Sized_relobj::do_local_got_offset): Likewise.
(Sized_relobj::do_set_local_got_offset): Likewise.
(Sized_relobj::Local_got_offsets): Change type of the key from
unsigned int to Local_got_entry_key, and add hash and equal_to.
* output.cc (Got_entry::write): Take addend into account for
calculating value of the local symbol for GOT.
(Output_data_got::add_local): New definition of overloaded method.
(Output_data_got::add_local_with_rel): Likewise.
(Output_data_got::add_local_pair_with_rel): Likewise.
* output.h (Output_data_got::add_local): New declaration of overloaded
method.

8 years agoRemove duplicate arch/arm.h include in linux-arm-low.c.
Antoine Tremblay [Thu, 3 Dec 2015 18:56:37 +0000 (13:56 -0500)]
Remove duplicate arch/arm.h include in linux-arm-low.c.

A duplicate include arm/arm.h was introduced, remove it.
Pushed as obvious.

gdb/gdbserver/ChangeLog:

* linux-arm-low.c: Remove duplicate arch/arm.h include.

8 years agoRun gdb.base/sizeof.exp with board having gdb,noinferiorio
Yao Qi [Thu, 3 Dec 2015 17:12:41 +0000 (17:12 +0000)]
Run gdb.base/sizeof.exp with board having gdb,noinferiorio

In my remote cross testing (x86_64 host and aarch64 target), the test
gdb.base/sizeof.exp is skipped because gdb,noinferiorio is defined in
my gdbserver board file.  Tests are skipped because the test checks
the expected value from the program's output, but I don't see why must
do it this way.  With my patch applied, we can save the result in variable
in the program, and check the variable then.  Then, the test doesn't rely
on inferiorio.

gdb/testsuite:

2015-12-03  Yao Qi  <yao.qi@linaro.org>

* gdb.base/sizeof.c: Don't include stdio.h and
../lib/unbuffer_output.c.
(main): New variable 'size' and 'value'.  Remove printf and
gdb_unbuffer_output.  Assign return value to size and value.
* gdb.base/sizeof.exp: Remove the checking to gdb,noinferiorio
at the beginning.
(check_sizeof): Check the result by printing variable 'size'.
(check_valueof): Check the result by printing variable 'value'.

8 years agoDarwin: add new mach-o header flags.
Tristan Gingold [Thu, 3 Dec 2015 10:56:09 +0000 (11:56 +0100)]
Darwin: add new mach-o header flags.

binutils/
* od-macho.c (bfd_mach_o_header_flags_name): Add name
for flags until BFD_MACH_O_MH_APP_EXTENSION_SAFE.

include/mach-o/
* loader.h (bfd_mach_o_header_flags): Add
BFD_MACH_O_MH_APP_EXTENSION_SAFE.

8 years agoAutomatic date update in version.in
GDB Administrator [Thu, 3 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agoaddr2line vs. inlined C functions called from C++
Alan Modra [Wed, 2 Dec 2015 05:16:48 +0000 (15:46 +1030)]
addr2line vs. inlined C functions called from C++

In this case the inlined function doesn't have DW_AT_linkage_name in
.debug_info, but the language is C++ so find_nearest_line goes looking
in the symbol table.  Since the function is inlined the enclosing
non-inline function symbol is returned from _bfd_elf_find_function,
which is wrong.  This patch only uses a symbol if its address matches.

PR binutils/19315
* dwarf2.c (_bfd_elf_find_function): Return symbol matched.
(_bfd_dwarf2_find_nearest_line): Check symbol returned above
against dwarf range.
* elf-bfd.h (_bfd_elf_find_function): Update prototype.

8 years agoMake --enable-initfini-array the default
Alan Modra [Wed, 2 Dec 2015 08:53:41 +0000 (19:23 +1030)]
Make --enable-initfini-array the default

* configure.ac (--enable-initfini-array): Remove run test.  Default
to "yes".  Change help string to --disable-initfini-array.
* configure: Regenerate.

8 years agoFix powerpc64 segfault caused by zero r_symndx relocs.
Alan Modra [Wed, 2 Dec 2015 08:19:53 +0000 (18:49 +1030)]
Fix powerpc64 segfault caused by zero r_symndx relocs.

Fixes a segfault in ppc64_elf_tls_optimize found when testing
R_PPC64_ENTRY, and potential for trouble in other places found by
code inspection.

* elf64-ppc.c (ppc64_elf_tls_optimize): Don't segfault on NULL
symbol section or output section.
(ppc64_elf_edit_toc): Similarly for ld -R objects.
(ppc64_elf_size_stubs): Likewise.

8 years agoFix ldah being disassembled as ldaexh
Andre Vieira [Wed, 25 Nov 2015 13:56:55 +0000 (13:56 +0000)]
Fix ldah being disassembled as ldaexh

2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>

opcodes/
    * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
    <ldah>: ... to this.

gas/testsuite/
    * gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ...
    <ldah>: ... to this.

8 years agoAutomatic date update in version.in
GDB Administrator [Wed, 2 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in

8 years agoProperly check symbol defined by assignment in linker script
H.J. Lu [Tue, 1 Dec 2015 22:45:51 +0000 (14:45 -0800)]
Properly check symbol defined by assignment in linker script

Symbol defined by a linker assignment may have type bfd_link_hash_new
or bfd_link_hash_undefined.  And h->def_regular is always set.
elf_i386_convert_load and elf_x86_64_convert_load should check
h->def_regular as well as bfd_link_hash_undefined and bfd_link_hash_new
to see if a symbol is defined by a linker script.

bfd/

PR ld/19319
* elf32-i386.c (elf_i386_convert_load): Check h->def_regular
instead of bfd_link_hash_new.
* elf64-x86-64.c (elf_x86_64_convert_load): Likewise.  Skip
relocation overflow for bfd_link_hash_undefined and
bfd_link_hash_new if h->def_regular is set.

ld/testsuite/

PR ld/19319
* ld-i386/i386.exp: Run pr19319 test.
* ld-x86-64/x86-64.exp: Likewise.
* ld-i386/pr19319.dd: New file.
* ld-i386/pr19319a.S: Likewise.
* ld-i386/pr19319b.S: Likewise.
* ld-x86-64/pr19319.dd: Likewise.
* ld-x86-64/pr19319a.S: Likewise.
* ld-x86-64/pr19319b.S: Likewise.

8 years agoAvoid "operation may be undefined" warning in remote.c
Ulrich Weigand [Tue, 1 Dec 2015 17:04:39 +0000 (18:04 +0100)]
Avoid "operation may be undefined" warning in remote.c

GCC 4.1 gives the following warning:
gdb/remote.c: In function 'remote_parse_stop_reply':
gdb/remote.c:6549: warning: operation on 'p' may be undefined
on this line of code:

event->ptid = read_ptid (++p, &p);

Since p actually isn't used afterwards anyway, simply use NULL.

gdb/
* remote.c (remote_parse_stop_reply): Avoid GCC 4.1 "operation
may be undefined" warning.

8 years agoFix uninitialized variable warnings in remote.c
Ulrich Weigand [Tue, 1 Dec 2015 16:49:27 +0000 (17:49 +0100)]
Fix uninitialized variable warnings in remote.c

Fix a couple of places where a struct thread_item was added to a
vector while the item.name field was uninitialized.

gdb/
* remote.c (remote_newthread_step): Initialize item.name.
(remote_get_threads_with_qthreadinfo): Likewise.

8 years agoRun gdb.base/disp-step-syscall.exp for aarch64-linux
Yao Qi [Tue, 1 Dec 2015 12:37:04 +0000 (12:37 +0000)]
Run gdb.base/disp-step-syscall.exp for aarch64-linux

This patch handles target aarch64*-*-linux* for syscall instruction.

gdb/testsuite:

2015-12-01  Yao Qi  <yao.qi@linaro.org>

* gdb.base/disp-step-syscall.exp: Define syscall instruction
for aarch64*-*-linux* target.

8 years agoTrim unused params from aout adjust_sizes_and_vmas
Alan Modra [Tue, 1 Dec 2015 03:26:09 +0000 (13:56 +1030)]
Trim unused params from aout adjust_sizes_and_vmas

* aoutx.h (adjust_sizes_and_vmas): Remove unused text_size and
text_end parameters.  Update callers.
* aout-tic30.c: Update adjust_sizes_and_vmas callers.
* hp300hpux.c: Likewise.
* i386lynx.c: Likewise.
* libaout.h: Likewise.
* netbsd.h: Likewise.
* pdp11.c: Likewise.
* riscix.c: Likewise.

8 years agoInvoke aout N_* macros with pointer to struct internal_exec
Alan Modra [Tue, 1 Dec 2015 01:10:52 +0000 (11:40 +1030)]
Invoke aout N_* macros with pointer to struct internal_exec

No functional changes here.

BTW, some of these headers don't seem to be used anywhere:
include/aout/dynix3.h, include/aout/encap.h, include/aout/hp.h,
gas/config/aout_gnu.h

bfd/
* aout-adobe.c: Invoke aout N_* macros with pointer to
struct internal_exec.
* aout-arm.c: Likewise.
* aout-cris.c: Likewise.
* aout-target.h: Likewise.
* aout-tic30.c: Likewise.
* aoutf1.h: Likewise.
* aoutx.h: Likewise.
* bout.c: Likewise.
* freebsd.h: Likewise.
* gen-aout.c: Likewise.
* hp300hpux.c: Likewise.
* i386aout.c: Likewise.
* i386linux.c: Likewise.
* i386lynx.c: Likewise.
* i386mach3.c: Likewise.
* i386os9k.c: Likewise.
* libaout.h: Likewise.
* m68klinux.c: Likewise.
* m88kmach3.c: Likewise.
* mipsbsd.c: Likewise.
* netbsd.h: Likewise.
* pc532-mach.c: Likewise.
* pdp11.c: Likewise.
* riscix.c: Likewise.
* sparclinux.c: Likewise.
* sparclynx.c: Likewise.
gas/
* config/aout_gnu.h: Invoke aout N_* macros with pointer to
struct internal_exec.
include/
* bout.h: Invoke aout N_* macros with pointer to
struct internal_exec.
* os9k.h: Likewise.
include/aout/
* adobe.h: Invoke aout N_* macros with pointer to
struct internal_exec.
* aout64.h: Likewise.
* dynix3.h: Likewise.
* encap.h: Likewise.
* hp.h: Likewise.
* hp300hpux.h: Likewise.
* sun4.h: Likewise.

8 years agoDon't use BFD_TRADITIONAL_FORMAT flag in COFF support
Alan Modra [Tue, 1 Dec 2015 01:10:25 +0000 (11:40 +1030)]
Don't use BFD_TRADITIONAL_FORMAT flag in COFF support

info->traditional_format is available, or can be easily made
available.  This relegates BFD_TRADITIONAL_FORMAT to AOUT use only.

* coff-rs6000.c (_bfd_xcoff_put_symbol_name): Replace abfd param
with info param.  Test info->traditional_format rather than
BFD_TRADITIONAL_FORMAT flag.
* coff64-rs6000.c (_bfd_xcoff64_put_symbol_name): Likewise.
* libxcoff.h (struct xcoff_backend_data_rec): Update
_xcoff_put_symbol_name prototype.
(bfd_xcoff_put_symbol_name): Add info param.
* xcofflink.c (xcoff_find_tc0): Update bfd_xcoff_put_symbol_name call.
(xcoff_write_global_symbol): Likewise.
(xcoff_link_input_bfd): Test info->traditional_format rather than
BFD_TRADITIONAL_FORMAT flag.
* cofflink.c (_bfd_coff_final_link): Likewise.
(_bfd_coff_link_input_bfd, _bfd_coff_write_global_sym): Likewise.

8 years agobinutils/configure update
Alan Modra [Tue, 1 Dec 2015 01:10:02 +0000 (11:40 +1030)]
binutils/configure update

Missed from f8c2a965.

* configure: Regenerate.

8 years agoSRC-POTFILES.in update
Alan Modra [Tue, 1 Dec 2015 01:09:37 +0000 (11:39 +1030)]
SRC-POTFILES.in update

* po/SRC-POTFILES.in: Regenerate.

8 years agoRe: ARC port broken reloc processing
Alan Modra [Tue, 1 Dec 2015 03:06:30 +0000 (13:36 +1030)]
Re: ARC port broken reloc processing

* elf32-arc.c (ARC_ELF_HOWTO): Delete.
(arc_elf_howto): New function.
(bfd_elf32_bfd_reloc_type_lookup): Use it in place of existing
init code.
(bfd_elf32_bfd_reloc_name_lookup): Use arc_elf_howto.
(arc_info_to_howto_rel, elf_arc_relocate_section): Likwise.
(elf_arc_check_relocs): Likewise.

8 years agoARC port broken reloc processing
Alan Modra [Tue, 1 Dec 2015 00:40:23 +0000 (11:10 +1030)]
ARC port broken reloc processing

This initialises howto.dst_mask so that relocations in debug sections
are applied by the generic reloc processing used by objdump to display
debug sections.

* elf32-arc.c (arc_elf_howto_init): Init dst_mask.