Ian Lance Taylor [Thu, 13 Jul 2017 03:44:14 +0000 (03:44 +0000)]
re PR go/81393 (Bootstrap failure on s390x-linux while building libgo against recent glibc)
PR go/81393
syscall: don't use GETREGS/SETREGS on s390
They were removed in recent glibc.
Patch by Andreas Krebbel for GCC PR 81393.
Reviewed-on: https://go-review.googlesource.com/48231
From-SVN: r250174
GCC Administrator [Thu, 13 Jul 2017 00:16:24 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250173
Michael Meissner [Wed, 12 Jul 2017 23:07:50 +0000 (23:07 +0000)]
re PR target/81193 (PowerPC GCC __builtin_cpu_is and __builtin_cpu_supports should warn about old libraries)
[gcc]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If GLIBC
provides the hardware capability bits, define the macro
__BUILTIN_CPU_SUPPORTS__.
* config/rs6000/rs6000.c (cpu_expand_builtin): Generate a warning
if GLIBC does not provide the hardware capability bits. Add a
gcc_unreachable call if the built-in cpu function is neither
__builtin_cpu_is nor __builtin_cpu_supports.
(rs6000_get_function_versions_dispatcher): Change the warning
that an old GLIBC is used which does not export the capability
bits to be an error.
* doc/extend.texi (target_clones attribute): Document the
restriction that GLIBC 2.23 or newer is needed on the PowerPC.
(PowerPC built-in functions): Document that GLIBC 2.23 or newer is
needed by __builtin_cpu_is and __builtin_cpu_supports. Document
the macros defined by GCC if the newer GLIBC is available.
[gcc/testsuite]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* gcc.target/powerpc/bmi-andn-1.c: Add guard against using
__builtin_cpu_supports with old GLIBC's.
* gcc.target/powerpc/bmi-andn-2.c: Likewise.
* gcc.target/powerpc/bmi-bextr-1.c: Likewise.
* gcc.target/powerpc/bmi-bextr-2.c: Likewise.
* gcc.target/powerpc/bmi-bextr-4.c: Likewise.
* gcc.target/powerpc/bmi-bextr-5.c: Likewise.
* gcc.target/powerpc/bmi-blsi-1.c: Likewise.
* gcc.target/powerpc/bmi-blsi-2.c: Likewise.
* gcc.target/powerpc/bmi-blsmsk-1.c: Likewise.
* gcc.target/powerpc/bmi-blsmsk-2.c: Likewise.
* gcc.target/powerpc/bmi-blsr-1.c: Likewise.
* gcc.target/powerpc/bmi-blsr-2.c: Likewise.
* gcc.target/powerpc/bmi-tzcnt-1.c: Likewise.
* gcc.target/powerpc/bmi-tzcnt-2.c: Likewise.
* gcc.target/powerpc/bmi2-bzhi32-1.c: Likewise.
* gcc.target/powerpc/bmi2-bzhi64-1.c: Likewise.
* gcc.target/powerpc/bmi2-mulx32-1.c: Likewise.
* gcc.target/powerpc/bmi2-mulx32-2.c: Likewise.
* gcc.target/powerpc/bmi2-mulx64-1.c: Likewise.
* gcc.target/powerpc/bmi2-mulx64-2.c: Likewise.
* gcc.target/powerpc/bmi2-pdep32-1.c: Likewise.
* gcc.target/powerpc/bmi2-pdep64-1.c: Likewise.
* gcc.target/powerpc/bmi2-pext32-1.c: Likewise.
* gcc.target/powerpc/bmi2-pext64-1.c: Likewise.
* gcc.target/powerpc/cpu-builtin-1.c: Likewise.
[libgcc]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* configure.ac (PowerPC float128 hardware support): Test whether
we can use __builtin_cpu_supports before enabling the ifunc
handler.
* configure: Regenerate.
From-SVN: r250165
Jeff Law [Wed, 12 Jul 2017 21:43:40 +0000 (15:43 -0600)]
riscv.c: Remove unnecessary includes.
* config/riscv/riscv.c: Remove unnecessary includes. Reorder
remaining includes slightly.
* config/riscv/riscv-builtins.c: Include profile-count.h.
From-SVN: r250162
Nathan Sidwell [Wed, 12 Jul 2017 19:46:33 +0000 (19:46 +0000)]
libcp1plugin.cc (plugin_build_decl): Use DECL_CXX_{CON,DE}STRUCTOR directly.
* libcp1plugin.cc (plugin_build_decl): Use
DECL_CXX_{CON,DE}STRUCTOR directly.
From-SVN: r250159
Nathan Sidwell [Wed, 12 Jul 2017 17:29:11 +0000 (17:29 +0000)]
cp-tree.h (DECL_CONSTRUCTOR_P, [...]): Look at identifier flags.
* cp-tree.h (DECL_CONSTRUCTOR_P, DECL_MAYBE_IN_CHARGE_CONSTRUCTOR,
DECL_DESTRUCTOR_P, DECL_MAYBE_IN_CHARGE_DESTRCTOR): Look at
identifier flags.
* decl.c (grokfndecl): Set DECL_CXX_CONSTRUCTOR and
DECL_CXX_DESTRUCTOR explicitly.
* decl2.c (grokclassfn): Likewise.
* friend.c (do_friend): Likewise.
* method.c (make_thunk, make_alias_for,
implicitly_declare_fn): Likewise.
From-SVN: r250158
Georg-Johann Lay [Wed, 12 Jul 2017 15:25:07 +0000 (15:25 +0000)]
re PR target/79883 (avr i18n: untranslated "interrupt" or "signal")
PR target/79883
* config/avr/avr.c (avr_set_current_function): In diagnostic
messages: Quote keywords and (parts of) identifiers.
[WITH_AVRLIBC]: Warn for functions named "ISR", "SIGNAL" or
"INTERUPT".
From-SVN: r250156
Carl Love [Wed, 12 Jul 2017 15:10:21 +0000 (15:10 +0000)]
rs6000-c.c: Add support for built-in functions vector bool char vec_revb (vector bool char)...
gcc/ChangeLog:
2017-07-12 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector bool char vec_revb (vector bool char);
vector bool short vec_revb (vector short char);
vector bool int vec_revb (vector bool int);
vector bool long long vec_revb (vector bool long long);
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
gcc/testsuite/ChangeLog:
2017-07-12 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/p9-xxbr-1.c (rev_bool_char, rev_bool_short,
rev_bool_int): Add test cases for builtins.
* gcc.target/powerpc/p9-xxbr-2.c (rev_long_long, rev_ulong_ulong): Add
test cases for builtins.
From-SVN: r250155
Carl Love [Wed, 12 Jul 2017 15:04:44 +0000 (15:04 +0000)]
builtins-1-p9-runnable.c (dg-ddo run): Add lp64 && p9vector_hw.
gcc/testsuite/ChangeLog:
2017-07-12 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-1-p9-runnable.c (dg-ddo run): Add
lp64 && p9vector_hw.
From-SVN: r250154
Andreas Krebbel [Wed, 12 Jul 2017 15:00:58 +0000 (15:00 +0000)]
S/390: Remove loc splitter
The backend splitter splitting a 3 operand load on condition into 2 is
wrong. The S/390 load on condition instruction might trap on the
memory operand even if the condition is false. So if the first load
on condition overwrites a register used as part of the memory address
of the second the second might trigger a segfault even if it does not
actually perform the load.
Trying to fix this I noticed that the generated code looks anyway
better without the splitter. So removing the splitter entirely is the
way to go here.
gcc/ChangeLog:
2017-07-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.md: Remove movcc splitter.
From-SVN: r250153
Andreas Krebbel [Wed, 12 Jul 2017 14:59:36 +0000 (14:59 +0000)]
S/390: Calculate costs for load/store on condition
This adds code to the backend rtx_costs function in order to model the
costs of a load/store on condition.
gcc/ChangeLog:
2017-07-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.c (s390_rtx_costs): Return proper costs for
load/store on condition.
From-SVN: r250152
Georg-Johann Lay [Wed, 12 Jul 2017 13:58:34 +0000 (13:58 +0000)]
re PR target/81407 ([avr] Diagnose if a variable in progmem needs constructing.)
PR target/81407
* config/avr/avr.c (avr_encode_section_info)
[progmem && !TREE_READONLY]: Error if progmem object needs
constructing.
From-SVN: r250151
Christophe Lyon [Wed, 12 Jul 2017 07:53:28 +0000 (07:53 +0000)]
[testsuite] Fix dg-require-stack-check
2017-07-12 Christophe Lyon <christophe.lyon@linaro.org>
* lib/target-supports.exp (check_stack_check_available): Make
testcase name depend on stack_kind.
From-SVN: r250149
Michael Collison [Wed, 12 Jul 2017 02:18:06 +0000 (02:18 +0000)]
aarch64-simd.md (aarch64_sub<mode>_compare0): New pattern.
2017-07-11 Michael Collison <michael.collison@arm.com>
* config/aarch64/aarch64-simd.md(aarch64_sub<mode>_compare0):
New pattern.
* testsuite/gcc.target/aarch64/cmp-2.c: New testcase.
From-SVN: r250148
GCC Administrator [Wed, 12 Jul 2017 00:16:28 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250147
Paolo Carlini [Tue, 11 Jul 2017 21:24:11 +0000 (21:24 +0000)]
re PR c++/51270 (missed warning about returning reference to temporary)
2017-07-11 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/51270
* g++.dg/warn/Wreturn-local-addr-3.C: New.
From-SVN: r250140
Jason Merrill [Tue, 11 Jul 2017 18:41:32 +0000 (14:41 -0400)]
Core DR 393 - parameter pointer to array of unknown bound
* decl.c (grokparms): Downgrade error about array of unknown bound
to pedwarn and disable it for C++17.
From-SVN: r250137
Carl Love [Tue, 11 Jul 2017 14:53:06 +0000 (14:53 +0000)]
rs6000-c.c: Add support for builtins vector unsigned int vec_parity_lsbb (vector signed int)...
gcc/ChangeLog:
2017-07-11 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for builtins
vector unsigned int vec_parity_lsbb (vector signed int);
vector unsigned int vec_parity_lsbb (vector unsigned int);
vector unsigned __int128 vec_parity_lsbb (vector signed __int128);
vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128);
vector unsigned long long vec_parity_lsbb (vector signed long long);
vector unsigned long long vec_parity_lsbb (vector unsigned long long);
* config/rs6000/rs6000-builtin.def (VPARITY_LSBB): Add BU_P9V_OVERLOAD1.
* config/rs6000/altivec.h (vec_parity_lsbb): Add define.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
gcc/testsuite/ChangeLog:
2017-07-11 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-2-p9-runnable.c: Add new file with
test cases for the builtins.
From-SVN: r250135
David Malcolm [Tue, 11 Jul 2017 14:02:27 +0000 (14:02 +0000)]
Fix ChangeLog omission in r250133
From-SVN: r250134
David Malcolm [Tue, 11 Jul 2017 13:43:31 +0000 (13:43 +0000)]
diagnostics: support compact printing of secondary locations
gcc/ChangeLog:
* diagnostic-show-locus.c: Include "gcc-rich-location.h".
(layout::m_primary_loc): New field.
(layout::layout): Initialize new field. Move location filtering
logic from here to...
(layout::maybe_add_location_range): ...this new method. Add
support for filtering to just the lines already specified by other
locations.
(layout::will_show_line_p): New method.
(selftest::test_add_location_if_nearby): New test function.
(selftest::diagnostic_show_locus_c_tests): Call it.
* gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
New method.
From-SVN: r250133
Nathan Sidwell [Tue, 11 Jul 2017 12:28:21 +0000 (12:28 +0000)]
* decl2.c (reset_type_linkage_2): Dont't change ctor name.
From-SVN: r250130
Tom de Vries [Tue, 11 Jul 2017 12:25:01 +0000 (12:25 +0000)]
Add extra initialization of broadcasted condition variables
2017-07-11 Tom de Vries <tom@codesourcery.com>
* config/nvptx/nvptx.c (WORKAROUND_PTXJIT_BUG): New macro.
(bb_first_real_insn): New function.
(nvptx_single): Add extra initialization of broadcasted condition
variables.
From-SVN: r250129
Yury Gribov [Tue, 11 Jul 2017 12:23:58 +0000 (12:23 +0000)]
profopt.exp: Print relative names in UNSUPPORTED AutoFDO tests.
2017-07-11 Yury Gribov <tetra2005@gmail.com>
* lib/profopt.exp: Print relative names in UNSUPPORTED
AutoFDO tests.
From-SVN: r250128
Nathan Sidwell [Tue, 11 Jul 2017 12:22:24 +0000 (12:22 +0000)]
* dwarf2out.c (gen_member_die): Remove useless check for anon ctors.
From-SVN: r250127
Jonathan Wakely [Tue, 11 Jul 2017 11:11:33 +0000 (12:11 +0100)]
Improvements to the libstdc++ FAQ and manual
* doc/xml/faq.xml: Update several old entries. Improve
cross-references.
* doc/xml/manual/intro.xml: Add anchors to each DR.
* doc/html/*: Regenerate.
From-SVN: r250125
Georg-Johann Lay [Tue, 11 Jul 2017 10:26:30 +0000 (10:26 +0000)]
extend.texi (AVR Function Attributes): Remove weblink to Binutils doc as TEXI will mess them up.
* doc/extend.texi (AVR Function Attributes): Remove weblink to
Binutils doc as TEXI will mess them up.
* doc/invoke.texi (AVR Options): Same here.
From-SVN: r250124
Daniel Cederman [Tue, 11 Jul 2017 07:18:50 +0000 (07:18 +0000)]
sparc.opt (mfix-ut700): New option.
* config/sparc/sparc.opt (mfix-ut700): New option.
(mfix-gr712rc): Likewise.
(sparc_fix_b2bst): New variable.
* doc/invoke.texi (SPARC options): Document them.
(ARM options): Fix warnings.
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent sequences that can trigger the store-store
errata for certain LEON3FT processors.
(pass_work_around_errata::gate): Also test sparc_fix_b2bst.
(sparc_option_override): Set sparc_fix_b2bst appropriately.
* config/sparc/sparc.md (fix_b2bst): New attribute.
(in_branch_delay): Prevent stores in delay slot if fix_b2bst.
From-SVN: r250114
Michael Collison [Tue, 11 Jul 2017 00:17:02 +0000 (00:17 +0000)]
var_shift_mask_1.c: Fix for ILP32
2017-07-10 Michael Collison <michael.collison@arm.com>
* gcc.target/aarch64/var_shift_mask_1.c: Fix for ILP32
From-SVN: r250112
GCC Administrator [Tue, 11 Jul 2017 00:16:21 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250111
Uros Bizjak [Mon, 10 Jul 2017 22:01:06 +0000 (00:01 +0200)]
re PR target/81375 (unrecognizable insn)
PR target/81375
* config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH.
(rcpps): Ditto.
(*rsqrtsf2_sse): Ditto.
(rsqrtsf2): Ditto.
(div<mode>3): Macroize insn from divdf3 and divsf3
using MODEF mode iterator.
testsuite/ChangeLog:
PR target/81375
* gcc.target/i386/pr81375.c: New test.
From-SVN: r250107
Martin Sebor [Mon, 10 Jul 2017 21:21:51 +0000 (21:21 +0000)]
PR tree-optimization/80397 - missing -Wformat-overflow with arguments of enum types
gcc/ChangeLog:
PR tree-optimization/80397
* gimple-ssa-sprintf.c (format_integer): Use INTEGRAL_TYPE_P()
instead of testing for equality to INTEGER_TYPE.
gcc/testsuite/ChangeLog:
PR tree-optimization/80397
* gcc.dg/tree-ssa/builtin-sprintf-warn-17.c: New test.
From-SVN: r250106
Martin Sebor [Mon, 10 Jul 2017 21:08:04 +0000 (21:08 +0000)]
cp-tree.h (cp_operator_id, [...]): Document.
gcc/cp/ChangeLog:
* cp-tree.h (cp_operator_id, cp_assignment_operator_id): Document.
From-SVN: r250105
Martin Sebor [Mon, 10 Jul 2017 21:00:56 +0000 (21:00 +0000)]
PR other/81345 - -Wall resets -Wstringop-overflow to 1 from the default 2
gcc/c-family/ChangeLog:
PR other/81345
* c.opt (-Wstringop-overflow): Set defaults in LangEnabledBy.
gcc/testsuite/ChangeLog:
PR other/81345
* gcc.dg/pr81345.c: New test.
From-SVN: r250104
Jonathan Wakely [Mon, 10 Jul 2017 18:43:02 +0000 (19:43 +0100)]
Include missing header for std::free
* testsuite/abi/pr42230.cc: Add header for std::free.
From-SVN: r250102
Jonathan Wakely [Mon, 10 Jul 2017 17:59:02 +0000 (18:59 +0100)]
PR libstdc++/81381 support stateful allocators in basic_stringbuf
PR libstdc++/81381
* include/bits/sstream.tcc (basic_stringbuf::overflow)
(basic_stringbuf::basic_stringbuf(const __string_type&, ios::mode))
(basic_stringbuf::str()): Construct new strings with an allocator.
* testsuite/27_io/basic_stringbuf/cons/81381.cc: New.
From-SVN: r250101
Jonathan Wakely [Mon, 10 Jul 2017 17:58:56 +0000 (18:58 +0100)]
PR libstdc++/81338 correctly manage string capacity
PR libstdc++/81338
* include/bits/basic_string.h [_GLIBCXX_USE_CXX11_ABI] (basic_string):
Declare basic_stringbuf to be a friend.
* include/bits/sstream.tcc (basic_stringbuf::overflow)
[_GLIBCXX_USE_CXX11_ABI]: Use unused capacity before reallocating.
* include/std/sstream (basic_stringbuf::__xfer_bufptrs): Update string
length to buffer length.
* testsuite/27_io/basic_stringstream/assign/81338.cc: New.
From-SVN: r250100
Vineet Gupta [Mon, 10 Jul 2017 13:55:26 +0000 (13:55 +0000)]
[ARC] Configure script to allow non uclibc based triplets
gcc/
2017-07-10 Vineet Gupta <vgupta@synopsys.com>
* config.gcc: Remove uclibc from arc target spec.
libgcc/
2017-07-10 Vineet Gupta <vgupta@synopsys.com>
* config.host: Remove uclibc from arc target spec.
From-SVN: r250097
Claudiu Zissulescu [Mon, 10 Jul 2017 13:55:16 +0000 (15:55 +0200)]
[ARC] Fix tests asm constraints.
LRA doesn't like the 'X' constraint as used in our tests, remove it.
gcc/testsuite
2017-07-10 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/mulsi3_highpart-1.c: Remove 'X' constraint.
* gcc.target/arc/mulsi3_highpart-2.c: Likewise.
From-SVN: r250096
Claudiu Zissulescu [Mon, 10 Jul 2017 13:55:05 +0000 (15:55 +0200)]
[ARC] Define ADDITIONAL_REGISTER_NAMES.
This macro is needed to be used with -ffixed-<reg> option, and inline asm.
gcc/
2017-07-10 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Define.
From-SVN: r250095
Jan Hubicka [Mon, 10 Jul 2017 13:25:23 +0000 (15:25 +0200)]
re PR bootstrap/80838 (PGO/LTO bootstrapped compiler 5% slower than pure PGO bootstrapped one)
PR lto/80838
* lto-wrapper.c (remove_option): New function.
(merge_and_complain): Merge PIC/PIE options more realistically.
From-SVN: r250094
Georg-Johann Lay [Mon, 10 Jul 2017 09:49:18 +0000 (09:49 +0000)]
Better ISR prologues by supporting GASes __gcc_isr pseudo insn.
gcc/
Better ISR prologues by supporting GASes __gcc_isr pseudo insn.
PR target/20296
PR target/81268
* configure.ac [target=avr]: Add GAS check for -mgcc-isr.
(HAVE_AS_AVR_MGCCISR_OPTION): If so, AC_DEFINE it.
* config.in: Regenerate.
* configure: Regenerate.
* doc/extend.texi (AVR Function Attributes) <no_gccisr>: Document it.
* doc/invoke.texi (AVR Options) <-mgas-isr-prologues>: Document it.
* config/avr/avr.opt (-mgas-isr-prologues): New option and...
(TARGET_GASISR_PROLOGUES): ...target mask.
* common/config/avr/avr-common.c
(avr_option_optimization_table) [OPT_LEVELS_1_PLUS_NOT_DEBUG]:
Set -mgas-isr-prologues.
* config/avr/avr-passes.def (avr_pass_pre_proep): Add
INSERT_PASS_BEFORE for it.
* config/avr/avr-protos.h (make_avr_pass_pre_proep): New proto.
* config/avr/avr.c (avr_option_override)
[!HAVE_AS_AVR_MGCCISR_OPTION]: Unset TARGET_GASISR_PROLOGUES.
(avr_no_gccisr_function_p, avr_hregs_split_reg): New static functions.
(avr_attribute_table) <no_gccisr>: Add new function attribute.
(avr_set_current_function) <is_no_gccisr>: Init machine field.
(avr_pass_data_pre_proep, avr_pass_pre_proep): New pass data
and rtl_opt_pass.
(make_avr_pass_pre_proep): New function.
(emit_push_sfr) <treg>: Add argument to function and use it
instead of TMP_REG.
(avr_expand_prologue) [machine->gasisr.maybe]: Emit gasisr insn
and set machine->gasisr.yes.
(avr_expand_epilogue) [machine->gasisr.yes]: Similar.
(avr_asm_function_end_prologue) [machine->gasisr.yes]: Add
__gcc_isr.n_pushed to .L__stack_usage.
(TARGET_ASM_FINAL_POSTSCAN_INSN): Define to...
(avr_asm_final_postscan_insn): ...this new static function.
* config/avr/avr.h (machine_function)
<is_no_gccisr, use_L__stack_usage>: New fields.
<gasisr, gasisr.yes, gasisr.maybe, gasisr.regno>: New fields.
* config/avr/avr.md (UNSPECV_GASISR): Add unspecv enum.
(GASISR_Prologue, GASISR_Epilogue, GASISR_Done): New define_constants.
(gasisr, *gasisr): New expander and insn.
* config/avr/gen-avr-mmcu-specs.c (print_mcu)
[HAVE_AS_AVR_MGCCISR_OPTION]: Print asm_gccisr spec.
* config/avr/specs.h (ASM_SPEC) <asm_gccisr>: Add sub spec.
From-SVN: r250093
Richard Earnshaw [Mon, 10 Jul 2017 09:39:12 +0000 (09:39 +0000)]
[arm] Fix warning in parsecpu.awk
In awk, single quotes within a quoted string do not need escaping.
The existing code causes awk to grumble in the build logs.
* config/arm/parsecpu.awk (gen_comm_data): Do not escape single quotes
in quoted strings.
(really commit it this time)...
From-SVN: r250092
Georg-Johann Lay [Mon, 10 Jul 2017 08:22:47 +0000 (08:22 +0000)]
Move jump-tables out of .text again.
gcc/
Move jump-tables out of .text again.
PR target/81075
* config/avr/avr.c (ASM_OUTPUT_ADDR_VEC_ELT): Remove function.
(ASM_OUTPUT_ADDR_VEC): New function.
(avr_adjust_insn_length) [JUMP_TABLE_DATA_P]: Return 0.
(avr_final_prescan_insn) [avr_log.insn_addresses]: Dump
INSN_ADDRESSes as asm comment.
* config/avr/avr.h (JUMP_TABLES_IN_TEXT_SECTION): Adjust comment.
(ASM_OUTPUT_ADDR_VEC_ELT): Remove define.
(ASM_OUTPUT_ADDR_VEC): Define to avr_output_addr_vec.
* config/avr/avr.md (*tablejump): Adjust comment.
* config/avr/elf.h (ASM_OUTPUT_BEFORE_CASE_LABEL): Remove.
* config/avr/avr-log.c (avr_log_set_avr_log) <insn_addresses>:
New detail.
* config/avr/avr-protos.h (avr_output_addr_vec_elt): Remove proto.
(avr_output_addr_vec): New proto.
(avr_log_t) <insn_addresses>: New field.
From-SVN: r250091
GCC Administrator [Mon, 10 Jul 2017 00:16:51 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250090
Uros Bizjak [Sun, 9 Jul 2017 21:01:42 +0000 (23:01 +0200)]
re PR target/81313 (Bad stack realignment code with -mno-accumulate-outgoing-args)
PR target/81313
* gcc.dg/stack-layout-dynamic-1.c (bar): Add 4 additional
integer argumets to bypass x86_64 outgoing args optimization.
From-SVN: r250086
Thomas Koenig [Sun, 9 Jul 2017 19:09:33 +0000 (19:09 +0000)]
eoshift2.c (eoshift2): Use memcpy for innermost copy where possible.
2017-06-09 Thomas Koenig <tkoenig@gcc.gnu.org>
* intrinsics/eoshift2.c (eoshift2): Use memcpy
for innermost copy where possible.
* m4/eoshift1.m4 (eoshift1): Likewise.
* m4/eoshift3.m4 (eoshift3): Likewise.
* generated/eoshift1_16.c: Regenerated.
* generated/eoshift1_4.c: Regenerated.
* generated/eoshift1_8.c: Regenerated.
* generated/eoshift3_16.c: Regenerated.
* generated/eoshift3_4.c: Regenerated.
* generated/eoshift3_8.c: Regenerated.
2017-06-09 Thomas Koenig <tkoenig@gcc.gnu.org>
* gfortran.dg/eoshift_4.f90: New test.
* gfortran.dg/eoshift_5.f90: New test.
* gfortran.dg/eoshift_6.f90: New test.
From-SVN: r250085
H.J. Lu [Sun, 9 Jul 2017 18:25:49 +0000 (18:25 +0000)]
x86: Use DRAP only if there are outgoing arguments on stack
Since DRAP is needed only if there are outgoing arguments on stack, we
should track outgoing arguments on stack and avoid setting need_drap to
true when there are no outgoing arguments on stack.
gcc/
PR target/81313
* config/i386/i386.c (ix86_function_arg_advance): Set
outgoing_args_on_stack to true if there are outgoing arguments
on stack.
(ix86_function_arg): Likewise.
(ix86_get_drap_rtx): Use DRAP only if there are outgoing
arguments on stack and ACCUMULATE_OUTGOING_ARGS is false.
* config/i386/i386.h (machine_function): Add
outgoing_args_on_stack.
gcc/testsuite/
PR target/81313
* gcc.target/i386/pr81313-1.c: New test.
* gcc.target/i386/pr81313-2.c: Likewise.
* gcc.target/i386/pr81313-3.c: Likewise.
* gcc.target/i386/pr81313-4.c: Likewise.
* gcc.target/i386/pr81313-5.c: Likewise.
From-SVN: r250084
Dominique d'Humieres [Sun, 9 Jul 2017 17:41:45 +0000 (19:41 +0200)]
re PR fortran/81341 (trunk/gcc/fortran/class.c:313: redundant condition ?)
2017-07-09 Dominique d'Humieres <dominiq@lps.ens.fr>
PR fortran/81341
* class.c (class_array_ref_detected): Remove a redundant
condition.
From-SVN: r250083
Krister Walfridsson [Sun, 9 Jul 2017 04:22:43 +0000 (04:22 +0000)]
config.gcc (*-*-netbsd*): Remove check for NetBSD versions not supporting pthreds.
2017-07-09 Krister Walfridsson <krister.walfridsson@gmail.com>
* config.gcc (*-*-netbsd*): Remove check for NetBSD versions not
supporting pthreds.
* config/netbsd.h (NETBSD_LIBGCC_SPEC): Always enable pthreads.
From-SVN: r250081
Krister Walfridsson [Sun, 9 Jul 2017 04:01:02 +0000 (04:01 +0000)]
config.host (*-*-netbsd*): Remove check for aout NetBSD releases.
2017-07-09 Krister Walfridsson <krister.walfridsson@gmail.com>
* config.host (*-*-netbsd*): Remove check for aout NetBSD releases.
From-SVN: r250080
GCC Administrator [Sun, 9 Jul 2017 00:16:18 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250079
Richard Sandiford [Sat, 8 Jul 2017 13:40:03 +0000 (13:40 +0000)]
Fix coretypes.h-related dependencies
The bug fix here is to build/min-insn-modes.o, the rest are related
clean-ups.
2017-07-08 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* Makefile.in (HOOKS_H, RTL_BASE_H, FUNCTION_H, EXPR_H, REGS_H)
(REAL_H): Remove $(MACHMODE_H).
(FIXED_VALUE_H, TREE_CORE_H, CFGLOOP_H): Remove $(MACHMODE_H) and
double-int.h.
(CORETYPES_H): Add signop.h, wide-int.h, wide-int-print.h,
$(MACHMODE_H) and double-int.h.
(build/min-insn-modes.o): Depend on $(CORETYPES_H) rather than
$(MACHMODE_H).
(gengtype-state.o, gengtype.o, build/gengtype.o): Don't depend on
double-int.h.
From-SVN: r250075
Richard Sandiford [Sat, 8 Jul 2017 10:38:40 +0000 (10:38 +0000)]
Force a dependence distance of 1 in gnat.dg/vect17.adb
2017-07-08 Richard Sandiford <richard.sandiford@linaro.org>
gcc/testsuite/
* gnat.dg/vect15.ads (Sarray): Increase range to 1 .. 5.
* gnat.dg/vect16.ads (Sarray): Likewise.
* gnat.dg/vect17.ads (Sarray): Likewise.
* gnat.dg/vect15.adb (Add): Create a dependence distance of 1.
* gnat.dg/vect16.adb (Add): Likewise.
* gnat.dg/vect17.adb (Add): Likewise.
From-SVN: r250074
GCC Administrator [Sat, 8 Jul 2017 00:16:18 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250072
Andrew Pinski [Fri, 7 Jul 2017 22:52:12 +0000 (22:52 +0000)]
aarch64.c (aarch_macro_fusion_pair_p): Check prev_set and curr_set for AARCH64_FUSE_ALU_BRANCH.
2017-07-07 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Check
prev_set and curr_set for AARCH64_FUSE_ALU_BRANCH.
From-SVN: r250068
Peter Bergner [Fri, 7 Jul 2017 21:08:42 +0000 (16:08 -0500)]
float128-ifunc.c: Don't include auxv.h.
libgcc/
* config/rs6000/float128-ifunc.c: Don't include auxv.h.
(have_ieee_hw_p): Delete function.
(SW_OR_HW) Use __builtin_cpu_supports().
From-SVN: r250061
David Malcolm [Fri, 7 Jul 2017 18:49:09 +0000 (18:49 +0000)]
libcpp: preserve ranges within macro expansions (PR c++/79300)
gcc/testsuite/ChangeLog:
PR c++/79300
* g++.dg/diagnostic/pr79300.C: New test case.
libcpp/ChangeLog:
PR c++/79300
* line-map.c (linemap_macro_loc_to_def_point): Preserve range
information for macro expansions by delaying resolving ad-hoc
locations until within the loop.
From-SVN: r250058
Michael Meissner [Fri, 7 Jul 2017 18:43:55 +0000 (18:43 +0000)]
rs6000.c (rs6000_get_function_versions_dispatcher): Add warning if GCC was not configured to link against a GLIBC that exports the...
[gcc]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_get_function_versions_dispatcher):
Add warning if GCC was not configured to link against a GLIBC that
exports the hardware capability bits.
(make_resolver_func): Make resolver function private and not a
COMDAT function. Create the name with clone_function_name instead
of make_unique_name.
[gcc/testsuite]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/clone1.c: Add check to make sure the
__builtin_cpu_supports function is fully supported.
* gcc.target/powerpc/clone2.c: New runtime test for
target_clones.
From-SVN: r250055
Michael Meissner [Fri, 7 Jul 2017 17:02:58 +0000 (17:02 +0000)]
re PR target/81348 (PowerPC64: Code built with -mcpu=power9 hits SEGV in RTL split2)
[gcc]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81348
* config/rs6000/rs6000.md (HI sign_extend splitter): Use the
correct operand in doing the split.
[gcc/testsuite]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81348
* gcc.target/powerpc/pr81348.c: New test.
From-SVN: r250054
Szabolcs Nagy [Fri, 7 Jul 2017 16:46:22 +0000 (16:46 +0000)]
Fix pr60510.f test on arm-linux-gnueabihf
Only run the test if the target supports double precision vectorization.
gcc/testsuite/ChangeLog:
2017-07-07 Szabolcs Nagy <szabolcs.nagy@arm.com>
* gfortran.dg/vect/pr60510.f: Require vect_double support.
From-SVN: r250053
Carl Love [Fri, 7 Jul 2017 16:20:52 +0000 (16:20 +0000)]
builtins-1-p9-runnable.c: Forgot to add new file before doing commit 250051.
gcc/testsuite/ChangeLog:
2017-07-07 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-1-p9-runnable.c: Forgot to add new
file before doing commit 250051.
From-SVN: r250052
Carl Love [Fri, 7 Jul 2017 16:17:46 +0000 (16:17 +0000)]
rs6000-c: Add support for built-in function vector unsigned short vec_pack_to_short_fp32...
gcc/ChangeLog:
2017-07-07 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c: Add support for built-in function
vector unsigned short vec_pack_to_short_fp32 (vector float,
vector float).
* config/rs6000/rs6000-builtin.def (CONVERT_4F32_8I16): Add
BU_P9V_AV_2 and BU_P9V_OVERLOAD_2 definitions.
* config/rs6000/altivec.h (vec_pack_to_short_fp32): Add define.
* config/rs6000/altivec.md(UNSPEC_CONVERT_4F32_8I16): Add UNSPEC.
(convert_4f32_8i16): Add define_expand.
* doc/extend.texi: Update the built-in documentation file for the
new built-in function.
gcc/testsuite/ChangeLog:
2017-07-07 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-1-p9-runnable.c: Add new test
file for built-ins.
From-SVN: r250051
Jose E. Marchesi [Fri, 7 Jul 2017 13:59:30 +0000 (15:59 +0200)]
Support for the SPARC M8 cpu.
This patch serie adds support for the SPARC M8 processor to GCC.
The SPARC M8 processor implements the Oracle SPARC Architecture 2017.
- bmask* instructions are put in their own instruction type. It makes
little sense to have them in the same category than array
instructions.
- Similarly, VIS compare instructions are put in their own instruction
type. This is to better accommodate subtypes, which are not quite
the same than the subtypes of `visl' instructions.
- The introduction of a new `subtype' insn attribute in sparc.md
avoids the need for adjusting the instruction scheduler DFAs for
previous cpu models every time a new cpu is introduced.
- The full set of SPARC instructions used in sparc.md, and their
position in the type/subtype hierarchy, is documented in a comment.
This eases the modification of the DFA schedulers, and the addition
of new cpus.
- The M7 DFA scheduler is reworked:
+ To use the new type/subtype hierarchy.
+ The v3pipe insn attribute is no longer needed.
+ More accurate latencies for instructions.
+ The C4 core pipeline is documented in a comment in niagara7.md.
- Support for -mcpu=m8 (we are thus suggesting to abandon the niagaraN
denomination for M8 and later processors.)
- Support for a new VIS level, VIS4B, covering the new VIS
instructions introduced in OSA2017 and implemented in the M8. Also
built-ins.
- A M8 DFA scheduler:
+ Also based on the new type/subtype hierarchy.
+ The functional units in the C5 core are explicitly documented in a
comment in m8.md.
gcc/ChangeLog:
* config/sparc/m8.md: New file.
* config/sparc/sparc.md: Include m8.md.
* config/sparc/sparc.opt: New option -mvis4b.
* config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B.
(sparc_option_override): Handle VIS4B.
(enum sparc_builtins): Define
SPARC_BUILTIN_DICTUNPACK{8,16,32},
SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and
SPARC_BUILTIN_FPCMPUR{8,16,32}SHL.
(check_constant_argument): New function.
(sparc_vis_init_builtins): Define builtins
__builtin_vis_dictunpack{8,16,32},
__builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl,
__builtin_vis_fpcmpu{le,gt}{8,16,32}shl,
__builtin_vis_fpcmpde{8,16,32}shl and
__builtin_vis_fpcmpur{8,16,32}shl.
(sparc_expand_builtin): Check that the constant operands to
__builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed
constant and in range.
* config/sparc/sparc-c.c (sparc_target_macros): Handle
TARGET_VIS4B.
* config/sparc/sparc.h (SPARC_IMM2_P): Define.
(SPARC_IMM5_P): Likewise.
* config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b".
(enabled): Handle vis4b.
(UNSPEC_DICTUNPACK): New unspec.
(UNSPEC_FPCMPSHL): Likewise.
(UNSPEC_FPUCMPSHL): Likewise.
(UNSPEC_FPCMPDESHL): Likewise.
(UNSPEC_FPCMPURSHL): Likewise.
(cpu_feature): New CPU feature `vis4b'.
(dictunpack{8,16,32}): New insns.
(FPCSMODE): New mode iterator.
(fpcscond): New code iterator.
(fpcsucond): Likewise.
(fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns.
(fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise.
(fpcmpde{8,16,32}{si,di}shl): Likewise.
(fpcmpur{8,16,32}{si,di}shl): Likewise.
* config/sparc/constraints.md: Define constraints `q' for unsigned
2-bit integer constants and `t' for unsigned 5-bit integer
constants.
* config/sparc/predicates.md (imm5_operand_dictunpack8): New
predicate.
(imm5_operand_dictunpack16): Likewise.
(imm5_operand_dictunpack32): Likewise.
(imm2_operand): Likewise.
* doc/invoke.texi (SPARC Options): Document -mvis4b.
* doc/extend.texi (SPARC VIS Built-in Functions): Document the
ditunpack* and fpcmp*shl builtins.
* config.gcc: Handle m8 in --with-{cpu,tune} options.
* config.in: Add HAVE_AS_SPARC6 define.
* config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC
M8.
* config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for
TARGET_CPU_m8.
(ASM_CPU32_DEFAUILT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle m8.
(ASM_CPU_SPEC): Likewise.
* config/sparc/sparc-opts.h (enum processor_type): Add
PROCESSOR_M8.
* config/sparc/sparc.c (m8_costs): New struct.
(sparc_option_override): Handle TARGET_CPU_m8.
(sparc32_initialize_trampoline): Likewise.
(sparc64_initialize_trampoline): Likewise.
(sparc_issue_rate): Likewise.
(sparc_register_move_cost): Likewise.
* config/sparc/sparc.h (TARGET_CPU_m8): Define.
(CPP_CPU64_DEFAULT_SPEC): Define for M8.
(ASM_CPU64_DEFAULT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle M8.
(ASM_CPU_SPEC): Likewise.
(AS_M8_FLAG): Define.
* config/sparc/sparc.md: Add m8 to the cpu attribute.
* config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets.
* configure.ac (HAVE_AS_SPARC6): Check for assembler support for
M8 instructions.
* configure: Regenerate.
* doc/invoke.texi (SPARC Options): Document -mcpu=m8 and
-mtune=m8.
* config/sparc/niagara7.md: Rework the DFA scheduler to use insn
subtypes.
* config/sparc/sparc.md: Remove the `v3pipe' insn attribute.
("*movdi_insn_sp32"): Do not set v3pipe.
("*movsi_insn"): Likewise.
("*movdi_insn_sp64"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("*sign_extendsidi2_insn"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("<vlop:code><VL:mode>3"): Likewise.
("*not_<vlop:code><VL:mode>3"): Likewise.
("*nand<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise.
("one_cmpl<VL:mode>2"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likweise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
("bmaskdi_vis"): Likewise.
("bmasksi_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("pdistn<P:mode>_vis"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
* config/sparc/sparc.md ("subtype"): New insn attribute.
("*wrgsr_sp64"): Set insn subtype.
("*rdgsr_sp64"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likewise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("fexpand_vis"): Likewise.
("fpmerge_vis"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("fchksm16_vis"): Likewise.
("v<vis3_shift_patname><GCM:mode>3"): Likewise.
("fmean16_vis"): Likewise.
("fp<plusminus_insn>64_vis"): Likewise.
("<plusminus_insn>v8qi3"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
("<vis4_minmax_patname><VMMAX:mode>3"): Likewise.
("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise.
("<vis3_addsub_ss_patname>v8qi3"): Likewise.
("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise.
("*movqi_insn"): Likewise.
("*movhi_insn"): Likewise.
("*movsi_insn"): Likewise.
("movsi_pic_gotdata_op"): Likewise.
("*movdi_insn_sp32"): Likewise.
("*movdi_insn_sp64"): Likewise.
("movdi_pic_gotdata_op"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendhisi2_insn"): Likewise.
("*zero_extendqihi2_insn"): Likewise.
("*zero_extendqisi2_insn"): Likewise.
("*zero_extendqidi2_insn"): Likewise.
("*zero_extendhidi2_insn"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("ldfsr"): Likewise.
("prefetch_64"): Likewise.
("prefetch_32"): Likewise.
("tie_ld32"): Likewise.
("tie_ld64"): Likewise.
("*tldo_ldub_sp32"): Likewise.
("*tldo_ldub1_sp32"): Likewise.
("*tldo_ldub2_sp32"): Likewise.
("*tldo_ldub_sp64"): Likewise.
("*tldo_ldub1_sp64"): Likewise.
("*tldo_ldub2_sp64"): Likewise.
("*tldo_ldub3_sp64"): Likewise.
("*tldo_lduh_sp32"): Likewise.
("*tldo_lduh1_sp32"): Likewise.
("*tldo_lduh_sp64"): Likewise.
("*tldo_lduh1_sp64"): Likewise.
("*tldo_lduh2_sp64"): Likewise.
("*tldo_lduw_sp32"): Likewise.
("*tldo_lduw_sp64"): Likewise.
("*tldo_lduw1_sp64"): Likewise.
("*tldo_ldx_sp64"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.
* config/sparc/sparc.md ("type"): New insn type viscmp.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to
viscmp.
("fpcmp<gcond:code>8<P:mode>_vis"): Likewise.
("fucmp<gcond:code>8<P:mode>_vis"): Likewise.
("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
* config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle
viscmp.
("n7_vis_logical_11cycle"): Likewise.
* config/sparc/niagara4.md ("n4_vis_logical"): Likewise.
* config/sparc/niagara2.md ("niag3_vis": Likewise.
* config/sparc/niagara.md ("niag_vis"): Likewise.
* config/sparc/ultra3.md ("us3_fga"): Likewise.
* config/sparc/ultra1_2.md ("us1_fga_double"): Likewise.
* config/sparc/sparc.md: New instruction type `bmask'.
(bmaskdi_vis): Use the `bmask' type.
(bmasksi_vis): Likewise.
* config/sparc/ultra3.md (us3_array): Likewise.
* config/sparc/niagara7.md (n7_array): Likewise.
* config/sparc/niagara4.md (n4_array): Likewise.
* config/sparc/niagara2.md (niag2_vis): Likewise.
(niag3_vis): Likewise.
* config/sparc/niagara.md (niag_vis): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/sparc/dictunpack.c: New file.
* gcc.target/sparc/fpcmpdeshl.c: Likewise.
* gcc.target/sparc/fpcmpshl.c: Likewise.
* gcc.target/sparc/fpcmpurshl.c: Likewise.
* gcc.target/sparc/fpcmpushl.c: Likewise.
From-SVN: r250049
Jan Hubicka [Fri, 7 Jul 2017 13:28:35 +0000 (15:28 +0200)]
ipa-comdats.c: Remove optimize check from gate.
* ipa-comdats.c: Remove optimize check from gate.
* ipa-fnsummary.c (ipa_fn_summary_generate): do not generate summary
for functions not optimized.
(ipa_fn_summary_read): Skip optimize check.
(ipa_fn_summary_write): Likewise.
* ipa-inline-analysis.c (do_estimate_growth_1): Check that caller
is optimized.
* ipa-inline.c (can_inline_edge_p): Not optimized functions are
uninlinable.
(can_inline_edge_p): Check flag_pcc_struct_return for match.
(check_callers): Give up on caller which is not optimized.
(inline_small_functions): Likewise.
(ipa_inline): Do not give up when not optimizing.
* ipa-visbility.c (function_and_variable_visibility): Do not optimize
away unoptimizes cdtors.
(whole_program_function_and_variable_visibility): Do
ipa_discover_readonly_nonaddressable_vars in LTO mode.
* ipa.c (process_references): Do not check optimize.
(symbol_table::remove_unreachable_nodes): Update optimize check.
(set_writeonly_bit): Update optimize check.
(pass_ipa_cdtor_merge::gate): Do not check optimize.
(pass_ipa_single_use::gate): Remove.
From-SVN: r250048
GCC Administrator [Fri, 7 Jul 2017 00:16:25 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250047
Aaron Sawdey [Thu, 6 Jul 2017 20:20:48 +0000 (20:20 +0000)]
rs6000.c (union_defs, [...]): Move all code related to p8 swap optimizations to file rs6000-p8swap.c.
2017-07-06 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (union_defs, union_uses, insn_is_load_p,
insn_is_store_p, insn_is_swap_p, const_load_sequence_p, v2df_reduction_p,
rtx_is_swappable_p, insn_is_swappable_p, chain_contains_only_swaps,
mark_swaps_for_removal, swap_const_vector_halves, adjust_subreg_index,
permute_load, permute_store, adjust_extract, adjust_splat,
adjust_xxpermdi, adjust_concat, adjust_vperm, handle_special_swappables,
replace_swap_with_copy, dump_swap_insn_table,
alignment_with_canonical_addr, alignment_mask, find_alignment_op,
recombine_lvx_pattern, recombine_stvx_pattern,
recombine_lvx_stvx_patterns, rs6000_analyze_swaps,
make_pass_analyze_swaps): Move all code related to p8 swap optimizations
to file rs6000-p8swap.c.
* config/rs6000/rs6000-p8swap.c: New file.
* config/rs6000/t-rs6000: Add rule to build rs6000-p8swap.o.
* config.gcc: Add rs6000-p8swap.o to extra_objs for powerpc*-*-*
and rs6000*-*-* targets.
From-SVN: r250040
Harald Anlauf [Thu, 6 Jul 2017 19:49:33 +0000 (19:49 +0000)]
re PR fortran/70071 (ICE on wrong usage of a subscript triplet)
2017-07-06 Harald Anlauf <anlauf@gmx.de>
PR fortran/70071
* array.c (gfc_ref_dimen_size): Handle bad subscript triplets.
2017-07-06 Harald Anlauf <anlauf@gmx.de>
PR fortran/70071
* gfortran.dg/coarray_44.f90: New testcase.
From-SVN: r250039
Jason Merrill [Thu, 6 Jul 2017 18:26:59 +0000 (14:26 -0400)]
PR c++/81204 - parse error with dependent template-name
PR c++/81204 - parse error with dependent template-name
* parser.c (cp_parser_lookup_name): Revert previous change.
From-SVN: r250037
David Malcolm [Thu, 6 Jul 2017 17:37:14 +0000 (17:37 +0000)]
Remove selftest dependency on C++ frontend
gcc/ChangeLog
* Makefile.in (selftest): Remove dependency on s-selftest-c++.
From-SVN: r250036
Jan Hubicka [Thu, 6 Jul 2017 16:47:20 +0000 (18:47 +0200)]
lto-wrapper.c (merge_and_complain): Do not merge fexceptions...
* lto-wrapper.c (merge_and_complain): Do not merge
fexceptions, fnon_call_exceptions, ftrapv, ffp_contract_, fmath_errno,
fsigned_zeros, ftrapping_math, fwrapv.
(append_compiler_options): Do not track these options.
(append_linker_options): Likewie
From-SVN: r250035
Jan Hubicka [Thu, 6 Jul 2017 16:46:47 +0000 (18:46 +0200)]
cgraphunit.c (cgraph_node::finalize_function): When !flag_toplevel_reorde set no_reorder flag.
* cgraphunit.c (cgraph_node::finalize_function): When
!flag_toplevel_reorde set no_reorder flag.
(varpool_node::finalize_decl): Likewise.
(symbol_table::compile): Drop no toplevel reorder path.
* lto-partition.c (lto_balanced_map): Do not check
flag_toplevel_reorder.
From-SVN: r250034
Jan Hubicka [Thu, 6 Jul 2017 16:12:01 +0000 (18:12 +0200)]
bb-reorder.c (better_edge_p): Do not build traces across abnormal/eh edges...
* bb-reorder.c (better_edge_p): Do not build traces across abnormal/eh
edges; zero probability is not better than uninitialized.
From-SVN: r250033
Maxim Ostapenko [Thu, 6 Jul 2017 16:05:00 +0000 (16:05 +0000)]
asan.h (asan_sanitize_allocas_p): Declare.
gcc/
* asan.h (asan_sanitize_allocas_p): Declare.
* asan.c (asan_sanitize_allocas_p): New function.
(handle_builtin_stack_restore): Bail out if !asan_sanitize_allocas_p.
(handle_builtin_alloca): Likewise.
* cfgexpand.c (expand_used_vars): Do not add allocas unpoisoning stuff
if !asan_sanitize_allocas_p.
* params.def (asan-instrument-allocas): Add new option.
* params.h (ASAN_PROTECT_ALLOCAS): Define.
* opts.c (common_handle_option): Disable allocas sanitization for
KASan by default.
gcc/testsuite/
* c-c++-common/asan/kasan-alloca-1.c: New test.
* c-c++-common/asan/kasan-alloca-2.c: Likewise.
From-SVN: r250032
Maxim Ostapenko [Thu, 6 Jul 2017 16:02:06 +0000 (16:02 +0000)]
ASAN: Implement dynamic allocas/VLAs sanitization.
gcc/
* asan.c: Include gimple-fold.h.
(get_last_alloca_addr): New function.
(handle_builtin_stackrestore): Likewise.
(handle_builtin_alloca): Likewise.
(asan_emit_allocas_unpoison): Likewise.
(get_mem_refs_of_builtin_call): Add new parameter, remove const
quallifier from first paramerer. Handle BUILT_IN_ALLOCA,
BUILT_IN_ALLOCA_WITH_ALIGN and BUILT_IN_STACK_RESTORE builtins.
(instrument_builtin_call): Pass gimple iterator to
get_mem_refs_of_builtin_call.
(last_alloca_addr): New global.
* asan.h (asan_emit_allocas_unpoison): Declare.
* builtins.c (expand_asan_emit_allocas_unpoison): New function.
(expand_builtin): Handle BUILT_IN_ASAN_ALLOCAS_UNPOISON.
* cfgexpand.c (expand_used_vars): Call asan_emit_allocas_unpoison
if function calls alloca.
* gimple-fold.c (replace_call_with_value): Remove static keyword.
* gimple-fold.h (replace_call_with_value): Declare.
* internal-fn.c: Include asan.h.
* sanitizer.def (BUILT_IN_ASAN_ALLOCA_POISON,
BUILT_IN_ASAN_ALLOCAS_UNPOISON): New builtins.
gcc/testsuite/
* c-c++-common/asan/alloca_big_alignment.c: New test.
* c-c++-common/asan/alloca_detect_custom_size.c: Likewise.
* c-c++-common/asan/alloca_instruments_all_paddings.c: Likewise.
* c-c++-common/asan/alloca_loop_unpoisoning.c: Likewise.
* c-c++-common/asan/alloca_overflow_partial.c: Likewise.
* c-c++-common/asan/alloca_overflow_right.c: Likewise.
* c-c++-common/asan/alloca_safe_access.c: Likewise.
* c-c++-common/asan/alloca_underflow_left.c: Likewise.
From-SVN: r250031
David Malcolm [Thu, 6 Jul 2017 15:49:37 +0000 (15:49 +0000)]
Support C++-specific selftests
gcc/ChangeLog:
* Makefile.in (SELFTEST_FLAGS): Drop "-x c", moving it to...
(C_SELFTEST_FLAGS): New.
(CPP_SELFTEST_FLAGS): New.
(SELFTEST_DEPS): New, from deps of s-selftest.
(C_SELFTEST_DEPS): New, from deps of s-selftest.
(CPP_SELFTEST_DEPS): New.
(selftest): Add dependency on s-selftest-c++.
(s-selftest): Rename to...
(s-selftest-c): ...this, moving deps to SELFTEST_DEPS
and C_SELFTEST_DEPS, and using C_SELFTEST_FLAGS rather
than SELFTEST_FLAGS.
(selftest-gdb): Rename to...
(selftest-c-gdb): ...this, using C_SELFTEST_DEPS and
C_SELFTEST_FLAGS.
(selftest-gdb): Reintroduce as an alias for selftest-c-gdb.
(selftest-valgrind): Rename to...
(selftest-c-valgrind): ...this, using C_SELFTEST_DEPS and
C_SELFTEST_FLAGS.
(selftest-valgrind): Reintroduce as an alias for
selftest-c-valgrind.
(s-selftest-c++): New.
(selftest-c++-gdb): New.
(selftest-c++-valgrind): New.
gcc/c-family/ChangeLog:
* c-common.c (selftest::c_family_tests): New.
* c-common.h (selftest::run_c_tests): Move decl to c/c-lang.h.
(selftest::c_family_tests): New decl.
gcc/c/ChangeLog:
* c-lang.c (selftest::run_c_tests): Move body to c_family_tests,
and call that instead.
* c-tree.h (selftest::run_c_tests): New decl.
gcc/cp/ChangeLog:
* cp-lang.c (LANG_HOOKS_RUN_LANG_SELFTESTS): Define as
selftest::run_cp_tests.
(selftest::run_cp_tests): New function.
* cp-tree.h (selftest::run_cp_tests): New decl.
From-SVN: r250030
Georg-Johann Lay [Thu, 6 Jul 2017 15:31:42 +0000 (15:31 +0000)]
re PR target/81305 ([avr] avrtiny uses LDS for SREG in ISR routines which is out of range of LDS.)
PR target/81305
* gcc.target/avr/isr-test.h: Fix warnings.
From-SVN: r250029
Olivier Hainque [Thu, 6 Jul 2017 15:28:40 +0000 (15:28 +0000)]
Fix previous ChangeLog entry, taken from the original
patch instead of the update.
From-SVN: r250028
Olivier Hainque [Thu, 6 Jul 2017 15:04:30 +0000 (15:04 +0000)]
gcc.c (spec_undefvar_allowed): New global.
2017-07-06 Olivier Hainque <hainque@adacore.com>
* gcc.c (spec_undefvar_allowed): New global.
(process_command): Set to true when running for --version or --help
alone, or together.
(getenv_spec_function): When the variable is not defined, use the
variable name as the variable value if we're allowed not to issue
a fatal error.
From-SVN: r250027
Jan Hubicka [Thu, 6 Jul 2017 14:40:47 +0000 (16:40 +0200)]
auto-profile.c (afdo_set_bb_count, [...]): Set counts/probabilities as determined by afdo.
* auto-profile.c (afdo_set_bb_count, afdo_propagate_edge,
afdo_annotate_cfg): Set counts/probabilities as determined by afdo.
From-SVN: r250026
Thomas Preud'homme [Thu, 6 Jul 2017 14:37:28 +0000 (14:37 +0000)]
Add support for ARMv8-R architecture
2017-07-06 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-cpus.in (armv8-r): Add new entry.
* config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
enumerator.
* doc/invoke.texi: Mention -march=armv8-r and its extensions.
gcc/testsuite/
* lib/target-supports.exp: Generate
check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
and check_effective_target_arm_arch_v8r_multilib.
libgcc/
* config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
From-SVN: r250025
Carl Love [Thu, 6 Jul 2017 14:34:41 +0000 (14:34 +0000)]
ChangeLog: Clean up from mid air collision
gcc/ChangeLog:
2017-07-06 Carl Love <cel@us.ibm.com>
* ChangeLog: Clean up from mid air collision
gcc/testsuite/ChangeLog:
2017-07-06 Carl Love <cel@us.ibm.com>
* ChangeLog: Clean up from mid air collision
From-SVN: r250024
Carl Love [Thu, 6 Jul 2017 14:28:15 +0000 (14:28 +0000)]
rs6000-c.c: Add support for built-in functions vector signed int vec_subc (vector signed int...
gcc/ChangeLog:
2017-07-06 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector signed int vec_subc (vector signed int, vector signed int);
vector signed __int128 vec_subc (vector signed __int128,
vector signed __int128);
vector unsigned __int128 vec_subc (vector unsigned __int128,
vector unsigned __int128);
vector signed int vec_sube (vector signed int, vector signed int,
vector signed int);
vector unsigned int vec_sube (vector unsigned int,
vector unsigned int,
vector unsigned int);
vector signed __int128 vec_sube (vector signed __int128,
vector signed __int128,
vector signed__int128);
vector unsigned __int128 vec_sube (vector unsigned __int128,
vector unsigned __int128,
vector unsigned __int128);
vector signed int vec_subec (vector signed int, vector signed int,
vector signed int);
vector unsigned int vec_subec (vector unsigned int,
vector unsigned int,
vector unsigned int);
vector signed __int128 vec_subec (vector signed __int128,
vector signed __int128,
vector signed__int128);
vector unsigned __int128 vec_subec (vector unsigned __int128,
vector unsigned __int128,
vector unsigned __int128);
* config/rs6000/rs6000.c (ALTIVEC_BUILTIN_VEC_SUBE,
ALTIVEC_BUILTIN_VEC_SUBEC): Add ef_builtins.
* config/rs6000/rs6000-builtin.def (SUBE, SUBEC): Add
BU_ALTIVEC_OVERLOAD_X definitions.
* config/rs6000/altivec.h (vec_sube, vec_subec): Add builtin defines.
* doc/extend.texi: Update the built-in documentation file for the new
built-in functions.
gcc/testsuite/ChangeLog:
2017-07-06 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/p8vector-builtin-8.c (foo): Add test cases for
the new vec_subc, vec_sube, vec_subec built-ins. Add the missing test
cases for vec_addc, adde and addec builtins.
From-SVN: r250023
David Malcolm [Thu, 6 Jul 2017 14:17:24 +0000 (14:17 +0000)]
diagnostics: fix end-points of ranges within macros (PR c++/79300)
gcc/ChangeLog:
PR c++/79300
* diagnostic-show-locus.c (layout::layout): Use start and finish
spelling location for the start and finish of each range.
* genmatch.c (linemap_client_expand_location_to_spelling_point):
Add unused aspect param.
* input.c (expand_location_1): Add "aspect" param, and use it
to access the correct part of the location.
(expand_location): Pass LOCATION_ASPECT_CARET to new param of
expand_location_1.
(expand_location_to_spelling_point): Likewise.
(linemap_client_expand_location_to_spelling_point): Add "aspect"
param, and pass it to expand_location_1.
gcc/testsuite/ChangeLog:
PR c++/79300
* c-c++-common/Wmisleading-indentation-3.c (fn_14): Update
expected underlining within macro expansion.
* c-c++-common/pr70264.c: Likewise.
* g++.dg/plugin/diagnostic-test-expressions-1.C
(test_within_macro_1): New test.
(test_within_macro_2): Likewise.
(test_within_macro_3): Likewise.
(test_within_macro_4): Likewise.
* gcc.dg/format/diagnostic-ranges.c (test_macro_3): Update
expected underlining within macro expansion.
(test_macro_4): Likewise.
* gcc.dg/plugin/diagnostic-test-expressions-1.c
(test_within_macro_1): New test.
(test_within_macro_2): Likewise.
(test_within_macro_3): Likewise.
(test_within_macro_4): Likewise.
* gcc.dg/spellcheck-fields-2.c (test_macro): Update expected
underlining within macro expansion.
libcpp/ChangeLog:
PR c++/79300
* include/line-map.h (enum location_aspect): New enum.
(linemap_client_expand_location_to_spelling_point): Add
enum location_aspect param.
* line-map.c (rich_location::get_expanded_location): Update for
new param of linemap_client_expand_location_to_spelling_point.
(rich_location::maybe_add_fixit): Likewise.
(fixit_hint::affects_line_p): Likewise.
From-SVN: r250022
Jonathan Wakely [Thu, 6 Jul 2017 12:42:51 +0000 (13:42 +0100)]
Fix memory leaks in libstdc++ tests
* testsuite/20_util/specialized_algorithms/memory_management_tools/
1.cc: Free memory.
* testsuite/22_locale/locale/cons/5.cc: Remove redundant restoration
of original environment and free memory.
From-SVN: r250021
Jonathan Wakely [Thu, 6 Jul 2017 12:42:46 +0000 (13:42 +0100)]
Fix memory leaks in libstdc++ ABI tests
* testsuite/abi/pr42230.cc: Free memory.
* testsuite/util/testsuite_abi.cc (demangle): Return std::string
instead of pointer that might need freeing.
* testsuite/util/testsuite_abi.h (demangle): Likewise.
* testsuite/util/testsuite_hooks.cc (verify_demangle): Free memory.
From-SVN: r250020
Jonathan Wakely [Thu, 6 Jul 2017 11:54:10 +0000 (12:54 +0100)]
Prevent __uses_alloc from holding dangling references
* include/bits/uses_allocator.h (__use_alloc(const _Alloc&&)): Add
deleted overload to prevent dangling references to rvalues.
* include/experimental/memory_resource
(polymorphic_allocator::construct): Do not call __use_alloc with
rvalue arguments.
From-SVN: r250019
Sebastian Peryt [Thu, 6 Jul 2017 11:52:05 +0000 (13:52 +0200)]
Add missing intrinsics for VGETMANT[SD,SS] and VGETEXP[SD,SS]
gcc/
* config/i386/avx512fintrin.h (_mm_mask_getexp_round_ss,
_mm_maskz_getexp_round_ss, _mm_mask_getexp_round_sd,
_mm_maskz_getexp_round_sd, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss, _mm_mask_getexp_ss, _mm_maskz_getexp_ss,
_mm_mask_getexp_sd, _mm_maskz_getexp_sd, _mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_mask_getmant_ss,
_mm_maskz_getmant_ss): New intrinsics.
(__builtin_ia32_getexpss128_mask): Changed to ...
__builtin_ia32_getexpss128_round ... this.
(__builtin_ia32_getexpsd128_mask): Changed to ...
__builtin_ia32_getexpsd128_round ... this.
* config/i386/i386-builtin-types.def
((V2DF, V2DF, V2DF, INT, V2DF, UQI, INT),
(V4SF, V4SF, V4SF, INT, V4SF, UQI, INT)): New function type aliases.
* config/i386/i386-builtin.def (__builtin_ia32_getexpsd_mask_round,
__builtin_ia32_getexpss_mask_round, __builtin_ia32_getmantsd_mask_round,
__builtin_ia32_getmantss_mask_round): New builtins.
* config/i386/i386.c (V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI_INT,
V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI_INT): Handle new types.
(CODE_FOR_avx512f_vgetmantv2df_mask_round,
CODE_FOR_avx512f_vgetmantv4sf_mask_round): New cases.
* config/i386/sse.md
(avx512f_sgetexp<mode><round_saeonly_name>): Changed to ...
avx512f_sgetexp<mode><mask_scalar_name>
<round_saeonly_scalar_name> ... this.
(vgetexp<ssescalarmodesuffix>\t{<round_saeonly_op3>%2, %1, %0|
%0, %1, %2<round_saeonly_op3>}): Changed to ...
vgetexp<ssescalarmodesuffix>
\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %2<round_saeonly_scalar_mask_op3>} ... this.
(avx512f_vgetmant<mode><round_saeonly_name>): Changed to ...
avx512f_vgetmant<mode><mask_scalar_name>
<round_saeonly_scalar_name> ... this.
(vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|
%0, %1, %2<round_saeonly_op4>, %3}): Changed to ...
vgetmant<ssescalarmodesuffix>
\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|
%0<mask_scalar_operand4>, %1, %2
<round_saeonly_scalar_mask_op4>, %3} ... this.
* config/i386/subst.md (mask_scalar_operand4,
round_saeonly_scalar_mask_operand4, round_saeonly_scalar_mask_op4,
round_saeonly_scalar_nimm_predicate): New subst attributes.
gcc/testsuite/
* gcc.target/i386/avx512f-vgetexpsd-1.c (_mm_mask_getexp_sd,
_mm_maskz_getexp_sd, _mm_mask_getexp_round_sd,
_mm_maskz_getexp_round_sd): Test new intrinsics.
* gcc.target/i386/avx512f-vgetexpss-1.c (_mm_mask_getexp_ss,
_mm_maskz_getexp_ss, _mm_mask_getexp_round_ss,
_mm_maskz_getexp_round_ss): Ditto.
* gcc.target/i386/avx512f-vgetmantsd-1.c (_mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd): Ditto.
* gcc.target/i386/avx512f-vgetmantss-1.c (_mm_mask_getmant_ss,
_mm_maskz_getmant_ss, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss): Ditto.
* gcc.target/i386/avx512f-vgetexpsd-2.c (_mm_mask_getexp_sd,
_mm_maskz_getexp_sd, _mm_getexp_round_sd, _mm_mask_getexp_round_sd,
_mm_maskz_getexp_round_sd): New runtime tests.
* gcc.target/i386/avx512f-vgetexpss-2.c (_mm_mask_getexp_ss,
_mm_maskz_getexp_ss, _mm_getexp_round_ss, _mm_mask_getexp_round_ss,
_mm_maskz_getexp_round_ss): Ditto.
* gcc.target/i386/avx512f-vgetmantsd-2.c (_mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_getmant_round_sd, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd): Ditto.
* gcc.target/i386/avx512f-vgetmantss-2.c (_mm_mask_getmant_ss,
_mm_maskz_getmant_ss, _mm_getmant_round_ss, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss): Ditto.
* gcc.target/i386/avx-1.c (__builtin_ia32_getexpsd_mask_round,
__builtin_ia32_getexpss_mask_round, __builtin_ia32_getmantsd_mask_round,
__builtin_ia32_getmantss_mask_round): Test new builtins.
* gcc.target/i386/sse-13.c : Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c (_mm_maskz_getexp_round_sd,
_mm_maskz_getexp_round_ss, _mm_mask_getmant_round_sd,
_mm_maskz_getmant_round_sd, _mm_mask_getmant_round_ss,
_mm_maskz_getmant_round_ss, _mm_mask_getexp_round_sd,
_mm_mask_getexp_round_ss): Test new intrinsics.
* gcc.target/i386/testround-1.c: Ditto.
* gcc.target/i386/sse-22.c (_mm_maskz_getmant_round_sd,
_mm_maskz_getmant_round_ss, _mm_mask_getmant_round_sd,
_mm_mask_getmant_round_ss): Test new intrinsics
* gcc.target/i386/testimm-10.c (_mm_mask_getmant_sd,
_mm_maskz_getmant_sd, _mm_mask_getmant_ss,
_mm_maskz_getmant_ss): Test new intrinsics.
From-SVN: r250018
Julia Koval [Thu, 6 Jul 2017 11:03:35 +0000 (13:03 +0200)]
Remove old rounding code
gcc/
* gcc/config/i386/i386.c (ix86_erase_embedded_rounding):
Remove code for old rounding pattern.
From-SVN: r250017
Richard Earnshaw [Thu, 6 Jul 2017 10:00:44 +0000 (10:00 +0000)]
[arm] Fix warning in parsecpu.awk
In awk, single quotes within a quoted string do not need escaping.
The existing code causes awk to grumble in the build logs.
* config/arm/parsecpu.awk (gen_comm_data): Do not escape single quotes
in quoted strings.
From-SVN: r250016
Richard Earnshaw [Thu, 6 Jul 2017 09:49:19 +0000 (09:49 +0000)]
[arm] Fix cross-native builds
The patch I committed yesterday to remove some generated headers from
the source tree unfortunately has a dependency missing that is only
revealed when doing a cross-native or full Canadian cross build. The
gen* programs were missing a dependency on one of the generated
headers.
Fixed by adding an explicit dependency rule for GTM_H in the same way
as we do for TM_H.
* config/arm/t-arm (GTM_H): Add arm-cpu.h.
Checked that this restores cross-native building.
From-SVN: r250015
Christophe Lyon [Thu, 6 Jul 2017 08:12:33 +0000 (08:12 +0000)]
[testsuite] Add dg-require-stack-check
2017-07-06 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* doc/sourcebuild.texi (Test Directives, Variants of
dg-require-support): Add documentation for dg-require-stack-check.
gcc/testsuite/
* lib/target-supports-dg.exp (dg-require-stack-check): New.
* lib/target-supports.exp (check_stack_check_available): New.
* g++.dg/other/i386-9.C: Add dg-require-stack-check.
* gcc.c-torture/compile/stack-check-1.c: Likewise.
* gcc.dg/graphite/run-id-pr47653.c: Likewise.
* gcc.dg/pr47443.c: Likewise.
* gcc.dg/pr48134.c: Likewise.
* gcc.dg/pr70017.c: Likewise.
* gcc.target/aarch64/stack-checking.c: Likewise.
* gcc.target/arm/stack-checking.c: Likewise.
* gcc.target/i386/pr48723.c: Likewise.
* gcc.target/i386/pr55672.c: Likewise.
* gcc.target/i386/pr67265-2.c: Likewise.
* gcc.target/i386/pr67265.c: Likewise.
* gnat.dg/opt49.adb: Likewise.
* gnat.dg/stack_check1.adb: Likewise.
* gnat.dg/stack_check2.adb: Likewise.
* gnat.dg/stack_check3.adb: Likewise.
From-SVN: r250013
GCC Administrator [Thu, 6 Jul 2017 00:16:26 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r250012
Kelvin Nilsen [Wed, 5 Jul 2017 20:51:37 +0000 (20:51 +0000)]
re PR target/80103 (ICE in output_1144, at config/rs6000/vsx.md:2298)
gcc/testsuite/ChangeLog:
2017-07-05 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/80103
* gcc.target/powerpc/pr80103-1.c (void b): Correct spelling of
__attribute__.
From-SVN: r250008
Sebastian Peryt [Wed, 5 Jul 2017 16:44:18 +0000 (18:44 +0200)]
Scalar mask and round RTL templates
gcc/
* config/i386/subst.md (mask_scalar, round_scalar,
round_saeonly_scalar): New meta-templates.
(mask_scalar_name, mask_scalar_operand3, round_scalar_name,
round_scalar_mask_operand3, round_scalar_mask_op3,
round_scalar_constraint, round_scalar_prefix, round_saeonly_scalar_name,
round_saeonly_scalar_mask_operand3, round_saeonly_scalar_mask_op3,
round_saeonly_scalar_constraint,
round_saeonly_scalar_prefix): New subst attribute.
* config/i386/sse.md
(<sse>_vm<plusminus_insn><mode>3<mask_name><round_name>): Renamed to ...
<sse>_vm<plusminus_insn><mode>3<mask_scalar_name>
<round_scalar_name> ... this.
(<sse>_vm<multdiv_mnemonic><mode>3<mask_name><round_name>): Renamed to ...
<sse>_vm<multdiv_mnemonic><mode>3<mask_scalar_name>
<round_scalar_name> ... this.
(<sse>_vm<code><mode>3<mask_name><round_saeonly_name>): Renamed to ...
<sse>_vm<code><mode>3<mask_scalar_name>
<round_saeonly_scalar_name> ... this.
(v<plusminus_mnemonic><ssescalarmodesuffix>
\t{<round_mask_op3>%2, %1, %0<mask_operand3>|
%0<mask_operand3>, %1, %<iptr>2<round_mask_op3>}): Changed to ...
v<plusminus_mnemonic><ssescalarmodesuffix>
\t{<round_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %<iptr>2<round_scalar_mask_op3>} ... this.
(v<multdiv_mnemonic><ssescalarmodesuffix>
\t{<round_mask_op3>%2, %1, %0<mask_operand3>|
%0<mask_operand3>, %1, %<iptr>2<round_mask_op3>}): Changed to ...
v<multdiv_mnemonic><ssescalarmodesuffix>
\t{<round_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %<iptr>2<round_scalar_mask_op3>} ... this.
(v<maxmin_float><ssescalarmodesuffix>
\t{<round_saeonly_mask_op3>%2, %1, %0<mask_operand3>|
%0<mask_operand3>, %1, %<iptr>2<round_saeonly_mask_op3>}): Changed to ...
v<maxmin_float><ssescalarmodesuffix>
\t{<round_saeonly_scalar_mask_op3>%2, %1, %0<mask_scalar_operand3>|
%0<mask_scalar_operand3>, %1, %<iptr>2
<round_saeonly_scalar_mask_op3>} ... this.
gcc/testsuite/
* gcc.target/i386/avx512f-vaddsd-3.c: New test for mask 0 verification.
* gcc.target/i386/avx512f-vaddss-3.c: Ditto.
* gcc.target/i386/avx512f-vdivsd-3.c: Ditto.
* gcc.target/i386/avx512f-vdivss-3.c: Ditto.
* gcc.target/i386/avx512f-vmaxsd-3.c: Ditto.
* gcc.target/i386/avx512f-vmaxss-3.c: Ditto.
* gcc.target/i386/avx512f-vminsd-3.c: Ditto.
* gcc.target/i386/avx512f-vminss-3.c: Ditto.
* gcc.target/i386/avx512f-vmulsd-3.c: Ditto.
* gcc.target/i386/avx512f-vmulss-3.c: Ditto.
* gcc.target/i386/avx512f-vsubsd-3.c: Ditto.
* gcc.target/i386/avx512f-vsubss-3.c: Ditto.
From-SVN: r250006
Richard Earnshaw [Wed, 5 Jul 2017 15:32:47 +0000 (15:32 +0000)]
[ARM] Implement TARGET_FIXED_CONDITION_CODE_REGS
This patch implements TARGET_FIXED_CONDITION_CODE_REGS on ARM.
We have two main cases to consider: in Thumb1 code there are no
condition code registers, so we simply return false. For other
cases we set the the first pointer to CC_REGNUM and the second to
VFPCC_REGNUM iff generating hard-float code.
Running the CSiBE benchmark I see a couple of cases (both in the same
file) where this feature kicks in, so it's not a major change.
* config/arm/arm.c (arm_fixed_condition_code_regs): New function.
(TARGET_FIXED_CONDITION_CODE_REGS): Redefine.
From-SVN: r250005
Richard Sandiford [Wed, 5 Jul 2017 15:32:37 +0000 (15:32 +0000)]
Use SET_DECL_MODE in libcc1
2017-07-05 Richard Sandiford <richard.sandiford@linaro.org>
libcc1/
* libcp1plugin.cc (plugin_build_field): Use SET_DECL_MODE.
From-SVN: r250004
Richard Sandiford [Wed, 5 Jul 2017 15:29:27 +0000 (15:29 +0000)]
Remove enum before machine_mode
r216834 did a mass removal of "enum" before "machine_mode". This patch
removes some new uses that have been added since then.
2017-07-05 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* combine.c (simplify_if_then_else): Remove "enum" before
"machine_mode".
* compare-elim.c (can_eliminate_compare): Likewise.
* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type):
Likewise.
(aarch64_lookup_simd_builtin_type): Likewise.
(aarch64_simd_builtin_type): Likewise.
(aarch64_init_simd_builtin_types): Likewise.
(aarch64_simd_expand_args): Likewise.
* config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist):
Likewise.
(aarch64_reverse_mask): Likewise.
(aarch64_simd_emit_reg_reg_move): Likewise.
(aarch64_gen_adjusted_ldpstp): Likewise.
(aarch64_ccmp_mode_to_code): Likewise.
(aarch64_operands_ok_for_ldpstp): Likewise.
(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
* config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class):
Likewise.
(aarch64_min_divisions_for_recip_mul): Likewise.
(aarch64_reassociation_width): Likewise.
(aarch64_get_condition_code_1): Likewise.
(aarch64_simd_emit_reg_reg_move): Likewise.
(aarch64_simd_attr_length_rglist): Likewise.
(aarch64_reverse_mask): Likewise.
(aarch64_operands_ok_for_ldpstp): Likewise.
(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
(aarch64_gen_adjusted_ldpstp): Likewise.
* config/aarch64/cortex-a57-fma-steering.c (fma_node::rename):
Likewise.
* config/arc/arc.c (legitimate_offset_address_p): Likewise.
* config/arm/arm-builtins.c (arm_simd_builtin_std_type): Likewise.
(arm_lookup_simd_builtin_type): Likewise.
(arm_simd_builtin_type): Likewise.
(arm_init_simd_builtin_types): Likewise.
(arm_expand_builtin_args): Likewise.
* config/arm/arm-protos.h (arm_expand_builtin): Likewise.
* config/ft32/ft32.c (ft32_libcall_value): Likewise.
(ft32_setup_incoming_varargs): Likewise.
(ft32_function_arg): Likewise.
(ft32_function_arg_advance): Likewise.
(ft32_pass_by_reference): Likewise.
(ft32_arg_partial_bytes): Likewise.
(ft32_valid_pointer_mode): Likewise.
(ft32_addr_space_pointer_mode): Likewise.
(ft32_addr_space_legitimate_address_p): Likewise.
* config/i386/i386-protos.h (ix86_operands_ok_for_move_multiple):
Likewise.
* config/i386/i386.c (ix86_setup_incoming_vararg_bounds): Likewise.
(ix86_emit_outlined_ms2sysv_restore): Likewise.
(iamcu_alignment): Likewise.
(canonicalize_vector_int_perm): Likewise.
(ix86_noce_conversion_profitable_p): Likewise.
(ix86_mpx_bound_mode): Likewise.
(ix86_operands_ok_for_move_multiple): Likewise.
* config/microblaze/microblaze-protos.h
(microblaze_expand_conditional_branch_reg): Likewise.
* config/microblaze/microblaze.c
(microblaze_expand_conditional_branch_reg): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_init_hard_regno_mode_ok):
Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_invalid_binary_op): Likewise.
(fusion_p9_p): Likewise.
(emit_fusion_p9_load): Likewise.
(emit_fusion_p9_store): Likewise.
* config/riscv/riscv-protos.h (riscv_regno_mode_ok_for_base_p):
Likewise.
(riscv_hard_regno_mode_ok_p): Likewise.
(riscv_address_insns): Likewise.
(riscv_split_symbol): Likewise.
(riscv_legitimize_move): Likewise.
(riscv_function_value): Likewise.
(riscv_hard_regno_nregs): Likewise.
(riscv_expand_builtin): Likewise.
* config/riscv/riscv.c (riscv_build_integer_1): Likewise.
(riscv_build_integer): Likewise.
(riscv_split_integer): Likewise.
(riscv_legitimate_constant_p): Likewise.
(riscv_cannot_force_const_mem): Likewise.
(riscv_regno_mode_ok_for_base_p): Likewise.
(riscv_valid_base_register_p): Likewise.
(riscv_valid_offset_p): Likewise.
(riscv_valid_lo_sum_p): Likewise.
(riscv_classify_address): Likewise.
(riscv_legitimate_address_p): Likewise.
(riscv_address_insns): Likewise.
(riscv_load_store_insns): Likewise.
(riscv_force_binary): Likewise.
(riscv_split_symbol): Likewise.
(riscv_force_address): Likewise.
(riscv_legitimize_address): Likewise.
(riscv_move_integer): Likewise.
(riscv_legitimize_const_move): Likewise.
(riscv_legitimize_move): Likewise.
(riscv_address_cost): Likewise.
(riscv_subword): Likewise.
(riscv_output_move): Likewise.
(riscv_canonicalize_int_order_test): Likewise.
(riscv_emit_int_order_test): Likewise.
(riscv_function_arg_boundary): Likewise.
(riscv_pass_mode_in_fpr_p): Likewise.
(riscv_pass_fpr_single): Likewise.
(riscv_pass_fpr_pair): Likewise.
(riscv_get_arg_info): Likewise.
(riscv_function_arg): Likewise.
(riscv_function_arg_advance): Likewise.
(riscv_arg_partial_bytes): Likewise.
(riscv_function_value): Likewise.
(riscv_pass_by_reference): Likewise.
(riscv_setup_incoming_varargs): Likewise.
(riscv_print_operand): Likewise.
(riscv_elf_select_rtx_section): Likewise.
(riscv_save_restore_reg): Likewise.
(riscv_for_each_saved_reg): Likewise.
(riscv_register_move_cost): Likewise.
(riscv_hard_regno_mode_ok_p): Likewise.
(riscv_hard_regno_nregs): Likewise.
(riscv_class_max_nregs): Likewise.
(riscv_memory_move_cost): Likewise.
* config/rl78/rl78-protos.h (rl78_split_movsi): Likewise.
* config/rl78/rl78.c (rl78_split_movsi): Likewise.
(rl78_addr_space_address_mode): Likewise.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_invalid_binary_op): Likewise.
(fusion_p9_p): Likewise.
(emit_fusion_p9_load): Likewise.
(emit_fusion_p9_store): Likewise.
* config/visium/visium-protos.h (prepare_move_operands): Likewise.
(ok_for_simple_move_operands): Likewise.
(ok_for_simple_move_strict_operands): Likewise.
(ok_for_simple_arith_logic_operands): Likewise.
(visium_legitimize_reload_address): Likewise.
(visium_select_cc_mode): Likewise.
(output_cbranch): Likewise.
(visium_split_double_move): Likewise.
(visium_expand_copysign): Likewise.
(visium_expand_int_cstore): Likewise.
(visium_expand_fp_cstore): Likewise.
* config/visium/visium.c (visium_pass_by_reference): Likewise.
(visium_function_arg): Likewise.
(visium_function_arg_advance): Likewise.
(visium_libcall_value): Likewise.
(visium_setup_incoming_varargs): Likewise.
(visium_legitimate_constant_p): Likewise.
(visium_legitimate_address_p): Likewise.
(visium_legitimize_address): Likewise.
(visium_secondary_reload): Likewise.
(visium_register_move_cost): Likewise.
(visium_memory_move_cost): Likewise.
(prepare_move_operands): Likewise.
(ok_for_simple_move_operands): Likewise.
(ok_for_simple_move_strict_operands): Likewise.
(ok_for_simple_arith_logic_operands): Likewise.
(visium_function_value_1): Likewise.
(rtx_ok_for_offset_p): Likewise.
(visium_legitimize_reload_address): Likewise.
(visium_split_double_move): Likewise.
(visium_expand_copysign): Likewise.
(visium_expand_int_cstore): Likewise.
(visium_expand_fp_cstore): Likewise.
(visium_split_cstore): Likewise.
(visium_select_cc_mode): Likewise.
(visium_split_cbranch): Likewise.
(output_cbranch): Likewise.
(visium_print_operand_address): Likewise.
* expmed.c (flip_storage_order): Likewise.
* expmed.h (emit_cstore): Likewise.
(flip_storage_order): Likewise.
* genrecog.c (validate_pattern): Likewise.
* hsa-gen.c (gen_hsa_addr): Likewise.
* internal-fn.c (expand_arith_overflow): Likewise.
* ira-color.c (allocno_copy_cost_saving): Likewise.
* lra-assigns.c (find_hard_regno_for_1): Likewise.
* lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise.
(process_invariant_for_inheritance): Likewise.
* lra-eliminations.c (move_plus_up): Likewise.
* omp-low.c (lower_oacc_reductions): Likewise.
* simplify-rtx.c (simplify_subreg): Likewise.
* target.def (TARGET_SETUP_INCOMING_VARARG_BOUNDS): Likewise.
(TARGET_CHKP_BOUND_MODE): Likewise..
* targhooks.c (default_chkp_bound_mode): Likewise.
(default_setup_incoming_vararg_bounds): Likewise.
* targhooks.h (default_chkp_bound_mode): Likewise.
(default_setup_incoming_vararg_bounds): Likewise.
* tree-ssa-math-opts.c (divmod_candidate_p): Likewise.
* tree-vect-loop.c (calc_vec_perm_mask_for_shift): Likewise.
(have_whole_vector_shift): Likewise.
* tree-vect-stmts.c (vectorizable_load): Likewise.
* doc/tm.texi: Regenerate.
gcc/brig/
* brig-c.h (brig_type_for_mode): Remove "enum" before "machine_mode".
* brig-lang.c (brig_langhook_type_for_mode): Likewise.
gcc/jit/
* dummy-frontend.c (jit_langhook_type_for_mode): Remove "enum" before
"machine_mode".
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r250003
Georg-Johann Lay [Wed, 5 Jul 2017 13:57:28 +0000 (13:57 +0000)]
Graceful degrade if Binutils PR21472 is not available.
gcc/
Graceful degrade if Binutils PR21472 is not available.
PR target/81072
* configure.ac [target=avr]: WARN instead of ERROR if avrxmega3
.rodata in flash test fails.
(HAVE_LD_AVR_AVRXMEGA3_RODATA_IN_FLASH): Define it if test passes.
* confgure: Regenerate.
* config.in: Regenerate.
* config/avr/avr.c (avr_asm_named_section)
[HAVE_LD_AVR_AVRXMEGA3_RODATA_IN_FLASH]: Only trigger
__do_copy_data for stuff in .rodata if flash_pm_offset = 0.
(avr_asm_init_sections): Same.
From-SVN: r250000
Ramana Radhakrishnan [Wed, 5 Jul 2017 12:58:46 +0000 (12:58 +0000)]
[Patch ARM] Remove %? string from some Advanced SIMD patterns.
Advanced SIMD patterns are not predicable, thus they should not have
%? in their output templates. Found when auditing the code for
something else. This has been in my tree for sometime , bootstrapped
and regression tested on armhf for armv7ve+simd as the architectural
base.
Applied to trunk
<DATE> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/neon.md (fma<VCVTF:mode>4): Remove %?.
(fma<VH:mode>4_intrinsic): Likewise.
(*fmsub<VCVTF:mode>4): Likewise.
(*fmsub<VH:mode>4_intrinsic): Likewise.
regards
Ramana
From-SVN: r249999
Georg-Johann Lay [Wed, 5 Jul 2017 12:38:51 +0000 (12:38 +0000)]
Move ChangeLog entry to testsuite.
From-SVN: r249997
projects / gcc.git / log