Ron Dreslinski [Thu, 12 Oct 2006 17:45:28 +0000 (13:45 -0400)]
Another memleak in the memtester (need [] with the delete)
src/cpu/memtest/memtest.cc:
Another memleak in the memtester
--HG--
extra : convert_revision :
f7ab079e90d578fb6b9d1ff238d049fcce55b01b
Ron Dreslinski [Thu, 12 Oct 2006 17:43:12 +0000 (13:43 -0400)]
Fix a memory leak in the memtester
--HG--
extra : convert_revision :
93062b0f1a3ba7a5210e2f27099f20ae8f66522b
Ron Dreslinski [Thu, 12 Oct 2006 17:33:21 +0000 (13:33 -0400)]
Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
--HG--
extra : convert_revision :
fc78192863afb11fc7c591fba169021b9e127d16
Ron Dreslinski [Thu, 12 Oct 2006 01:04:11 +0000 (21:04 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
b6224624ea493531e5ecc161bede7433f96d8a0f
Ron Dreslinski [Thu, 12 Oct 2006 00:54:06 +0000 (20:54 -0400)]
Make default ID unique (not broadcast)
Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
--HG--
extra : convert_revision :
9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
Ron Dreslinski [Wed, 11 Oct 2006 23:47:11 +0000 (19:47 -0400)]
Forgot to mark myself as on the retry list
--HG--
extra : convert_revision :
c20170320a284a7bf143a929e4d3aa1475a8bfe0
Korey Sewell [Wed, 11 Oct 2006 23:26:56 +0000 (19:26 -0400)]
add spec2k tests
--HG--
extra : convert_revision :
619d6af7013b597ade6440f8cf84d6d099e31763
Ron Dreslinski [Wed, 11 Oct 2006 23:25:48 +0000 (19:25 -0400)]
Fix bus in FS mode.
src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
--HG--
extra : convert_revision :
fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
Korey Sewell [Wed, 11 Oct 2006 23:07:10 +0000 (19:07 -0400)]
add bzip test-prog
--HG--
extra : convert_revision :
f5197172b094d59ced84423eb34c31ddf23689ee
Ron Dreslinski [Wed, 11 Oct 2006 22:28:33 +0000 (18:28 -0400)]
More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
--HG--
extra : convert_revision :
43f880e29215776167c16ea90793ebf8122c785b
Ron Dreslinski [Wed, 11 Oct 2006 05:59:38 +0000 (01:59 -0400)]
Update for Atomic Coherece with Gabes bus
--HG--
extra : convert_revision :
6a23052056d1c61cba0a4c77f1030cee419c6fa3
Ron Dreslinski [Wed, 11 Oct 2006 05:18:20 +0000 (01:18 -0400)]
Interesting memtest finally.
Get over 500,000 reads on each of 8 testers before memory leak becomes large.
tests/configs/memtest.py:
Update test to be more interesting
--HG--
extra : convert_revision :
4258b798fbeeed2a376f1bfac100a109eb05620e
Ron Dreslinski [Wed, 11 Oct 2006 05:02:18 +0000 (01:02 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
70187b8f04d0f8424512f64bdade05bf1aca85a3
Ron Dreslinski [Wed, 11 Oct 2006 05:01:40 +0000 (01:01 -0400)]
Use bus response time paramteres
Fix bug with deadlocking
src/mem/cache/base_cache.cc:
Make sure to not wait anymore
--HG--
extra : convert_revision :
5f7b44a1c475820b9862275a0d6113ec2991735d
Gabe Black [Wed, 11 Oct 2006 04:54:47 +0000 (00:54 -0400)]
Don't call recvRetry if the bus is busy anyway. This takes care of a corner case as well when dealing with grants that aren't used.
--HG--
extra : convert_revision :
38f7ef1b41477fb2a2438387ef3a81cccd3e7a8a
Ron Dreslinski [Wed, 11 Oct 2006 04:31:40 +0000 (00:31 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
d2d19b27533f35c6570ee84c6c83b2919f27b97f
Gabe Black [Wed, 11 Oct 2006 04:26:21 +0000 (00:26 -0400)]
Make the bus work if the other sides recvRetry doesn't call sendTiming for some reason.
--HG--
extra : convert_revision :
e722ddb0354a5c021dc7c44a3e2f0a64e962442b
Ron Dreslinski [Wed, 11 Oct 2006 04:19:31 +0000 (00:19 -0400)]
When turning asserts into if's don't forget to invert.
src/mem/cache/base_cache.cc:
When turning asserts into if's don't forget to invert.
Must be too sleepy.
--HG--
extra : convert_revision :
ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
Ron Dreslinski [Wed, 11 Oct 2006 04:13:53 +0000 (00:13 -0400)]
Writebacks can be pulled out from under the BusRequest when snoops of uprgades to owned blocks hit in the WB buffer
--HG--
extra : convert_revision :
f0502836a79ce303150daa7e571badb0bce3a97a
Ron Dreslinski [Wed, 11 Oct 2006 03:53:10 +0000 (23:53 -0400)]
Only issue responses if we aren;t already blocked
--HG--
extra : convert_revision :
511c0bcd44b93d5499eefa8399f36ef8b6607311
Ron Dreslinski [Wed, 11 Oct 2006 03:37:14 +0000 (23:37 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
--HG--
extra : convert_revision :
18608114350c466a56ab499ae523b01fcb2f6ef2
Gabe Black [Wed, 11 Oct 2006 03:28:33 +0000 (23:28 -0400)]
Make the bus is occupied for none broadcast packets as well.
--HG--
extra : convert_revision :
aef3c625172e92be8f29c4c57077fefee43046bb
Ron Dreslinski [Wed, 11 Oct 2006 02:52:52 +0000 (22:52 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
--HG--
extra : convert_revision :
eaae105025635c37af06cf72bb061ce82def9dc9
Ron Dreslinski [Wed, 11 Oct 2006 02:50:36 +0000 (22:50 -0400)]
Debugging info
src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
--HG--
extra : convert_revision :
a6c4b452466a8e0b50a86e886833cb6e29edc748
Gabe Black [Wed, 11 Oct 2006 02:10:08 +0000 (22:10 -0400)]
Put in an accounting mechanism and an assert to make sure something doesn't try to send another packet while it's still waiting for the bus.
--HG--
extra : convert_revision :
4a2b83111e49f71ca27e05c98b55bc3bac8d9f53
Gabe Black [Tue, 10 Oct 2006 21:49:31 +0000 (17:49 -0400)]
Fixed a corner case and simplified the logic in Packet::intersect.
--HG--
extra : convert_revision :
b57c31ca7c220e701d34e02bb07ce392370e4428
Ron Dreslinski [Tue, 10 Oct 2006 21:32:24 +0000 (17:32 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
Ron Dreslinski [Tue, 10 Oct 2006 21:25:50 +0000 (17:25 -0400)]
Some more code cleanup
src/mem/cache/base_cache.cc:
Add sanity checks
src/mem/cache/base_cache.hh:
Fix for retry mechanism
--HG--
extra : convert_revision :
9298e32e64194b1ef3fe51242595eaa56dcbbcfd
Gabe Black [Tue, 10 Oct 2006 21:24:03 +0000 (17:24 -0400)]
Changed the bus to use a bool to keep track of retries rather than a pointer
src/mem/tport.cc:
minor formatting tweak
--HG--
extra : convert_revision :
7391d142815c5876fcc0f991bd053e6a1781c101
Gabe Black [Tue, 10 Oct 2006 21:18:09 +0000 (17:18 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
aa59d3169d84bcd13b8c97f22b52aeef43dc33c3
Ron Dreslinski [Tue, 10 Oct 2006 21:10:56 +0000 (17:10 -0400)]
Fix some more mem leaks, still some left
Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
--HG--
extra : convert_revision :
3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
Gabe Black [Tue, 10 Oct 2006 19:56:18 +0000 (15:56 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
4036e8447fb3038d93285c6582900210d7d88d67
Ron Dreslinski [Tue, 10 Oct 2006 19:53:25 +0000 (15:53 -0400)]
Fix cshr Retry's
Fix Upgrades being blocked by slave
--HG--
extra : convert_revision :
cca98a38e32233145163577500f1362cd807ab15
Gabe Black [Tue, 10 Oct 2006 19:04:55 +0000 (15:04 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
6027c395af044858465eafd3ea78bcfe4c923bcc
Kevin Lim [Tue, 10 Oct 2006 15:04:21 +0000 (11:04 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision :
8b27fc92f8aafe691d70dc654bff3798abf8e755
Kevin Lim [Tue, 10 Oct 2006 15:04:05 +0000 (11:04 -0400)]
Updates refs.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
Update refs.
--HG--
extra : convert_revision :
5341341507ddbe1211992e5f72013d7be0000bae
Ron Dreslinski [Tue, 10 Oct 2006 06:36:04 +0000 (02:36 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
87f83c4edf6ea51adc767d98265d1e74c0fbb46f
Ron Dreslinski [Tue, 10 Oct 2006 06:33:30 +0000 (02:33 -0400)]
Yet another fix to the HasData command attribute.
--HG--
extra : convert_revision :
dcf0d7eafa5168591c2b374b452821ca34dde7f9
Ron Dreslinski [Tue, 10 Oct 2006 06:21:03 +0000 (02:21 -0400)]
Actually set the HasData attribute on Read Responses
--HG--
extra : convert_revision :
129dadbf8091ab00fb7f16eace59df265fc3718c
Ron Dreslinski [Tue, 10 Oct 2006 06:00:37 +0000 (02:00 -0400)]
Fix another merge issue
--HG--
extra : convert_revision :
2b33da5e8578ea6a8bdd2d89f183c2e6b942b0fc
Ron Dreslinski [Tue, 10 Oct 2006 05:57:57 +0000 (01:57 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/packet.hh:
Hand merge code
--HG--
extra : convert_revision :
d659418f24f4f4bf9867fec8573a5d227c0dfcea
Kevin Lim [Tue, 10 Oct 2006 05:49:46 +0000 (01:49 -0400)]
Two minor fixes.
configs/common/SysPaths.py:
Undo accidental change.
src/SConscript:
Fix.
--HG--
extra : convert_revision :
665b186cff7d8ae560601ced7ae407a41a16cfea
Ron Dreslinski [Tue, 10 Oct 2006 05:32:18 +0000 (01:32 -0400)]
Fix several bugs pertaining to upgrades/mem leaks.
src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
A
\bFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
--HG--
extra : convert_revision :
fcb4f17dd58b537bb4f67a8c835f50e455e8c688
Gabe Black [Tue, 10 Oct 2006 04:49:27 +0000 (00:49 -0400)]
Fixed a bug where a packet was attempted to be sent even though another packet was waiting for the bus.
--HG--
extra : convert_revision :
29f7a4f676884330d7b7e93517dea85fc7bbf678
Gabe Black [Tue, 10 Oct 2006 03:24:21 +0000 (23:24 -0400)]
Fixes to the bus, and added fields to the packet.
src/mem/bus.cc:
Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
Remove the occupyBus function.
src/mem/packet.hh:
Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.
--HG--
extra : convert_revision :
cfc7670a33913d48a04d02c6d2448290a51f2d3c
Kevin Lim [Tue, 10 Oct 2006 02:59:56 +0000 (22:59 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
--HG--
extra : convert_revision :
a58cc439eb5e8f900d175ed8b5a85b6c8723e558
Kevin Lim [Tue, 10 Oct 2006 02:49:58 +0000 (22:49 -0400)]
Comment out code that messed up SMT (but will be needed eventually).
src/cpu/o3/cpu.cc:
Comment out reseting CPU structures for now. This can be updated to work in the future.
--HG--
extra : convert_revision :
bc1a86e2fe47da5acb14ba8b64568b0355431f1c
Ron Dreslinski [Tue, 10 Oct 2006 00:18:00 +0000 (20:18 -0400)]
Handle NACK's that occur from devices on the same bus.
Not fully implemented yet, but good enough for single level cache coherence
src/mem/packet.hh:
Add a bit to distinguish invalidates and upgrades
--HG--
extra : convert_revision :
5bf50d535857cea37fbdaf7993915d1332cb757e
Gabe Black [Mon, 9 Oct 2006 23:55:49 +0000 (19:55 -0400)]
updated reference output
--HG--
extra : convert_revision :
daf11630290c7a84d63bf37cafa44210861c4bf2
Gabe Black [Mon, 9 Oct 2006 23:35:53 +0000 (19:35 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
2adde42edead2cedeeba60cc0d2697a2d58682be
Ron Dreslinski [Mon, 9 Oct 2006 23:20:28 +0000 (19:20 -0400)]
Fix a typo preventing compilation
--HG--
extra : convert_revision :
9158d81231cd1d083393576744ce80afd0b74867
Ron Dreslinski [Mon, 9 Oct 2006 23:15:24 +0000 (19:15 -0400)]
Fix how upgrades work.
Remove some dead code.
src/mem/cache/cache_impl.hh:
Upgrades don't need a response.
Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
Upgrades don't require a response
--HG--
extra : convert_revision :
dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
Kevin Lim [Mon, 9 Oct 2006 23:14:14 +0000 (19:14 -0400)]
Be sure to delete packet and sender state if the cache is blocked.
src/cpu/o3/lsq_unit.hh:
Be sure to delete data if the cache is blocked.
--HG--
extra : convert_revision :
fafbcfb8937e85555823942e69e798e557a600e5
Kevin Lim [Mon, 9 Oct 2006 23:13:06 +0000 (19:13 -0400)]
Fix caches plus sampling switch over.
src/cpu/o3/cpu.cc:
Fix up caches plus sampling switch over.
--HG--
extra : convert_revision :
49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
Ron Dreslinski [Mon, 9 Oct 2006 22:52:20 +0000 (18:52 -0400)]
One step closet to having NACK's work.
src/cpu/memtest/memtest.cc:
Fix functional return path
src/cpu/memtest/memtest.hh:
Add snoop ranges in
src/mem/cache/base_cache.cc:
Properly signal NACKED
src/mem/cache/cache_impl.hh:
Catch nacked packet and panic for now
--HG--
extra : convert_revision :
59a64e82254dfa206681c5f987e6939167754d67
Gabe Black [Mon, 9 Oct 2006 22:19:35 +0000 (18:19 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
8267487b935eaf11665841ace3a5c664751b53b0
Gabe Black [Mon, 9 Oct 2006 22:12:45 +0000 (18:12 -0400)]
Potentially functional partially timed bandwidth limitted bus model.
src/mem/bus.cc:
Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
Put snooping back into recvTiming and not in it's own function.
--HG--
extra : convert_revision :
fd031b7e6051a5be07ed6926454fde73b1739dc6
Ron Dreslinski [Mon, 9 Oct 2006 21:31:58 +0000 (17:31 -0400)]
Update configs for cpu_id
tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
Update config for cpu_id
--HG--
extra : convert_revision :
32a1971997920473164ba12f2b121cb640bad7ac
Ron Dreslinski [Mon, 9 Oct 2006 21:30:54 +0000 (17:30 -0400)]
Fix a typo in the printf
--HG--
extra : convert_revision :
bfa8ffae0a9bef25ceca168ff376ba816abf23f3
Ron Dreslinski [Mon, 9 Oct 2006 21:25:43 +0000 (17:25 -0400)]
Multiprogrammed workload, need to generate ref's for it yet. But Nate wanted the config.
Not sure on the naming convention for tests.
--HG--
extra : convert_revision :
052c2fc95dc7e2bbd78d4a177600d7ec2a530a4c
Ron Dreslinski [Mon, 9 Oct 2006 21:18:34 +0000 (17:18 -0400)]
Fix a bitwise operation that was accidentally a logical operation.
--HG--
extra : convert_revision :
30f64bcb6bea47fd8cd6d77b0df17eff04dbbad0
Ron Dreslinski [Mon, 9 Oct 2006 21:13:50 +0000 (17:13 -0400)]
Make memtest work with 8 memtesters
src/mem/physical.cc:
Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
Make memtester have a way to connect functionally
tests/configs/memtest.py:
Properly create 8 memtesters and connect them to the memory system
--HG--
extra : convert_revision :
e5a2dd9c8918d58051b553b5c6a14785d48b34ca
Ron Dreslinski [Mon, 9 Oct 2006 20:48:58 +0000 (16:48 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
b4cb1702ffa2fca298cfde47683cac019e1da900
Ron Dreslinski [Mon, 9 Oct 2006 20:47:55 +0000 (16:47 -0400)]
Add more DPRINTF's fix a supply condition.
src/mem/cache/cache_impl.hh:
Add more usefull DPRINTF's
REmove the PC to get rid of asserts
--HG--
extra : convert_revision :
3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
Ron Dreslinski [Mon, 9 Oct 2006 20:37:02 +0000 (16:37 -0400)]
Set size properly on uncache accesses
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
--HG--
extra : convert_revision :
2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
Kevin Lim [Mon, 9 Oct 2006 15:01:19 +0000 (11:01 -0400)]
Fix outstanding bug (FS#158).
src/cpu/o3/cpu.cc:
Extra debugging, fix a bug brought up on bug tracker.
--HG--
extra : convert_revision :
23f8b166ba0d0af54e15b651ed28f59a1bc9d2f2
Kevin Lim [Mon, 9 Oct 2006 15:00:31 +0000 (11:00 -0400)]
Fix checker bug.
src/cpu/checker/thread_context.hh:
Checker's TC should only copy state, and not fully take over from the old context (prevents it from accidentally stealing the quiesce event).
--HG--
extra : convert_revision :
5760f9c5bae749f8d1df35e4c898df13e41b0224
Ron Dreslinski [Mon, 9 Oct 2006 05:04:37 +0000 (01:04 -0400)]
Have cpus send snoop ranges
--HG--
extra : convert_revision :
2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
Ron Dreslinski [Mon, 9 Oct 2006 04:31:24 +0000 (00:31 -0400)]
Put a check in so people know not to create more than 8 memtesters.
--HG--
extra : convert_revision :
41ab297dc681b2601be1df33aba30c39f49466d8
Ron Dreslinski [Mon, 9 Oct 2006 04:28:26 +0000 (00:28 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
77b06379a520dd91f124c0a543e30ec3a9cd1452
Ron Dreslinski [Mon, 9 Oct 2006 04:27:41 +0000 (00:27 -0400)]
Don't create a response if one isn't needed.
--HG--
extra : convert_revision :
37bd230f527f64eb12779157869aae9dcfdde7fd
Ron Dreslinski [Mon, 9 Oct 2006 04:27:03 +0000 (00:27 -0400)]
Don't block responses even if the cache is blocked.
--HG--
extra : convert_revision :
a1558eb55806b2a3e7e63249601df2c143e2235d
Ron Dreslinski [Mon, 9 Oct 2006 04:26:10 +0000 (00:26 -0400)]
Update the Memtester, commit a config file/test for it.
src/cpu/SConscript:
Add memtester to the compilation environment.
Someone who knows this better should make the MemTest a cpu model parameter.
For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
Update memtest python description
--HG--
extra : convert_revision :
d6a63e08fda0975a7abfb23814a86a0caf53e482
Lisa Hsu [Mon, 9 Oct 2006 04:12:16 +0000 (00:12 -0400)]
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd.
so you can restore by a command line like this:
m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3
configs/example/fs.py:
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.
--HG--
extra : convert_revision :
bf9c8d3265a3875cdfb6a878005baa7ae29af90d
Kevin Lim [Mon, 9 Oct 2006 04:09:44 +0000 (00:09 -0400)]
Update memory assertion to check for whole range.
src/mem/physical.cc:
Update assertion to check for full range.
--HG--
extra : convert_revision :
ee815702ba4dd6ae1169c0595c978dd153014c73
Lisa Hsu [Mon, 9 Oct 2006 03:19:03 +0000 (23:19 -0400)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
a0775bf59ff7049b76917b1ab551bc28efd56b3d
Lisa Hsu [Mon, 9 Oct 2006 03:18:19 +0000 (23:18 -0400)]
post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.
src/dev/ide_ctrl.cc:
this range change needs to be done for all pio devices, not just the ide.
src/dev/pcidev.cc:
range change needs to be done at here, not in the ide_ctrl file.
--HG--
extra : convert_revision :
60c65c55e965b02d671dba7aa8793e5a81f40348
Lisa Hsu [Mon, 9 Oct 2006 03:16:40 +0000 (23:16 -0400)]
add in serialization of AtomicSimpleCPU _status. This is needed because right now unserializing breaks an assert since CPU status is not saved. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
src/cpu/simple/atomic.cc:
add in serialization of AtomicSimpleCPU _status. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
--HG--
extra : convert_revision :
7000f660aecea6fef712bf81853d9a7b90d625ee
Steve Reinhardt [Mon, 9 Oct 2006 02:11:19 +0000 (19:11 -0700)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision :
755af6a54b309417afbc022544ee72f96bdac493
Steve Reinhardt [Mon, 9 Oct 2006 02:11:06 +0000 (19:11 -0700)]
Set cpu_id params (required by ll/sc code now).
--HG--
extra : convert_revision :
e0f7ccbeccca191a8edb54494d2b4f9369e9914c
Lisa Hsu [Mon, 9 Oct 2006 02:05:34 +0000 (22:05 -0400)]
update for m5 base linux. (the last changes were for the latest m5hack, i.e. with nate's stuff in it).
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
update for m5 base linux.
--HG--
extra : convert_revision :
c78a1748bf8a0950450c29a7b96bb8735c1bb3d2
Steve Reinhardt [Mon, 9 Oct 2006 01:26:59 +0000 (18:26 -0700)]
Fixes for Port proxies and proxy parameters.
--HG--
extra : convert_revision :
76b16fe2926611bd1c12c8ad7392355ad30a5138
Ron Dreslinski [Mon, 9 Oct 2006 01:08:27 +0000 (21:08 -0400)]
Update stats for functional path fix
--HG--
extra : convert_revision :
0f38abab28e7e44f1dc748c25938185651dd1b7d
Ron Dreslinski [Mon, 9 Oct 2006 00:47:50 +0000 (20:47 -0400)]
Make sure to propogate sendFunctional calls with functional not atomic.
src/mem/cache/cache_impl.hh:
Fix a error case by putting a panic in.
Make sure to propogate sendFunctional calls with functional not atomic.
--HG--
extra : convert_revision :
05d03f729a40cfa3ecb68bcba172eb560b24e897
Ron Dreslinski [Mon, 9 Oct 2006 00:30:42 +0000 (20:30 -0400)]
Fixes for functional path.
If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
Make the fuctional path do the correct tye of snoop
--HG--
extra : convert_revision :
70d09f954b907a8aa9b8137579cd2b06e02ae2ff
Gabe Black [Sun, 8 Oct 2006 23:14:09 +0000 (19:14 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
src/mem/bus.cc:
Hand merged. Needs to be fixed
--HG--
extra : convert_revision :
df03219ccfd18431cc726a063bd29d30554944a1
Ron Dreslinski [Sun, 8 Oct 2006 23:05:48 +0000 (19:05 -0400)]
Only respond if the pkt needs a response.
Fix an issue with memory handling writebacks.
src/mem/cache/base_cache.hh:
src/mem/tport.cc:
Only respond if the pkt needs a response.
src/mem/physical.cc:
Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.
--HG--
extra : convert_revision :
7601987a7923e54a6d1a168def4f8133d8de19fd
Ron Dreslinski [Sun, 8 Oct 2006 22:49:30 +0000 (18:49 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
f3067efb7f3ff30158d541dfc52de4ea8edae576
Ron Dreslinski [Sun, 8 Oct 2006 22:48:03 +0000 (18:48 -0400)]
Move away from using the statusChange function on snoops. Clean up snooping code in general.
--HG--
extra : convert_revision :
5a57bfd7742a212047fc32e8cae0dc602fdc915c
Gabe Black [Sun, 8 Oct 2006 22:45:21 +0000 (18:45 -0400)]
missing else
--HG--
extra : convert_revision :
8fe0e00dc3ae70b4449a78c15dd249939e644f02
Gabe Black [Sun, 8 Oct 2006 22:44:49 +0000 (18:44 -0400)]
bus changes
src/mem/bus.cc:
src/mem/bus.hh:
minor fix and some formatting changes
src/python/m5/objects/Bus.py:
changed bits to bytes
--HG--
extra : convert_revision :
dcd22205604b7a2727eaf2094084c4858f3589c5
Steve Reinhardt [Sun, 8 Oct 2006 21:48:24 +0000 (14:48 -0700)]
Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().
--HG--
extra : convert_revision :
f22ce3221d270ecf8631d3dcaed05753accd5461
Steve Reinhardt [Sun, 8 Oct 2006 21:07:23 +0000 (17:07 -0400)]
Update ref stats: ll/sc, cpu_id, new kernel (?)
--HG--
extra : convert_revision :
060cb7319c4474429917a6347a9a47f390208ec8
Gabe Black [Sun, 8 Oct 2006 18:09:13 +0000 (14:09 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
1749397443ccb320d32f8dd23c71ed0431d30cb7
Gabe Black [Sun, 8 Oct 2006 18:08:58 +0000 (14:08 -0400)]
A possible implementation of a multiplexed bus.
--HG--
extra : convert_revision :
3c560eda12ffd8ca539c91024baf2770b963ede8
Gabe Black [Sun, 8 Oct 2006 18:04:49 +0000 (14:04 -0400)]
Add in HasData, and move the define of NUM_MEM_CMDS to a more visible location.
--HG--
extra : convert_revision :
4379efe892ca0a39363ee04009e1bbb8c8f77afa
Steve Reinhardt [Sun, 8 Oct 2006 17:53:24 +0000 (10:53 -0700)]
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision :
6ce982d44924cc477e049b9adf359818908e72be
Steve Reinhardt [Sun, 8 Oct 2006 17:43:31 +0000 (10:43 -0700)]
Rename some vars for clarity.
--HG--
extra : convert_revision :
765283ae54d2d6b5885ea44c6c1813d4bcf18488
Steve Reinhardt [Sun, 8 Oct 2006 08:29:40 +0000 (04:29 -0400)]
Allocate new thread stacks and shared mem region via Process page table
for Tru64 thread library emulation.
--HG--
extra : convert_revision :
dbd307536e260e24ef79130d2aa88d84e33f03d4
Kevin Lim [Sun, 8 Oct 2006 05:12:42 +0000 (01:12 -0400)]
Clean up configs.
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
Add in default FUPool.
src/python/m5/objects/O3CPU.py:
Use defaults better. Also set checker parameters, and fix up a config bug.
--HG--
extra : convert_revision :
5fd0c000143f4881f10a9a575c3810dc97cb290b