Gabe Black [Sat, 6 Jan 2018 01:48:40 +0000 (17:48 -0800)]
x86, mem: Pass the multi level page table layout in as a parameter.
Don't get it from a global constant declared in an ISA header file.
Change-Id: Ie19440abdd76500a5e12e6791e6f755ad9e95af3
Reviewed-on: https://gem5-review.googlesource.com/7344
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Fri, 5 Jan 2018 23:01:00 +0000 (15:01 -0800)]
arch, mem: Make the page table lookup function return a pointer.
This avoids having a copy in the lookup function itself, and the
declaration of a lot of temporary TLB entry pointers in callers. The
gpu TLB seems to have had the most dependence on the original signature
of the lookup function, partially because it was relying on a somewhat
unsafe copy to a TLB entry using a base class pointer type.
Change-Id: I8b1cf494468163deee000002d243541657faf57f
Reviewed-on: https://gem5-review.googlesource.com/7343
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 8 Jan 2018 03:56:25 +0000 (19:56 -0800)]
base: Hide the BitUnion::__StorageType type.
Since this type is now accessible through a clean interface, hide it
from anybody that tries to peak around the curtain.
Change-Id: I1257b6675a45b8648be459ad8e8d0f27a6feee6b
Reviewed-on: https://gem5-review.googlesource.com/7205
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 8 Jan 2018 03:44:55 +0000 (19:44 -0800)]
arm, base: Generalize and move the BitUnion hash struct.
The ARM types.hh file defined an STL style hash structure to operate
on the ExtMachInst, but it referred to the underlying storage type
using internal typedefs in the BitUnion types. To avoid having to do
that, this change adds a hash structure to bitunion.hh which will work
on any BitUnion, and gets rid of the ARM ExtMachInst version.
Change-Id: I7c1c84d61b59061fec98abaaeab6becd06537dee
Reviewed-on: https://gem5-review.googlesource.com/7204
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 8 Jan 2018 03:35:40 +0000 (19:35 -0800)]
sim: Use the new BitUnion templates in serialize.hh.
serialize.hh should not reference internal implementation details in
the underlying BitUnion types.
Change-Id: I1ce29243db63801b7788f037fdc54811bdab889c
Reviewed-on: https://gem5-review.googlesource.com/7203
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Mon, 8 Jan 2018 02:38:04 +0000 (18:38 -0800)]
base: Enable specializing templates on BitUnion types.
Previously these relied on reaching into private internal definitions
in the BitUnion types.
Change-Id: Ia6c94de92986b85ec9e5fcb197459d450111fb36
Reviewed-on: https://gem5-review.googlesource.com/7202
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Jan 2018 13:30:46 +0000 (05:30 -0800)]
base: Rework bitunions so they can be more flexible.
They are now oriented around a class which makes it easy to provide
custom setter/getter functions which let you set or read bits in an
arbitrary way.
Future additions may add the ability to add custom bitfield methods,
and index-able bitfields.
Change-Id: Ibd6d4d9e49107490f6dad30a4379a8c93bda9333
Reviewed-on: https://gem5-review.googlesource.com/7201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 16 Jan 2018 09:25:39 +0000 (01:25 -0800)]
sim, arch, base: Refactor the base remote GDB class.
Fold the GDBListener class into the main BaseRemoteGDB class, move
around a bunch of functions, convert a lot of internal functions to
be private, move some functions into the .cc, make some functions
non-virtual which didn't really need to be overridden.
Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d
Reviewed-on: https://gem5-review.googlesource.com/7422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 4 Jan 2018 09:22:49 +0000 (01:22 -0800)]
arch, mem, sim: Consolidate and rename the SE mode page table classes.
Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.
Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.
Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Andreas Sandberg [Wed, 17 Jan 2018 18:06:05 +0000 (18:06 +0000)]
util: Add an option to specify paths in list_changes.py
Add an option to restrict change lists to changes that touch one or
more subdirectories in the source tree.
Change-Id: Id4e34fe300fdc3657505e2e188c727e583bcf611
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7461
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Gabe Black [Thu, 4 Jan 2018 08:30:38 +0000 (00:30 -0800)]
mem: Change the multilevel page table to inherit from FuncPageTable.
KVM looks up translations using the image of the page table in the
guest's memory, but we don't have to. By maintaining that image in
addition to rather than instead of maintaining an abstract copy makes
our lookups faster, and ironically avoids duplicate implementation.
Change-Id: I9ff4cae6f7cf4027c3738b75f74eae50dde2fda1
Reviewed-on: https://gem5-review.googlesource.com/7341
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Alec Roelke [Fri, 8 Dec 2017 23:29:56 +0000 (18:29 -0500)]
arch-riscv: Fix floating-poing op classes
This patch applies correct miscellaneous or multiply-accumulate op
classes to floating point instructions which had previously been
incorrectly classed as add or multiply instructions.
Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb
Reviewed-on: https://gem5-review.googlesource.com/6521
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Alec Roelke [Tue, 5 Dec 2017 03:54:35 +0000 (22:54 -0500)]
arch-riscv: Fix floating-point conversion bugs
Using the fetestexcept function to check for specific types of floating
point exceptions is unreliable for some kinds of
floating-point-to-integer conversion operations. RISC-V code used to
make use of them to check for some exceptional cases like overflow and
underflow, which caused incorrect output when compiler optimization is
turned on. This patch changes the use of fetestexcept to explicit checks
for those exceptional cases.
Change-Id: Id983906ea0664dc246e115a9e470d9ab7733bde1
Reviewed-on: https://gem5-review.googlesource.com/6402
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Gabe Black [Sat, 13 Jan 2018 00:16:56 +0000 (16:16 -0800)]
sim: Simplify registerThreadContext a little bit.
The code in this function was a little convoluted. This change attempts
to simplify it a little bit to make it easier to read.
Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f
Reviewed-on: https://gem5-review.googlesource.com/7421
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sat, 23 Dec 2017 03:21:30 +0000 (19:21 -0800)]
mem: Track TLB entries in the lookup cache as pointers.
Using the architectural page table on x86 and the functional page table
on ARM, both with the twolf benchmark in SE mode, there was no
performance penalty for doing so, and again possibly a performance
improvement. By using a pointer instead of an inline instance, it's
possible for the actual type of the TLB entry to be hidden somewhat,
taking a step towards abstracting away another aspect of the ISAs.
Since the TLB entries are no longer overwritten and now need to be
allocated and freed, this change introduces return types from the
updateCache and eraseCacheEntry functions. These functions will return
the pointer to any entry which has been displaced from the cache which
the caller can either free or ignore, depending on whether the entry
has a purpose outside of the cache.
Because the functional page table stores its entries over a longer time
period, it will generally not delete the pointer returned from those
functions. The "architechtural" page table, ie the one which is backed
by memory, doesn't have any other use for the TlbEntrys and will delete
them. That leads to more news and deletes than there used to be.
To address that, and also to speed up the architectural page table in
general, it would be a good idea to augment the functional page table
with an image of the table in memory, instead of replacing it with one.
The functional page table would provide quick lookups and also avoid
having to translate page table entries to TLB entries, making
performance essentially equivalent to the functional case. The backing
page tables, which are primarily for consumption by the physical
hardware when in KVM, can be updated when mappings change but otherwise
left alone.
If we end up doing that, we could just let the ISA specific process
classes enable whatever additional TLB machinery they need, likely
a backing copy in memory, without any knowledge or involvement from
the ISA agnostic class. We would be able to get rid of the useArchPT
setting and the bits of code in the configs which set it.
Change-Id: I2e21945cd852bb1b3d0740fe6a4c5acbfd9548c5
Reviewed-on: https://gem5-review.googlesource.com/6983
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Gabe Black [Sun, 14 Jan 2018 19:44:04 +0000 (11:44 -0800)]
arch: Fix a fatal_if in most of the arch's process classes.
When switching an assert to a fatal while addressing recent review
feedback, I forgot to reverse the polarity of the condition, making
the fatal fire in exactly the opposite of the conditions it was meant
to.
Change-Id: Icf49864ef449052bbb0d427dca786006166575c4
Reviewed-on: https://gem5-review.googlesource.com/7381
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Xiaoyu Ma [Thu, 30 Nov 2017 15:48:52 +0000 (07:48 -0800)]
sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().
Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.
Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Earl Ou [Fri, 6 Oct 2017 12:55:41 +0000 (20:55 +0800)]
util/m5: add Android.mk
Add Android.mk so we can build m5 tool in Android tree.
Change-Id: I7023130bd3ce5e015b8f7c41941eafb4611da8cb
Reviewed-on: https://gem5-review.googlesource.com/7363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Alec Roelke [Fri, 15 Dec 2017 04:22:10 +0000 (23:22 -0500)]
arch-riscv: Don't crash when printing unknown CSRs
This patch fixes a potential crash if an unnamed CSR is accessed and
debug flags are enabled that print disassembly. Unknown CSRs will be
identified as "??" followed by the address that was used.
Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
Reviewed-on: https://gem5-review.googlesource.com/7321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Nikos Nikoleris [Wed, 3 Jan 2018 11:10:09 +0000 (12:10 +0100)]
mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol
This changeset fixes a bug that was affecting the MOESI_CMP_token
protocol where setting the next timeout required an absolute tick in
the future.
Change-Id: Ibfdb59354e13c7e552cb3389e71bda010f333249
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7163
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Tue, 2 Jan 2018 20:33:25 +0000 (21:33 +0100)]
mem-ruby: Remove function that maps responses to a DMA engine
The function map_Address_to_DMA was used to route responses to the
first (and assumed to be the only) DMA engine in the system. This
function is now unused as protocols handle responses and route them to
the right DMA engine.
Change-Id: I2fba913cf2f12321d1a1e38e7ee85bdf26b8a47a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Tue, 2 Jan 2018 20:28:07 +0000 (21:28 +0100)]
mem-ruby: Add support for multiple DMA engines in MESI_Two_Level
Previously the MESI_Two_Level protocol supported systems with a single
DMA engine and responses from the directory to DMA requests were
routed back to the only DMA engine. This changeset adds support for
multiple DMA engines in the system by routing the response to the DMA
engine that originally sent the request.
Change-Id: I10ceda682ea29746636862ec8ef2a9c4220ca045
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7161
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Tue, 9 Jan 2018 03:08:17 +0000 (19:08 -0800)]
cpu: Make the CPU's TLB parameter a BaseTLB.
This is instead of the architecture specific version.
Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Reviewed-on: https://gem5-review.googlesource.com/7349
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 9 Jan 2018 03:07:21 +0000 (19:07 -0800)]
arm, power: Make the python TLB simobjects inherit from BaseTLB.
These were still inheriting from SimObject instead of BaseTLB, making
them incompatible with parameters which expect a BaseTLB.
Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40
Reviewed-on: https://gem5-review.googlesource.com/7348
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sat, 23 Dec 2017 01:14:47 +0000 (17:14 -0800)]
arch,mem: Remove the default value for page size.
This breaks one more architecture dependence outside of the ISAs.
Change-Id: I071f9ed73aef78e1cd1752247c183e30854b2d28
Reviewed-on: https://gem5-review.googlesource.com/6982
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Gabe Black [Sat, 23 Dec 2017 00:14:03 +0000 (16:14 -0800)]
arch,mem: Move page table construction into the arch classes.
This gets rid of an awkward NoArchPageTable class, and also gives the
arch a place to inject ISA specific parameters (specifically page size)
without having to have TheISA:: in the generic version of these types.
Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441
Reviewed-on: https://gem5-review.googlesource.com/6981
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Chen Zou [Wed, 3 Jan 2018 22:31:06 +0000 (16:31 -0600)]
configs: Fill in the cpu.isa field in etrace_replay.py since no default are provided now
Change-Id: I5f337b9969820bd74ed67e576e2d1a8e4666ecdb
Reviewed-on: https://gem5-review.googlesource.com/7021
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
BKP [Tue, 9 Jan 2018 19:16:29 +0000 (13:16 -0600)]
style: change C/C++ source permissions to noexec
Several files in the repository were tracked with execute permissions
even though the files are just normal C/C++ files (and the one .isa).
Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2
Reviewed-on: https://gem5-review.googlesource.com/7241
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Alec Roelke [Sat, 2 Dec 2017 17:58:14 +0000 (12:58 -0500)]
arch-riscv: Make use of ImmOp's polymorphism
This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.
Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
Reviewed-on: https://gem5-review.googlesource.com/6401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Gabe Black [Wed, 20 Dec 2017 07:14:34 +0000 (23:14 -0800)]
alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.
This constant is, first, a #define, and second only used in one place.
In that one place, it appears that the code it guards is no longer
necessary in general. It was originally written to avoid refetching a
block of data that you're still in, even if you've moved slightly
farther in it because you're skipping the next instruction due to an
annulled branch delay slot. In reality however, in SPARC, the one ISA
I'm aware of which has this sort of branching behavior, the PC state
object will correctly determine that no branch is happening in these
cases. Code lower down in the loop will then recompute where fetching
should continue based on the next PC, automatically skipping the
annulled branch slot without misinterpretting the gap as a branch.
This change therefore also removes this block of code.
Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Reviewed-on: https://gem5-review.googlesource.com/6821
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tuan Ta [Sun, 17 Sep 2017 16:57:21 +0000 (12:57 -0400)]
arch-riscv,sim: Support clone syscall in RISC-V
(1) This patch sets a correct order of clone syscall's arguments for
RISC-V. Linux kernel 4.15 uses CLONE_BACKWARDS flag by default for
RISC-V. The flag in the Linux kernel defines the list of clone syscall's
arguments in the following order:
clone_flags (flags)
newsp (newStack)
parent_tidptr (ptidPtr)
tls (tlsPtr)
child_tidptr (ctidPtr)
Code reference:
https://github.com/riscv/riscv-linux/blob/master/kernel/fork.c
https://github.com/riscv/riscv-linux/blob/master/arch/riscv/Kconfig
(2) This patch copies a parent thread's register values to its child
thread in clone syscall.
Change-Id: I2eb1c8e80990861080ce7153503ed784fb2c7bdf
Reviewed-on: https://gem5-review.googlesource.com/6904
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Nikos Nikoleris [Mon, 4 Sep 2017 15:38:36 +0000 (16:38 +0100)]
mem-cache: Prune unnecessary writebacks in exclusive caches
Exclusive caches use the tempBlock to fill for responses from a
downstream cache. The reason for this is that they only pass the block
to the cache above without keeping a copy. When all requests are
serviced the block is immediately invalidated unless it is dirty, in
which case it has to be written back to the memory below.
To avoid unnecessary writebacks, this changeset forces mostly
exclusive caches to issuse requests that can only fetch clean data
when possible.
Reported-by: Quereshi Muhammad Avais <avais@kaist.ac.kr>
Change-Id: I01b377563f5aa3e12d22f425a04db7c023071849
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Hanhwi Jang [Fri, 8 Dec 2017 10:14:24 +0000 (19:14 +0900)]
util: Add the missing wakecpu m5op in X86.
Change-Id: I74876a4638ad37308ecdb0ef68513a968fac8787
Reviewed-on: https://gem5-review.googlesource.com/6501
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Hanhwi Jang [Fri, 8 Dec 2017 05:34:59 +0000 (14:34 +0900)]
util: resolve m5op name mismatching in m5op headers.
Two m5op, load_symbol and dist_toggle_sync are defined with
different name in C and asm version headers 'm5ops.h'
The m5ops are named to m5_load_symbol() and m5_dist_toggle_sync().
Change-Id: I9630d74f3fb95bc3dc5fa082778d8f6eaa49b3cb
Reviewed-on: https://gem5-review.googlesource.com/6481
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sat, 6 Jan 2018 00:20:14 +0000 (16:20 -0800)]
cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.
When a fault happens in fetch in O3, a dummy inst is created to carry
the fault through the pipeline to commit, but conceptually there isn't
actually any instruction since we failed to fetch one.
This change marks the dummy instruction as NotAnInst, and when any
such instruction gets to commit, the fault object associated with it
is invoked and passed a null static inst pointer instead of a pointer
to the dummy inst.
Change-Id: I18d993083406deb625402e06af4ba0d4772ca5a3
Reviewed-on: https://gem5-review.googlesource.com/7124
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Jan 2018 23:40:47 +0000 (15:40 -0800)]
cpu: Add a NotAnInst flag to the BaseDynInst class.
This flag means that the instruction isn't an actual instruction, it's
just a placeholder to carry a fault down a pipeline, for instance.
Change-Id: I1cc12b068662dbd3d3b089c9941a07b6e88b57e3
Reviewed-on: https://gem5-review.googlesource.com/7123
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 5 Jan 2018 23:33:08 +0000 (15:33 -0800)]
cpu, power: Get rid of the remnants of the EA computation insts.
Get rid of some remnants of a system which was intended to separate
address computation into its own instruction object.
Change-Id: I23f9ffd70fcb89a8ea5bbb934507fb00da9a0b7f
Reviewed-on: https://gem5-review.googlesource.com/7122
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 6 Jan 2018 00:17:44 +0000 (16:17 -0800)]
arm: Make translateFunctional override the base implementation.
Now that translateFunctional is a virtual function, having an extra
parameter with a default value makes the compiler fall through to the
base implementation instead of overriding it. This change removes the
default value for the extra parameter, and adds a small wrapper with
the correct signature which overrides the base implementation and calls
the full version with the previously default value for the extra
parameter. To callers this will look like the same thing, but the
the right function will get called.
This was what was already being done for transateAtomic and
translateTiming.
Change-Id: I0b71adf34fd6f326005edbb8eaac93275b437c55
Reviewed-on: https://gem5-review.googlesource.com/7121
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tony Gutierrez [Fri, 5 Jan 2018 23:10:47 +0000 (18:10 -0500)]
gpu-compute: call createThreads() on cpu objs in apu_se.py
commit
8ad26e2688b8736f9290086bb4026cc7500429e9
cpu: Don't override ISA if provided by user
removed the default ISA from the BaseCPU, and instead relies on
createThreads() to initiate a default ISA if none is specified. the apu_se.py
script, however does not call creatThreads() leading to a fatal when
constructing CPU objects. this patch adds the appropriate calls to
createThreads() inside apu_se.py.
Change-Id: I16a5929454c59d68a3f1b7b3858c48a70cb76412
Reviewed-on: https://gem5-review.googlesource.com/7101
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tuan Ta [Sat, 23 Dec 2017 01:10:46 +0000 (20:10 -0500)]
arch-riscv: Ignore sched_yield syscall in SE mode
Change-Id: I14f22c06eb8fdbe063980b4cd0a49387b9113a97
Reviewed-on: https://gem5-review.googlesource.com/6961
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Tuan Ta [Thu, 21 Dec 2017 16:06:10 +0000 (11:06 -0500)]
sim: Fix a bug in prlimit syscall in SE mode
The old_limit pointer is supposed to be the 4th argument (index 3) of
the prlimit syscall. This patch sets old_limit pointer to the correct
argument.
Change-Id: I97808f7234cd2622cb3eb2f1e0beb7fc8cf492c1
Reviewed-on: https://gem5-review.googlesource.com/6903
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tuan Ta [Sun, 17 Dec 2017 19:22:12 +0000 (14:22 -0500)]
arch-riscv: Ignore set_robust_list and get_robust_list syscalls
Change-Id: I5a4744e5aed07337144af9f07978b83405b6695b
Reviewed-on: https://gem5-review.googlesource.com/6902
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Tuan Ta [Fri, 15 Dec 2017 21:07:05 +0000 (16:07 -0500)]
arch-riscv: Add an implementation of set_tid_address syscall in RISCV
Change-Id: Ida29ea6f6a9c3efe00aaebbfcb6b537fc62f6d06
Reviewed-on: https://gem5-review.googlesource.com/6901
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Alec Roelke [Fri, 5 Jan 2018 00:04:43 +0000 (19:04 -0500)]
arch-riscv: Correct syscall argument reg count
As per the discussion in patch #6904 and the Linux 4.15 kernel code for
RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0
through a6), with x17 (a7) being used for the system call number.
Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Reviewed-on: https://gem5-review.googlesource.com/7081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Alec Roelke [Thu, 4 Jan 2018 19:17:13 +0000 (14:17 -0500)]
arch-riscv: Remove "magic" syscall number constant
getSyscallArg() in RISC-V has an explicit check to make sure that the
register index is within the bounds of the system call register indices
vector. This patch fixes it so that it uses SyscallArgumentRegs.size()
rather than a "magic" constant that has to be updated every time
SyscallArgumentRegs is changed.
Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8
Reviewed-on: https://gem5-review.googlesource.com/7061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Gabe Black [Fri, 22 Dec 2017 04:49:50 +0000 (20:49 -0800)]
config: Handle NULL simobject parameters in read_config.py.
Change-Id: If0f87e8ee37099be4d0f3567db4fc34f8467e409
Reviewed-on: https://gem5-review.googlesource.com/6943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Fri, 22 Dec 2017 04:26:41 +0000 (20:26 -0800)]
config: Fix parsing AddrRange parameters in read_config.py.
The format of AddrRange parameters was changed, but
config/example/read_config.py wasn't updated for the new format.
Change-Id: Ie0da7aaa47c827bacc2b4f7f44929efd868b8794
Reviewed-on: https://gem5-review.googlesource.com/6942
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Fri, 15 Dec 2017 01:29:17 +0000 (17:29 -0800)]
config: Add a --checkpoint-dir argument to read_config.py.
This argument lets the user restore a checkpoint after loading
simulator state from config.ini.
Change-Id: I6e0630d75b798a1d2536e2408660843f57f46c4b
Reviewed-on: https://gem5-review.googlesource.com/6941
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 20 Dec 2017 08:06:07 +0000 (00:06 -0800)]
alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.
It's no longer used.
Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5
Reviewed-on: https://gem5-review.googlesource.com/6826
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 20 Dec 2017 08:02:47 +0000 (00:02 -0800)]
riscv,x86: Stop using the arch Nop machine instruction unnecessarily.
That particular ExtMachInst is a convenient placeholder, but a value
of 0 in RISCV or a static uninitialized ExtMachInst (which will
therefore be all zeroes) on x86 works just as well, and removes the
need for an ISA specific constant.
Also, the idea of a universal Nop doesn't always make sense since it
could be that what, exactly, doesn't do anything depends on context
which would be lost on a constant value of an ExtMachInst. For
instance, the value of an ExtMachInst that makes sense might depend on
what mode the CPU was in, etc.
Change-Id: I1f1a43a5c607a667e11b79bcf6e059e4f7141b3f
Reviewed-on: https://gem5-review.googlesource.com/6825
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Dec 2017 09:07:55 +0000 (01:07 -0800)]
arch,cpu: "virtualize" the TLB interface.
CPUs have historically instantiated the architecture specific version
of the TLBs to avoid a virtual function call, making them a little bit
more dependent on what the current ISA is. Some simple performance
measurement, the x86 twolf regression on the atomic CPU, shows that
there isn't actually any performance benefit, and if anything the
simulator goes slightly faster (although still within margin of error)
when the TLB functions are virtual.
This change switches everything outside of the architectures themselves
to use the generic BaseTLB type, and then inside the ISA for them to
cast that to their architecture specific type to call into architecture
specific interfaces.
The ARM TLB needed the most adjustment since it was using non-standard
translation function signatures. Specifically, they all took an extra
"type" parameter which defaulted to normal, and translateTiming
returned a Fault. translateTiming actually doesn't need to return a
Fault because everywhere that consumed it just stored it into a
structure which it then deleted(?), and the fault is stored in the
Translation object when the translation is done.
A little more work is needed to fully obviate the arch/tlb.hh header,
so the TheISA::TLB type is still visible outside of the ISAs.
Specifically, the TlbEntry type is used in the generic PageTable which
lives in src/mem.
Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575
Reviewed-on: https://gem5-review.googlesource.com/6921
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 20 Dec 2017 07:48:00 +0000 (23:48 -0800)]
cpu: Use the generic nop static inst instead of decoding the arch version.
This removes a dependence on the ISA.
Change-Id: I01013bc70558f0831327213912bcac11258066a6
Reviewed-on: https://gem5-review.googlesource.com/6824
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Wed, 20 Dec 2017 07:44:39 +0000 (23:44 -0800)]
cpu: Add a pointer to a generic Nop StaticInst.
This can be used whenever generic code needs a filler instruction that
doesn't do anything.
Change-Id: Ib245d3e880a951e229eb315a09ecc7c47e6ae00f
Reviewed-on: https://gem5-review.googlesource.com/6823
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 1 Dec 2017 16:25:55 +0000 (16:25 +0000)]
arch-arm: Fixed WFE/WFI trapping behaviour
This patch fixes the WFx trapping behaviour by introducing the arm arm
v8 pseudocode functions: checkForWFxTrap32 and checkForWFxTrap64
Change-Id: I3db0d78b5c4ad46860e6d199c2f2fc7b41842840
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6622
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 1 Dec 2017 13:24:29 +0000 (13:24 +0000)]
arch-arm: Hyp routed undef fault need to change its syndrome
If undefined instruction has to be routed to EL2, the HSR register
must change the HSR.EC and HSR.ISS accordingly, which means not using
the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0)
Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6621
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Tue, 19 Dec 2017 18:15:32 +0000 (18:15 +0000)]
arch-arm: Fix StaticInst encoding() method
The previously introduced method was missing the machInst value
to be masked.
Change-Id: Ic722f7cc2abc680da1a1f19c08299338b5c859a6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6881
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Wed, 20 Dec 2017 07:35:30 +0000 (23:35 -0800)]
cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.
Change-Id: I868021a01eb3e7902a4d64283bdfaa93c6d9f964
Reviewed-on: https://gem5-review.googlesource.com/6822
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 15 Dec 2017 10:03:19 +0000 (10:03 +0000)]
arch-arm: Instruction size methods in StaticInst class
This patch is introducing some methods in StaticInst so that is possible
to get the instruction size in byte of the instruction (can be 2 bytes
in Thumb) and the correct opcode (The machInst field contains some
appended metadata)
Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6781
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 15 Dec 2017 15:56:03 +0000 (15:56 +0000)]
arch-arm: Change casting type from reinterpret to static
Cosmetic fix: prefer static_cast rather than reinterpret_cast in
hierarchy.
Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6761
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Riken Gohil [Tue, 1 Aug 2017 10:08:16 +0000 (11:08 +0100)]
cpu-tester: Added ExitGen to TrafficGen
Added the ExitGen to the TrafficGenerator which allows an EXIT
state to be added to the TrafficGen configuration file. Entering this
state will cause the simulation to exit immediately. Please note that
if multiple TrafficGen instances have an EXIT state, the first of these
to be encountered will cause the simulation to terminate.
Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5723
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Riken Gohil [Wed, 12 Jul 2017 16:33:11 +0000 (17:33 +0100)]
cpu-tester: Refactoring traffic generators into separate files.
Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Swapnil Haria [Thu, 9 Nov 2017 19:04:39 +0000 (13:04 -0600)]
mem-ruby: Support atomic_noncaching acceses in ruby
Ruby has no support for atomic_noncaching accesses, which prevents using
it with kvm-cpu. This patch fixes this by directly forwarding atomic
requests from the ruby port/sequencer to the corresponding directory
based on the destination address of the packet.
Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d
Reviewed-on: https://gem5-review.googlesource.com/5601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Alec Roelke [Thu, 14 Dec 2017 17:17:31 +0000 (12:17 -0500)]
arch-riscv: Define AT_RANDOM properly
According to the getauxval(3) man page, the AT_RANDOM aux value should
be a pointer to 16 random bytes. In the initial implementation of
RISC-V, this was based on spike's program stack setup, which copied the
program header table there instead. This patch changes the
implementation to use the proper 16 random bytes, making it compatible
with some RISC-V programs that use custom linker scripts.
Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2
Reviewed-on: https://gem5-review.googlesource.com/6681
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Alec Roelke [Thu, 14 Dec 2017 00:00:11 +0000 (19:00 -0500)]
arch-riscv: Increase maximum stack size
This patch increases the maximum stack size of RISC-V, which should help
to reduce problems with programs that allocate large amounts of data on
the stack or do many small allocations.
Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d
Reviewed-on: https://gem5-review.googlesource.com/6661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Jason Lowe-Power [Wed, 13 Dec 2017 18:19:04 +0000 (10:19 -0800)]
misc: Updates for gcc7.2 for x86
GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:
* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878
Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
Jason Lowe-Power [Sat, 18 Nov 2017 01:02:05 +0000 (17:02 -0800)]
ext: Upgrade PyBind11 to version 2.2.1
This upgrade is necessary for pybind to build with GCC 7.2.
We still need to add the patch for stl.h. MSC_FULL_VER change is no longer
needed.
See https://gem5-review.googlesource.com/c/public/gem5/+/2230
Change-Id: I806729217d022070583994c2dfcaa74476aef30f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5801
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Wed, 13 Dec 2017 09:03:00 +0000 (01:03 -0800)]
x86: Use operand size 4 when it would be 2 for cmpxchg8b.
This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.
Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Andreas Sandberg [Wed, 13 Dec 2017 14:29:39 +0000 (14:29 +0000)]
scons, tests: Fix occasional linking error
There are some cases where scons incorrectly adds the same object
multiple times to the linker command line. This seems to be caused by
the test's source list being updated in place when determining test
framework dependencies. Fix this by explicitly copying the source list
and manipulate the copy.
Without this change, the following command fails:
scons ./build/ARM/unittests.opt/base/pixeltest.xml
Whereas this command succeeds:
scons ./build/ARM/base/pixeltest.opt
Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6641
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Andreas Sandberg [Wed, 13 Dec 2017 11:14:28 +0000 (11:14 +0000)]
scons, tests: Add support for GTest XML generation
The GTest framework supports result generation in XML (JUnit). Enable
this by creating unit test specific targets in the
build/${BUILD_OPTS}/unittests.${VARIANT} directory. Targets in the
directory use the following naming convention:
${SRC_PATH}/${TEST_NAME}.xml
For example, the opt version of the bitunion test built for ARM would
have this path:
build/ARM/unittests.opt/base/bituniontest.xml
Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6624
Reviewed-by: Gabe Black <gabeblack@google.com>
Andreas Sandberg [Wed, 13 Dec 2017 13:16:40 +0000 (13:16 +0000)]
scons: Make sure GTests have the right environment variables
SCons currently scrubs the environment variables used by GTests too
aggressively. This breaks systems where libraries are installed in
non-standard locations that need to be specified in
LD_LIBRARY_PATH. Run said tests in the gtest_env SCons environment
which white-lists the important environment variables.
Change-Id: I5fc8fb5e51f09644dc976ee97b21c78ab349bf7d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6623
Reviewed-by: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 13 Dec 2017 08:53:34 +0000 (00:53 -0800)]
arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.
Replace them with std::array<>s.
Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 13 Dec 2017 07:12:30 +0000 (23:12 -0800)]
cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.
Neither of these were used, particularly memAccInst.
Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc
Reviewed-on: https://gem5-review.googlesource.com/6601
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Wed, 13 Dec 2017 01:54:58 +0000 (17:54 -0800)]
x86: Rework how "split" loads/stores are handled.
Explicitly separate the way the data is represented in the underlying
representation from how it's represented in the instruction.
In order to make the ISA parser happy, the Mem operand needs to have
a single, particular type. To handle that with scalar types, we just
used uint64_ts and then worked with values that were smaller than the
maximum we could hold. To work with these new array values, we also
use an underlying uint64_t for each element.
To make accessing the underlying memory system more natural, when we
go to actually read or write values, we translate the access into an
array of the actual, correct underlying type. That way we don't have
non-exact asserts which confuse gcc, or weird endianness conversion
which assumes that the data should be flipped 8 bytes at a time.
Because the functions involved are generally inline, the syntactic
niceness should all boil off, and the final implementation in the
binary should be simple and efficient for the given data types.
Change-Id: I14ce7a2fe0dc2cbaf6ad4a0d19f743c45ee78e26
Reviewed-on: https://gem5-review.googlesource.com/6582
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 13 Dec 2017 01:49:35 +0000 (17:49 -0800)]
base: Add endianness conversion functions for std::array types.
These swap the endianness of each element within the array
individually.
They probably obsolute the Twin(32|64)_t types which I believe were
used for SPARC.
Change-Id: Ic389eb24bdcdc0081068b0c5a37abdf416f6c924
Reviewed-on: https://gem5-review.googlesource.com/6581
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 5 Dec 2017 04:04:20 +0000 (20:04 -0800)]
tests: Turn fbtest into a gtest and move it to src/base.
Change-Id: I9ca57e24f27e0eb747d1f27262972a8abcd10fc8
Reviewed-on: https://gem5-review.googlesource.com/6342
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 5 Dec 2017 03:46:26 +0000 (19:46 -0800)]
tests: Move the cprintftest unit test into src/base.
That way it will live alongside the code it tests.
Change-Id: I00baad2206870a4619b7cee792a1d4c303dad04d
Reviewed-on: https://gem5-review.googlesource.com/6324
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 5 Dec 2017 03:44:47 +0000 (19:44 -0800)]
tests: Convert the cprintf unit test into a gtest.
Change-Id: I0f78a202d1f5fd29cda94ca93b540618831fe898
Reviewed-on: https://gem5-review.googlesource.com/6323
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sun, 3 Dec 2017 09:59:39 +0000 (01:59 -0800)]
tests: Move the trietest unit test into base.
This puts it alongside trie.hh, the header file it tests.
Change-Id: Id8ca0c1d68bdc01807c5ba4b51c0142b1221385d
Reviewed-on: https://gem5-review.googlesource.com/6281
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Gabe Black [Sun, 3 Dec 2017 09:53:18 +0000 (01:53 -0800)]
tests: Plumb dumps of the test trie into the gtest macros.
With this change, when one of the tests fails, it will output a dump
of the trie data structure, making it a little easier to tell what
happened.
Change-Id: I0816ed727ef0b50fefd7ec485356b4fe8790bfe1
Reviewed-on: https://gem5-review.googlesource.com/6267
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Gabe Black [Sun, 3 Dec 2017 09:42:22 +0000 (01:42 -0800)]
tests: Convert the trie unit test into a gtest.
Change-Id: Idcf60260d9bda1b8ef5b6f5d59b74ca218395f0c
Reviewed-on: https://gem5-review.googlesource.com/6265
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Gabe Black [Sun, 3 Dec 2017 09:39:41 +0000 (01:39 -0800)]
tests: Add an implementation of the Logger interface for use gtests.
On exiting log types (panic and fatal), the message is set to an
ADD_FAILURE_AT macro, and the test is exited by throwing an otherwise
unexpected exception. On non-exiting log types, the message is sent to
the SUCCEEDED macro which currently doesn't output anything.
Change-Id: I1bb569e6cb8308dbc4c3e04eea7a962bd2b1ddd8
Reviewed-on: https://gem5-review.googlesource.com/6264
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sun, 3 Dec 2017 09:22:38 +0000 (01:22 -0800)]
misc: Rework the logging functions.
Removed the "verbose" switch which wasn't used.
Replaced the "get(LogLevel)" function with a get for each level. The
parameter was always constant, so we can just call the right function
at the right time.
Made the "exit" behavior of panic/fatal a part of the logging
implementation so that it can be overridden, and corrected a comment
which said that both fatal and panic called ::abort().
Got rid of the printEpilogue function by reworking the print() methods.
The subclasses of Logger can now override a "log" function which takes
a composed message, letting the Logger class centralize how the message
is put together and leaving the actual output mechanism to the
subclass.
Unfortunately there wasn't a way to tell gcc that the panic/fatal
macros wouldn't return, so there needed to be an exit_helper wrapper
function which calls the actual logger exit function. That can be
marked as noreturn, unlike the virtual exit function. If the exit
function does return, the wrapper will call ::abort(), placating gcc
and ensuring that even if exit isn't implemented properly, exit_helper
will still not return. That also provides a handy default
implementation.
Change-Id: I66d0cebd59f1127db980f3b565dbdf60687d8862
Reviewed-on: https://gem5-review.googlesource.com/6263
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Austin Harris [Sat, 2 Dec 2017 23:03:28 +0000 (17:03 -0600)]
config: Fix need to set ISA of switch cpus.
Since BaseCPU.createThreads() no longer overrides the BaseCPU.isa
parameter, switch_cpus should have the ISA copied. This fixes a
fatal error in BaseCPU when restoring from a checkpoint.
Change-Id: I4fdcacb76da46bdbe1ce37dcf05c5a6a8a9e5237
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/6241
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Giacomo Travaglini [Thu, 30 Nov 2017 13:35:05 +0000 (13:35 +0000)]
arm: Change access permission in TPIDRURO and TPIDRURW
This patch corrects the TPIDRURO and TPIDRURW access flags: TPIDRURO is
now readable in secure user mode, an TPIDRURW is readable and writable
in secure user mode.
Change-Id: I6293d9a3bcc7adc0f655bf98d29aca51eca5a002
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6381
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Matt Sinclair [Thu, 7 Dec 2017 01:29:11 +0000 (20:29 -0500)]
x86,misc: add additional info on faulting X86 instruction, fetched PC
Print faulting instruction for unmapped address panic in faults.cc
and print extra info about corresponding fetched PC in base.cc.
Change-Id: Id9e15d3e88df2ad6b809fb3cf9f6ae97e9e97e0f
Reviewed-on: https://gem5-review.googlesource.com/6461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 3 Dec 2017 09:20:12 +0000 (01:20 -0800)]
tests: Accept SourceFilters as sources for GTest.
This change introduces the idea of a SourceFilter which is an object
that can filter a SourceList and which can be composed with other
SourceFilters using | and & operators. This means a filter can be
constructed ahead of time, possibly before all sources have been
discovered, and then later applied to any SourceList necessary.
This change also modifies GTest so that it accepts SourceFilters in
addition to normal source files. These filters will be applied to the
final list of all sources, and the result included in the build for
that test.
By default, gtests will build in all sources tagged with 'gtest lib'.
This change also introduces the keyword argument "skip_lib" which will
exclude those files. They can then be left out entirely, or they can be
re-included as part of a more elaborate filter. That would be useful if
someone wanted to write a unit test for, for instance, the warn, etc.
macros which rely on the gtest logging support. Those classes could
be replaced by something under the control of the unit test, while
still including the rest of the gtest library.
Change-Id: I13a846dc884b86b9fdcaf809edefd57bb4168b8e
Reviewed-on: https://gem5-review.googlesource.com/6262
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sun, 3 Dec 2017 10:10:42 +0000 (02:10 -0800)]
tests: Add a pseudo target to run all the unit tests for build/variant.
Telling scons to build build/${BUILD_OPTS}/unittests.${VARIANT} will
get it to build and run all googletest based unit tests under the
${BUILD_OPTS} build options (ARM, ALPHA, X86, etc.), and compiled with
the flags, etc., for the ${VARIANT} variant (ie. opt, debug, etc.).
This will make it easy to run the unit tests without having to actually
know where they are, what tests are available, etc.
This target is called unittests* and not something based on gtest or
googletest since it's my intention for all unit tests to be based on
googletest, making the distinction unnecessary. Since the target is
essentially part of the external interface for scons, I wanted to name
it something general so it'll be less likely that we have to change it.
Change-Id: I8fdec768d821974309c92a2ce4c96dce7df24fa5
Reviewed-on: https://gem5-review.googlesource.com/6282
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Alec Roelke [Fri, 10 Nov 2017 20:46:11 +0000 (15:46 -0500)]
arch-riscv: Move compressed ops out of ISA
This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.
Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Reviewed-on: https://gem5-review.googlesource.com/6026
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Gabe Black [Wed, 6 Dec 2017 01:49:51 +0000 (17:49 -0800)]
x86: Split apart x87's FSW and TOP, and add a missing break.
The FSW and TOP values are technically part of the same register, but
they have very different behaviors. One of them can be renamed and
float along without affecting global state, while the other requires
serialization. They just need to *look* like the same register when
read by the user.
Also, there was a missing break in setMiscRegNoEffect.
Change-Id: If58de0f566f65068208240f4001209fb9e1826d6
Reviewed-on: https://gem5-review.googlesource.com/6441
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Jason Lowe-Power [Tue, 5 Dec 2017 17:18:44 +0000 (09:18 -0800)]
misc: Update MAINTAINERS with learning-gem5 tag
Change-Id: Ic91fb1d9b2c3c42946cb84c1ec52d9376d4e50b4
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/6422
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Gabe Black [Tue, 5 Dec 2017 04:22:43 +0000 (20:22 -0800)]
base: Split out the pixel class in framebuffer.(cc|hh).
These are really two separate things. Also, while it's realitively
straightforward to write a unit test for the pixel conversion code, the
framebuffer object is serializable and brings in more dependencies.
Change-Id: If954caeb0bfedb1002cfb1a7a115a00c90d56d19
Reviewed-on: https://gem5-review.googlesource.com/6341
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 5 Dec 2017 03:42:41 +0000 (19:42 -0800)]
base: Handle zero fill in cprintf when printing floats.
The fill_zero flag was being followed for ints, but not for floats.
This makes the cprintf unit test pass.
Change-Id: I4d17a3c9327aea05e0a3c81be1886c0c9256f03c
Reviewed-on: https://gem5-review.googlesource.com/6322
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 5 Dec 2017 03:10:28 +0000 (19:10 -0800)]
tests: Fix the source file for the cprintftime test.
It was using the source file for the cprintftest unit test.
Change-Id: I534798e892ad55cef2f48be2ba9d732aa1993819
Reviewed-on: https://gem5-review.googlesource.com/6321
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sun, 3 Dec 2017 08:56:36 +0000 (00:56 -0800)]
scons: Several fixes having to do with tags and sets.
There were a few places where tags weren't being converted to sets
correctly which unfortunately only manifested when called in certain
ways. This would be a pretty reasonable place to add some python unit
tests...
Change-Id: I87509369b4ec6f702b7521e52bf63701a87ec436
Reviewed-on: https://gem5-review.googlesource.com/6261
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 1 Dec 2017 00:09:29 +0000 (16:09 -0800)]
scons: Track and reuse object nodes for a given source file.
scons gets upset if two different environments are used to set up a
particular object file. This change adds two dicts to the SourceFile
class, one for static and one for shared object files, which are keyed
off of the appropriate suffix. If a suffix hasn't been set up yet,
a new node of the appropriate type is set up and stored in the cache,
and then whatever is in the cache (new or old) is returned.
Change-Id: Ice4b4fc728b438a4d3316c3ff6667c0480d2a6d7
Reviewed-on: https://gem5-review.googlesource.com/6224
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 5 Dec 2017 02:30:41 +0000 (18:30 -0800)]
x86: LOOP's operand size defaults to 64 bits in 64 bit mode.
The microcode for those instructions needs a directive which overrides
that setting in the instructions emulation environment.
Reported-by: Matt Sinclair <mattdsinclair@gmail.com>
Change-Id: I474d938c0b3cf01da92ec817a58b08de783f1967
Reviewed-on: https://gem5-review.googlesource.com/6301
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Hanhwi Jang [Tue, 5 Dec 2017 07:39:32 +0000 (16:39 +0900)]
learning-gem5: Fix missing misc.hh in hello_object.cc
misc.hh has been renamed in
commit
1088f0c4ac3999fc3c363cc51daef4cfb360a2bd
Change-Id: Ic4f8c6423e6a5466f8d924e793a24f62bb4eca9c
Reviewed-on: https://gem5-review.googlesource.com/6361
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Thu, 12 Jan 2017 17:59:44 +0000 (17:59 +0000)]
arm: Add support for the dc {civac, cvac, cvau, ivac} instr
This patch adds support for decoding and executing the following ARMv8
cache maintenance instructions by Virtual Address:
* dc civac: Clean and Invalidate by Virtual Address to the Point
of Coherency
* dc cvac: Clean by Virtual Address to the Point of Coherency
* dc cvau: Clean by Virtual Address to the Point of Unification
* dc ivac: Invalidate by Virtual Addrsess to the Point of Coherency
Change-Id: I58cabda37f9636105fda1b1e84a0a04965fb5670
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5060
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Tue, 7 Feb 2017 11:35:10 +0000 (11:35 +0000)]
arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions
This patch adds support for the ARMv7 cache maintenance
intructions:
* mcr dccmvac cleans a VA to the PoC
* mcr dcimvac invalidates a VA to the PoC
* mcr dccimvac cleans and invalidates a VA to the PoC
* mcr dccmvau cleans a VA to the PoU
Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5059
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Sat, 7 Oct 2017 10:19:54 +0000 (11:19 +0100)]
mem-ruby: Prevent ruby from crashing on CMOs
Ruby has no support for cache maintenace operations. As a workaround,
after printing a warning, we treat them as no-ops in the memory system
and respond immediately without handling them. There should be
workarounds in the memory system already that allow execution to
proceed without the requirement for cache maintenance operations.
Change-Id: I125ee4fa37b674c636d87f2d9205bbc1a74da101
Reviewed-on: https://gem5-review.googlesource.com/5057
Reviewed-by: Jieming Yin <bjm419@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>