[ARM] Optional -mthumb for Thumb only targets

2016-11-18  Terry Guo  <terry.guo@arm.com>
            Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * common/config/arm/arm-common.c (arm_target_thumb_only): New function.
    * config/arm/arm-opts.h: Include arm-flags.h.
    (struct arm_arch_core_flag): Define.
    (arm_arch_core_flags): Define.
    * config/arm/arm-protos.h: Include arm-flags.h
    (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32,
    FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E,
    FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM,
    FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV,
    FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT,
    FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST,
    FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4,
    FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E,
    FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J,
    FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ,
    FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A,
    FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM,
    FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE,
    FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE,
    ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2,
    ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2,
    ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2,
    ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER,
    ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY,
    ARM_FSET_CPU_SUBSET): Move to ...
    * config/arm/arm-flags.h: This new file.
    * config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define.
    (EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value.
    (TARGET_MODE_SPECS): Define.
    (DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value.

    gcc/testsuite/
    * gcc.target/arm/optional_thumb-1.c: New test.
    * gcc.target/arm/optional_thumb-2.c: New test.
    * gcc.target/arm/optional_thumb-3.c: New test.

From-SVN: r242597

Make arm_feature_set agree with type of FL_* macros

2016-11-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M,
    FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED,
    FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF,
    FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON,
    FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL,
    FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1,
    FL2_ARCH8_2, FL2_FP16INST): Reindent comment, add final dot when
    missing and make value unsigned.
    (arm_feature_set): Use unsigned entries instead of unsigned long.

From-SVN: r242596

MAINTAINERS (Write After Approval): Add myself.

2016-11-18  Toma Tabacu  <toma.tabacu@imgtec.com>

* MAINTAINERS (Write After Approval): Add myself.

From-SVN: r242595

runtime: don't call __go_alloc/__go_free in environment functions

    Reviewed-on: https://go-review.googlesource.com/33363

From-SVN: r242594

libgo: remove old/regexp and old/template

    They were removed from the master Go library in 2012
    (https://golang.org/cl/5979046) but somehow that was not reflected here.

    Reviewed-on: https://go-review.googlesource.com/33391

From-SVN: r242592

S/390: Lower requirements for successful htm tests.

The attached patch makes the htm tests on s390 less sensitive to
spurious abort.  Please check the commit comment for details.  The
modified tests have been run once on a zEC12.

gcc/ChangeLog:

2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>

* config/rs6000/rs6000.c (rs6000_stack_info): PR/77359: Properly align
local variables in functions calling alloca.  Also update the ASCII
drawings
* config/rs6000/rs6000.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
PR/77359: Likewise.
* config/rs6000/aix.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
PR/77359: Copy AIX specific versions of the rs6000.h macros to aix.h.

From-SVN: r242591

Re-apply: Drop excess size used for run time allocated stack variables.

The patch got reverted after hitting PR77359 which turned out to be a
rs6000 backend problem.  Reapplying after the PR got fixed.

gcc/ChangeLog:

2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>

Re-apply after PR bootstrap/77359 is fixed:
2016-08-23  Dominik Vogt  <vogt@linux.vnet.ibm.com>

        * explow.c (get_dynamic_stack_size): Take known alignment of stack
        pointer + STACK_DYNAMIC_OFFSET into account when calculating the
        size needed.

--This line, and those below, will be
ignored--

M    gcc/ChangeLog
M    gcc/explow.c

From-SVN: r242590

RS6000: Fix PR 77359: Properly align local variables in functions calling alloca.

gcc/ChangeLog:

2016-11-18  Dominik Vogt  <vogt@linux.vnet.ibm.com>

* config/rs6000/rs6000.c (rs6000_stack_info): PR/77359: Properly align
local variables in functions calling alloca.  Also update the ASCII
drawings
* config/rs6000/rs6000.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
PR/77359: Likewise.
* config/rs6000/aix.h (STARTING_FRAME_OFFSET, STACK_DYNAMIC_OFFSET):
PR/77359: Copy AIX specific versions of the rs6000.h macros to aix.h.

From-SVN: r242589

MIPS: Check for sysroot support when upgrading/downgrading test options

gcc/testsuite/

* gcc.target/mips/inline-memcpy-1.c (dg-options): Add
(REQUIRES_STDLIB).
* gcc.target/mips/inline-memcpy-2.c: Ditto.
* gcc.target/mips/inline-memcpy-3.c: Ditto.
* gcc.target/mips/inline-memcpy-4.c: Ditto.
* gcc.target/mips/inline-memcpy-5.c: Ditto.
* gcc.target/mips/loongson-shift-count-truncated-1.c: Ditto.
* gcc.target/mips/loongson-simd.c: Ditto.
* gcc.target/mips/memcpy-1.c: Ditto.
* gcc.target/mips/mips-3d-1.c: Ditto.
* gcc.target/mips/mips-3d-2.c: Ditto.
* gcc.target/mips/mips-3d-3.c: Ditto.
* gcc.target/mips/mips-3d-4.c: Ditto.
* gcc.target/mips/mips-3d-5.c: Ditto.
* gcc.target/mips/mips-3d-6.c: Ditto.
* gcc.target/mips/mips-3d-7.c: Ditto.
* gcc.target/mips/mips-3d-8.c: Ditto.
* gcc.target/mips/mips-3d-9.c: Ditto.
* gcc.target/mips/mips-ps-1.c: Ditto.
* gcc.target/mips/mips-ps-2.c: Ditto.
* gcc.target/mips/mips-ps-3.c: Ditto.
* gcc.target/mips/mips-ps-4.c: Ditto.
* gcc.target/mips/mips-ps-6.c: Ditto.
* gcc.target/mips/mips16-attributes.c: Ditto.
* gcc.target/mips/mips32-dsp-run.c: Ditto.
* gcc.target/mips/mips32-dsp.c: Ditto.
* gcc.target/mips/save-restore-1.c: Ditto.
* gcc.target/mips/mips.exp (mips_option_groups): Add stdlib.
(mips_preprocess): Add ignore_output argument that when set
will not return the pre-processed output.
(mips_arch_info): Update arguments for the call to
mips_preprocess.
(mips-dg-init): Ditto.
(mips-dg-options): Check if a test having test option
(REQUIRES_STDLIB) has the required sysroot support for
the current test options.

Co-Authored-By: Toma Tabacu <toma.tabacu@imgtec.com>
From-SVN: r242587

Use rtx_mode_t instead of std::make_pair

This change makes the code less sensitive to the exact type of the mode,
i.e. it forces a conversion where necessary.  This becomes important
when wrappers like scalar_int_mode and scalar_mode can also be used
instead of machine_mode.

Using rtx_mode_t also abstracts away the representation.  The fact that
it's a std::pair rather than a custom class isn't important to users of
the interface.

gcc/
2016-11-18  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* combine.c (try_combine): Use rtx_mode_t instead of std::make_pair.
* dwarf2out.c (mem_loc_descriptor, loc_descriptor): Likewise.
(add_const_value_attribute): Likewise.
* explow.c (plus_constant): Likewise.
* expmed.c (expand_mult, make_tree): Likewise.
* expr.c (convert_modes): Likewise.
* loop-doloop.c (doloop_optimize): Likewise.
* postreload.c (reload_cse_simplify_set): Likewise.
* simplify-rtx.c (simplify_const_unary_operation): Likewise.
(simplify_binary_operation_1, simplify_const_binary_operation):
(simplify_const_relational_operation, simplify_immed_subreg): Likewise.
* wide-int.h: Update documentation to recommend rtx_mode_t
instead of std::make_pair.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242586

Add SET_DECL_MODE

This may no longer be necessary with the current version
of the SVE patches, but it does at least make things consistent
with the TYPE_MODE/SET_TYPE_MODE split.

gcc/ada/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
      Alan Hayward  <alan.hayward@arm.com>
      David Sherwood  <david.sherwood@arm.com>

* gcc-interface/utils.c (create_label_decl): Use SET_DECL_MODE.

gcc/c/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
      Alan Hayward  <alan.hayward@arm.com>
      David Sherwood  <david.sherwood@arm.com>

* c-decl.c (merge_decls): Use SET_DECL_MODE.
(make_label, finish_struct): Likewise.

gcc/cp/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
      Alan Hayward  <alan.hayward@arm.com>
      David Sherwood  <david.sherwood@arm.com>

* class.c (finish_struct_bits): Use SET_DECL_MODE.
(build_base_field_1, layout_class_type, finish_struct_1): Likewise.
* decl.c (make_label_decl): Likewise.
* pt.c (tsubst_decl): Likewise.

gcc/fortran/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
      Alan Hayward  <alan.hayward@arm.com>
      David Sherwood  <david.sherwood@arm.com>

* trans-common.c (build_common_decl): Use SET_DECL_MODE.
* trans-decl.c (gfc_build_label_decl): Likewise.
* trans-types.c (gfc_get_array_descr_info): Likewise.

gcc/lto/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
      Alan Hayward  <alan.hayward@arm.com>
      David Sherwood  <david.sherwood@arm.com>

* lto.c (offload_handle_link_vars): Use SET_DECL_MODE.

gcc/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
      Alan Hayward  <alan.hayward@arm.com>
      David Sherwood  <david.sherwood@arm.com>

* tree.h (SET_DECL_MODE): New macro.
* cfgexpand.c (avoid_deep_ter_for_debug): Use SET_DECL_MODE.
(expand_gimple_basic_block): Likewise.
* function.c (split_complex_args): Likeise.
* ipa-prop.c (ipa_modify_call_arguments): Likewise.
* omp-simd-clone.c (ipa_simd_modify_stmt_ops): Likewise.
* stor-layout.c (layout_decl, relayout_decl): Likewise.
(finish_bitfield_representative): Likewise.
* tree.c (make_node_stat): Likewise.
* tree-inline.c (remap_ssa_name): Likewise.
(tree_function_versioning): Likewise.
* tree-into-ssa.c (rewrite_debug_stmt_uses): Likewise.
* tree-sra.c (sra_ipa_reset_debug_stmts): Likewise.
* tree-ssa-ccp.c (optimize_atomic_bit_test_and): Likewise.
* tree-ssa-loop-ivopts.c (remove_unused_ivs): Likewise.
* tree-ssa.c (insert_debug_temp_for_var_def): Likewise.
* tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
* varasm.c (make_debug_expr_from_rtl): Likewise.

libcc1/
2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
      Alan Hayward  <alan.hayward@arm.com>
      David Sherwood  <david.sherwood@arm.com>

* plugin.cc (plugin_build_add_field): Use SET_DECL_MODE.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242585

bb-reorder: Improve compgotos pass (PR71785)

For code like the testcase in PR71785 GCC factors all the indirect branches
to a single dispatcher that then everything jumps to.  This is because
having many indirect branches with each many jump targets does not scale
in large parts of the compiler.  Very late in the pass pipeline (right
before peephole2) the indirect branches are then unfactored again, by
the duplicate_computed_gotos pass.

This pass works by replacing branches to such a common dispatcher by a
copy of the dispatcher.  For code like this testcase this does not work
so well: most cases do a single addition instruction right before the
dispatcher, but not all, and we end up with only two indirect jumps: the
one without the addition, and the one with the addition in its own basic
block, and now everything else jumps _there_.

This patch rewrites the algorithm to deal with this.  It also makes it
simpler: it does not need the "candidates" array anymore, it does not
need RTL layout mode, it does not need cleanup_cfg, and it does not
need to keep track of what blocks it already visited.

PR rtl-optimization/71785
* bb-reorder.c (maybe_duplicate_computed_goto): New function.
(duplicate_computed_gotos): New function.
(pass_duplicate_computed_gotos::execute): Rewrite.

From-SVN: r242584

Correct gcc/go/gofrontend/lex.cc and libgo/aclocal.m4 to the versions in the gofrontend repo...

Correct gcc/go/gofrontend/lex.cc and libgo/aclocal.m4 to the versions
in the gofrontend repo, which is supposed to be the master copy.

Remove a few files in libgo that somehow were not deleted in the past.

From-SVN: r242583

Update libgo/configure to restore it to the master version.

Update a few binary files that were changed in the master gc repo,
copied into the gofrontend repo, but not correctly copied into the GCC
repo.  The changes are all minor and do not affect any actual tests.
Two instances of "http" changed to "https", and two timestamps were
zeroed out.

From-SVN: r242582

Daily bump.

From-SVN: r242581

runtime, reflect: rewrite Go to FFI type conversion in Go

    As we move toward the Go 1.7 garbage collector, it's essential that all
    allocation of values that can contain Go pointers be done using the
    correct type descriptor.  That is simplest if we do all such allocation
    in Go code.  This rewrites the code that converts from a Go type to a
    libffi CIF into Go.

    Reviewed-on: https://go-review.googlesource.com/33353

From-SVN: r242578

re PR middle-end/38219 (gcc.dg/tree-ssa/vrp47.c fails on m68k)

PR middle-end/38219
* gcc.dg/tree-ssa/vrp47.c: Do not run on m68k.

From-SVN: r242576

re PR target/47192 (m68k target - gcc uses stack frame after it has been unlinked when compiling with -Os)

PR target/47192
* config/m68k/m68k.c (m68k_expand_epilogue): Emit a scheduling
barrier prior to deallocating the stack.

PR target/47192
* gcc.target/m68k/pr47192.c: New test.

From-SVN: r242575

branch-cost-1.c (dg-options): Use (HAS_MOVN) instead of isa>=4, in order to downgrade to R5.

2016-11-17  Toma Tabacu  <toma.tabacu@imgtec.com>

* gcc.target/mips/branch-cost-1.c (dg-options): Use (HAS_MOVN)
instead of isa>=4, in order to downgrade to R5.

From-SVN: r242574

PR c++/78193 - inherited ctor regressions on sparc32.

* call.c (build_over_call): Don't set CALL_FROM_THUNK_P here.
(build_call_a): Set it here, and don't insert EMPTY_CLASS_EXPR.
(convert_like_real) [ck_rvalue]: Also pass non-addressable
types along directly.

From-SVN: r242573

arc/nps400: New peephole2 pattern allow more cmem loads

In the case where we access a single bit from a value and use this in a
EQ/NE comparison, GCC will convert this into a sign-extend and GE/LT
comparison.

Normally this would be fine, however, if the value is in CMEM memory,
then we don't have a sign-extending load available (using the special
short CMEM load instructions), and instead we end up using a long form
load with LIMM, which is less efficient.

This peephole optimisation looks for the sign-extend followed by GE/LT
pattern and converts this back into a load and EQ/NE comparison.

gcc/ChangeLog:

* config/arc/arc.md (cmem bit/sign-extend peephole2): New peephole
to make better use of cmem loads in the case where a single bit is
being accessed.
* config/arc/predicates.md (ge_lt_comparison_operator): New
predicate.

gcc/testsuite/ChangeLog:

* gcc.target/arc/cmem-bit-1.c: New file.
* gcc.target/arc/cmem-bit-2.c: New file.
* gcc.target/arc/cmem-bit-3.c: New file.
* gcc.target/arc/cmem-bit-4.c: New file.

From-SVN: r242572

Add avx5124vnniw/avx5124fmaps to target attributes

gcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

* config/i386/i386.c (processor_features): Add F_AVX5124VNNIW,
F_AVX5124FMAPS.
(isa_names_table): Handle new features.

gcc/testsuite/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

* gcc.target/i386/builtin_target.c: Handle new "avx5124vnniw",
"avx5124fmaps".
* gcc.target/i386/funcspec-56.inc: Test new attributes.

libgcc/

2016-11-17  Andrew Senkevich <andrew.senkevich@intel.com>

* config/i386/cpuinfo.c (processor_features): Add
FEATURE_AVX5124VNNIW, FEATURE_AVX5124FMAPS.

From-SVN: r242570

Enable AVX512_4FMAPS and AVX512_4VNNIW instructions

This requires additional patch for register allocator from Vladimir
Makarov.

gcc/

2016-11-17  Kirill Yukhin  <kirill.yukhin@gmail.com>
    Andrew Senkevich <andrew.senkevich@intel.com>

* common/config/i386/i386-common.c
(OPTION_MASK_ISA_AVX5124FMAPS_SET,
OPTION_MASK_ISA_AVX5124FMAPS_UNSET,
OPTION_MASK_ISA_AVX5124VNNIW_SET,
OPTION_MASK_ISA_AVX5124VNNIW_UNSET): New.
(ix86_handle_option): Handle OPT_mavx5124fmaps,
OPT_mavx5124vnniw.
* config.gcc: Add avx5124fmapsintrin.h, avx5124vnniwintrin.h.
* config/i386/avx5124fmapsintrin.h: New file.
* config/i386/avx5124vnniwintrin.h: Ditto.
* config/i386/constraints.md (h): New constraint.
* config/i386/cpuid.h: (bit_AVX5124VNNIW,
bit_AVX5124FMAPS): New.
* config/i386/driver-i386.c (host_detect_local_cpu):
Detect avx5124fmaps, avx5124vnniw.
* config/i386/i386-builtin-types.def: Add types
V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI,
V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF,
V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF,
V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI,
V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI,
V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI.
* config/i386/i386-builtin.def (__builtin_ia32_4fmaddps_mask,
__builtin_ia32_4fmaddps, __builtin_ia32_4fmaddss,
__builtin_ia32_4fmaddss_mask, __builtin_ia32_4fnmaddps_mask,
__builtin_ia32_4fnmaddps, __builtin_ia32_4fnmaddss,
__builtin_ia32_4fnmaddss_mask, __builtin_ia32_vp4dpwssd,
__builtin_ia32_vp4dpwssd_mask, __builtin_ia32_vp4dpwssds,
__builtin_ia32_vp4dpwssds_mask): New.
* config/i386/i386-c.c (ix86_target_macros_internal):
Define __AVX5124FMAPS__, __AVX5124VNNIW__.
* config/i386/i386-modes.def: Fixed comment typos, added new
modes (VECTOR_MODES (FLOAT, 256), VECTOR_MODE (INT, SI, 64)).
* config/i386/i386.c (ix86_target_string): Add -mavx5124fmaps,
-mavx5124vnniw.
(PTA_AVX5124FMAPS, PTA_AVX5124VNNIW): Define.
(ix86_option_override_internal): Handle new options.
(ix86_valid_target_attribute_inner_p): Add avx5124fmaps,
avx5124vnniw.
(ix86_expand_builtin): Handle new builtins.
(ix86_additional_allocno_class_p): New.
* config/i386/i386.h (TARGET_AVX5124FMAPS,
TARGET_AVX5124FMAPS_P,
TARGET_AVX5124VNNIW,
TARGET_AVX5124VNNIW_P): Define.
(reg_class): Add MOD4_SSE_REGS.
(MOD4_SSE_REG_P, MOD4_SSE_REGNO_P): New.
* config/i386/i386.opt: Add mavx5124fmaps, mavx5124vnniw.
* config/i386/immintrin.h: Include avx5124fmapsintrin.h,
avx5124vnniwintrin.h.
* config/i386/sse.md (unspec): Add UNSPEC_VP4FMADD,
UNSPEC_VP4FNMADD,
UNSPEC_VP4DPWSSD, UNSPEC_VP4DPWSSDS.
(define_mode_iterator IMOD4): New.
(define_mode_attr imod4_narrow): Ditto.
(define_insn "mov<mode>"): Ditto.
(define_insn "avx5124fmaddps_4fmaddps"): Ditto.
(define_insn "avx5124fmaddps_4fmaddps_mask"): Ditto.
(define_insn "avx5124fmaddps_4fmaddps_maskz"): Ditto.
(define_insn "avx5124fmaddps_4fmaddss"): Ditto.
(define_insn "avx5124fmaddps_4fmaddss_mask"): Ditto.
(define_insn "avx5124fmaddps_4fmaddss_maskz"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddps"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddps_mask"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddps_maskz"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddss"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddss_mask"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddss_maskz"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssd"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssd_mask"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssd_maskz"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssds"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssds_mask"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssds_maskz"): Ditto.
* init-regs.c (initialize_uninitialized_regs): Add emit_clobber call.
* genmodes.c (mode_size_inline): Extend return type.
* machmode.h (mode_size, mode_base_align): Extend type.

gcc/testsuite/

2016-11-17  Kirill Yukhin  <kirill.yukhin@gmail.com>
    Andrew Senkevich <andrew.senkevich@intel.com>

* gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: New test.
* gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto.
* gcc.target/i386/avx5124fmaps-check.h: Ditto.
* gcc.target/i386/avx5124vnniw-check.h: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto.
* gcc.target/i386/avx512f-helper.h: Add avx5124fmaps-check.h,
avx5124vnniw-check.h.
* gcc.target/i386/i386.exp (check_effective_target_avx5124fmaps,
check_effective_target_avx5124vnniw): New.
* gcc.target/i386/m128-check.h (ESP_FLOAT, ESP_DOUBLE):
Set under ifndef.
* gcc.target/i386/sse-12.c: Add -mavx5124fmaps, -mavx5124vnniw.
* gcc.target/i386/sse-13.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.

From-SVN: r242569

re PR c++/55080 (-pedantic produces error: floating-point literal cannot appear in a constant-expression)

/cp
2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/55080
* parser.c (cp_parser_non_integral_constant_expression): Issue a
pedwarn instead of an error for case NIC_FLOAT.

/testsuite
2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/55080
* g++.dg/parse/pr55080.C: New.

From-SVN: r242565

re PR target/78101 (PowerPC 64-bit little endian fusion failure with -O3 -mcpu=power9)

[gcc]
2016-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/78101
* config/rs6000/predicates.md (fusion_addis_mem_combo_load): Add
the appropriate checks for SFmode/DFmode load/stores in GPR
registers.
(fusion_addis_mem_combo_store): Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Rename
fusion_fpr_* to fusion_vsx_* and add in support for ISA 3.0 scalar
d-form instructions for traditional Altivec registers.
(emit_fusion_p9_load): Likewise.
(emit_fusion_p9_store): Likewise.
* config/rs6000/rs6000.md (p9 fusion store peephole2): Remove
early clobber from scratch register.  Do not match if the register
being stored is the scratch register.
(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load): Rename fusion_fpr_*
to fusion_vsx_* and add in support for ISA 3.0 scalar d-form
instructions for traditional Altivec registers.
(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_load): Likewise.
(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store): Likewise.
(fusion_fpr_<P:mode>_<FPR_FUSION:mode>_store): Likewise.

[gcc/testsuite]
2016-11-17  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/78101
* gcc.target/powerpc/fusion4.c: New test.

From-SVN: r242564

PR c++/78124 - list-initialization and inherited ctor

* name-lookup.c (do_class_using_decl): Set CLASSTYPE_NON_AGGREGATE.

From-SVN: r242563

PR c++/78369 - {} as default argument

* call.c (build_special_member_call): Handle CONSTRUCTOR.

From-SVN: r242562

PR c++/68377 - parenthesized expr in fold-expression

* parser.c (cp_parser_fold_expression): Check TREE_NO_WARNING.

From-SVN: r242561

Fix PR77933: stack corruption on ARM when using high registers and LR

2016-11-17  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR target/77933
    * config/arm/arm.c (thumb1_expand_prologue): Distinguish between lr
    being live in the function and lr needing to be saved.  Distinguish
    between already saved pushable registers and registers to push.
    Check for LR being an available pushable register.

    gcc/testsuite/
    PR target/77933
    * gcc.target/arm/pr77933-1.c: New test.
    * gcc.target/arm/pr77933-2.c: Likewise.

From-SVN: r242559

i386.md (cmpstrnsi): New test to bail out if neither string input is a string constant.

2016-11-17  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

* config/i386/i386.md (cmpstrnsi): New test to bail out if neither
string input is a string constant.
* builtins.c (expand_builtin_strncmp): Attempt expansion of strncmp
via cmpstrnsi even if neither string is constant.

From-SVN: r242556

re PR middle-end/78201 (ICE in tree_to_shwi, at tree.h:4037 (seen both on ARM32 an AArch64))

PR middle-end/78201
* varasm.c (default_use_anchors_for_symbol_p): Fix a comment typo.
Don't test decl != NULL.  Don't look at DECL_SIZE, but DECL_SIZE_UNIT
instead, return false if it is NULL, or doesn't fit into uhwi, or
is larger or equal to targetm.max_anchor_offset.

* g++.dg/opt/pr78201.C: New test.

From-SVN: r242555

re PR rtl-optimization/78355 (LRA generates unaligned accesses when SLOW_UNALIGNED_ACCESS is 1)

PR rtl-optimization/78355
* doc/tm.texi.in (SLOW_UNALIGNED_ACCESS): Document that the macro only
needs to deal with unaligned accesses.
* doc/tm.texi: Regenerate.
* lra-constraints.c (simplify_operand_subreg): Only invoke
SLOW_UNALIGNED_ACCESS on innermode if the MEM is not aligned enough.

Co-Authored-By: Eric Botcazou <ebotcazou@adacore.com>
From-SVN: r242554

Fix PR78333 testcase for non-glibc systems.

2016-11-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/

* gcc.dg/pr78333.c: Add empty implementations of
__cyg_profile_func_enter() and __cyg_profile_func_exit() to avoid
problems on non-glibc systems.

From-SVN: r242553

Fix locations within raw strings

Whilst investigating PR preprocessor/78324 I noticed that the
substring location code currently doesn't handle raw strings
correctly, by not skipping the 'R', opening quote, delimiter
and opening parenthesis.

For example, an attempt to underline chars 4-7 with caret at 6 of
this raw string yields this erroneous output:
   __emit_string_literal_range (R"foo(0123456789)foo",
                                    ~~^~

With the patch, the correct range/caret is printed:

   __emit_string_literal_range (R"foo(0123456789)foo",
                                          ~~^~

gcc/ChangeLog:
* input.c (selftest::test_lexer_string_locations_long_line): New
function.
(selftest::test_lexer_string_locations_raw_string_multiline): New
function.
(selftest::input_c_tests): Call the new functions, via
for_each_line_table_case.

gcc/testsuite/ChangeLog:
* gcc.dg/plugin/diagnostic-test-string-literals-1.c
(test_raw_string_one_liner): New function.
(test_raw_string_multiline): New function.

libcpp/ChangeLog:
* charset.c (cpp_interpret_string_1): Skip locations from
loc_reader when advancing 'p' when handling raw strings.

From-SVN: r242552

[AArch64] Expand DImode constant stores to two SImode stores when profitable

* config/aarch64/aarch64.md (mov<mode>): Call
aarch64_split_dimode_const_store on DImode constant stores.
* config/aarch64/aarch64-protos.h (aarch64_split_dimode_const_store):
New prototype.
* config/aarch64/aarch64.c (aarch64_split_dimode_const_store): New
function.

* gcc.target/aarch64/store_repeating_constant_1.c: New test.
* gcc.target/aarch64/store_repeating_constant_2.c: Likewise.

From-SVN: r242551

re PR tree-optimization/77848 (Gimple if-conversion results in redundant comparisons)

[gcc]

2016-11-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
            Richard Biener  <rguenther@suse.de>

PR tree-optimization/77848
* tree-if-conv.c (tree_if_conversion): Always version loops unless
the user specified -ftree-loop-if-convert.

[gcc/testsuite]

2016-11-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
            Richard Biener  <rguenther@suse.de>

PR tree-optimization/77848
* gfortran.dg/vect/pr77848.f: New test.

Co-Authored-By: Richard Biener <rguenther@suse.de>
From-SVN: r242550

re PR target/77308 (surprisingly large stack usage for sha512 on arm)

2016-11-17  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        PR target/77308
        * config/arm/arm.md (*thumb2_ldrd, *thumb2_ldrd_base,
        *thumb2_ldrd_base_neg, *thumb2_strd, *thumb2_strd_base,
        *thumb2_strd_base_neg): Recognize insn regardless of
        current_tune->prefer_ldrd_strd.
        * config/arm/ldrdstrd.md: Enable all ldrd/strd peephole rules
        whenever possible.

testsuite:
2016-11-17  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        PR target/77308
        * gcc.target/arm/pr53447-5.c: New test.
        * lib/target-supports.exp
        (check_effective_target_arm_prefer_ldrd_strd): Adjust.

From-SVN: r242549

[ARC] Fix compilation issue in pr71872.

gcc/
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/arc.c (arc_ccfsm_post_advance): Handle return
instruction type.

From-SVN: r242548

[ARC][libgcc] Add support for QuarkSE processor.

libgcc/
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/dp-hack.h (ARC_OPTFPE): Define.
(__ARC_NORM__): Use instead ARC_OPTFPE.
* config/arc/fp-hack.h: Likewise.
* config/arc/lib1funcs.S (ARC_OPTFPE): Define.
(__ARC_MPY__): Use it insetead of __ARC700__ and __HS__.

From-SVN: r242547

[ARC] Add support for QuarkSE processor.

gcc/
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/arc-arches.def: Add FPX quarkse instruction as valid
for arcem.
* config/arc/arc-c.def (__ARC_FPX_QUARK__): Define.
* config/arc/arc-cpus.def (quarkse_em): Add.
* config/arc/arc-options.def (FL_FPX_QUARK, FL_QUARK): Likewise.
* config/arc/arc-opts.h (FPX_QK): Define.
* config/arc/arc-tables.opt: Regenerate.
* config/arc/arc.c (gen_compare_reg): Change.
(arc_register_move_cost): Avoid Dy,Dx moves.
* config/arc/arc.h (TARGET_HARD_FLOAT): Change.
(TARGET_FPX_QUARK, TARGET_FP_ASSIST): Define.
* config/arc/arc.md (divsf3, sqrtsf2, fix_truncsfsi2, floatsisf2):
New expands.
* config/arc/fpu.md (divsf3_fpu, sqrtsf2_fpu, floatsisf2_fpu)
(fix_truncsfsi2_fpu): Rename.
* config/arc/fpx.md (cmp_quark, cmpsf_quark_, cmpsf_quark_ord)
(cmpsf_quark_uneq, cmpsf_quark_eq, divsf3_quark, sqrtsf2_quark)
(fix_truncsfsi2_quark, floatsisf2_quark): New patterns.
* config/arc/t-multilib: Regenerate.

From-SVN: r242546

[ARC] Update target specific tests.

gcc/testsuite
2016-11-17  Claudiu Zissulescu  <claziss@synopsys.com>

* gcc.target/arc/abitest.S: New file.
* gcc.target/arc/abitest.h: Likewise.
* gcc.target/arc/va_args-1.c: Likewise.
* gcc.target/arc/va_args-2.c: Likewise.
* gcc.target/arc/va_args-3.c: Likewise.
* gcc.target/arc/mcrc.c: Deleted.
* gcc.target/arc/mdsp-packa.c: Likewise.
* gcc.target/arc/mdvbf.c: Likewise.
* gcc.target/arc/mmac-24.c: Likewise.
* gcc.target/arc/mmac-d16.c: Likewise.
* gcc.target/arc/mno-crc.c: Likewise.
* gcc.target/arc/mno-dsp-packa.c: Likewise.
* gcc.target/arc/mno-dvbf.c: Likewise.
* gcc.target/arc/mno-mac-24.c: Likewise.
* gcc.target/arc/mno-mac-d16.c: Likewise.
* gcc.target/arc/mno-rtsc.c: Likewise.
* gcc.target/arc/mno-xy.c: Likewise.
* gcc.target/arc/mrtsc.c: Likewise.
* gcc.target/arc/arc.exp (check_effective_target_arcem):
New function.
(check_effective_target_arc700): Likewise.
(check_effective_target_arc6xx): Likewise.
(check_effective_target_arcmpy): Likewise.
(check_effective_target_archs): Likewise.
(check_effective_target_clmcpu): Likewise.
(check_effective_target_barrelshifter): Likewise.
* gcc.target/arc/barrel-shifter-1.c: Changed.
* gcc.target/arc/builtin_simd.c: Test only for ARC700
cpus.
* gcc.target/arc/cmem-1.c: Changed.
* gcc.target/arc/cmem-2.c: Likewise.
* gcc.target/arc/cmem-3.c: Likewise.
* gcc.target/arc/cmem-4.c: Likewise.
* gcc.target/arc/cmem-5.c: Likewise.
* gcc.target/arc/cmem-6.c: Likewise.
* gcc.target/arc/cmem-7.c: Likewise.
* gcc.target/arc/interrupt-1.c: Test for RTIE as well.
* gcc.target/arc/interrupt-2.c: Skip it for ARCv2 cores.
* gcc.target/arc/interrupt-3.c: Match also ARCv2
warnings.
* gcc.target/arc/jump-around-jump.c: Update options.
* gcc.target/arc/mARC601.c: Changed.
* gcc.target/arc/mcpu-arc600.c: Changed.
* gcc.target/arc/mcpu-arc601.c: Changed.
* gcc.target/arc/mcpu-arc700.c: Changed.
* gcc.target/arc/mdpfp.c: Skip for ARCv2 cores.
* gcc.target/arc/movb-1.c: Changed.
* gcc.target/arc/movb-2.c: Likewise.
* gcc.target/arc/movb-3.c: Likewise.
* gcc.target/arc/movb-4.c: Likewise.
* gcc.target/arc/movb-5.c: Likewise.
* gcc.target/arc/movb_cl-1.c: Likewise.
* gcc.target/arc/movb_cl-2.c: Likewise.
* gcc.target/arc/movbi_cl-1.c: Likewise.
* gcc.target/arc/movh_cl-1.c: Likewise.
* gcc.target/arc/mspfp.c: Skip for ARC HS cores.
* gcc.target/arc/mul64.c: Enable it only for ARC600.
* gcc.target/arc/mulsi3_highpart-1.c: Scan for ARCv2
instructions.
* gcc.target/arc/mulsi3_highpart-2.c: Skip it for ARCv1
cores.
* gcc.target/arc/no-dpfp-lrsr.c: Skip it for ARC HS.
* gcc.target/arc/trsub.c: Only for ARC EM cores.
* gcc.target/arc/builtin_simdarc.c: Changed.
* gcc.target/arc/extzv-1.c: Likewise.
* gcc.target/arc/insv-1.c: Likewise.
* gcc.target/arc/insv-2.c: Likewise.
* gcc.target/arc/mA6.c: Likewise.
* gcc.target/arc/mA7.c: Likewise.
* gcc.target/arc/mARC600.c: Likewise.
* gcc.target/arc/mARC700.c: Likewise.
* gcc.target/arc/mcpu-arc600.c: Likewise.
* gcc.target/arc/mcpu-arc700.c: Likewise.
* gcc.target/arc/movl-1.c: Likewise.
* gcc.target/arc/nps400-1.c: Likewise.
* gcc.target/arc/trsub.c: Likewise.
* gcc.target/arc/barrel-shifter-2.c: Check for barrel
shifter configuration.
* gcc.target/arc/mlock.c: Skip for arc6xx
configurations.
* gcc.target/arc/mswape.c: Likewise.

From-SVN: r242545

avr.c (avr_print_operand_address): Use CONST_INT_P if appropriate.

* config/avr/avr.c (avr_print_operand_address): Use CONST_INT_P if
appropriate.
(ashlqi3_out, ashlsi3_out, ashrqi3_out, ashrhi3_out): Same.
(ashrsi3_out, lshrqi3_out, lshrhi3_out, lshrsi3_out): Same.
(avr_rtx_costs_1, extra_constraint_Q): Same.
(avr_address_cost): Use SUBREG_P if possible.

From-SVN: r242544

re PR c++/78383 (label as values ICE with C++ lambda)

2016-11-17  Richard Biener  <rguenther@suse.de>

PR middle-end/78383
* tree-cfgcleanup.c (cleanup_control_flow_bb): Do not turn
non-local goto into CFG.

From-SVN: r242543

common.opt (ftree-loop-if-convert-stores): Mark as preserved for backward compatibility.

2016-11-17  Richard Biener  <rguenther@suse.de>

* common.opt (ftree-loop-if-convert-stores): Mark as preserved for
backward compatibility.
* doc/invoke.texi (ftree-loop-if-convert-stores): Remove.
* tree-if-conv.c (pass_if_conversion::gate): Do not test
flag_tree_loop_if_convert_stores.
(pass_if_conversion::execute): Likewise.

From-SVN: r242542

re PR c++/68180 ([ICE]  at cp/constexpr.c:2768 in initializing __vector in a loop)

2016-11-17  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/68180
* g++.dg/cpp1y/pr68180.C: New.

From-SVN: r242541

re PR tree-optimization/78319 (PASS->FAIL: gcc.dg/uninit-pred-8_a.c bogus warning (test for bogus messages, line 20))

2016-11-17  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

PR tree-optimization/78319

testsuite/
* gcc.dg/uninit-pred-8_a.c (foo): Mark dg-bogus test to xfail on
arm-none-eabi.

From-SVN: r242540

[AArch64] Fix gcc.dg/torture/float32-builtin.c with RTL checking

    * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): Check for
    const_double code before calling aarch64_float_const_zero_rtx_p.

From-SVN: r242539

re PR middle-end/78306 ([CilkPlus] "inlining failed in call to always_inline ‘memset’: function not inlinable" with -fcilkplus)

2016-11-17  Richard Biener  <rguenther@suse.de>

PR tree-optimization/78306
* ipa-inline-analysis.c (initialize_inline_failed): Do not
inhibit inlining if function calls cilk_spawn.
(can_inline_edge_p): Likewise.

* gcc.dg/cilk-plus/pr78306.c: New testcase.

From-SVN: r242537

re PR tree-optimization/78305 (Wrong constant folding)

2016-11-17  Richard Biener  <rguenther@suse.de>

PR middle-end/78305
* fold-const.c (negate_expr_p): Fix multiplication case.

* gcc.dg/torture/pr78305.c: New testcase.

From-SVN: r242536

re PR fortran/66227 ([OOP] EXTENDS_TYPE_OF n returns wrong result for polymorphic variable allocated to extended type)

2016-11-17  Janus Weil  <janus@gcc.gnu.org>

PR fortran/66227
* simplify.c (gfc_simplify_extends_type_of): Fix missed optimization.
Prevent over-simplification. Fix a comment. Add a comment.

2016-11-17  Janus Weil  <janus@gcc.gnu.org>

PR fortran/66227
* gfortran.dg/extends_type_of_3.f90: Fix and extend the test case.

From-SVN: r242535

re PR target/78357 (nios2 uses non-standard atomic functions)

2016-11-17  Chung-Lin Tang  <cltang@codesourcery.com>

PR target/78357
* config/nios2/nios2.c (nios2_init_libfuncs): Remove TARGET_LINUX_ABI
condition.
(TARGET_INIT_LIBFUNCS): Delete definition and...
* config/nios2/linux.h (TARGET_INIT_LIBFUNCS): ...move to here, add
comments.

From-SVN: r242534

netbsd-stdint.h: New.

2016-11-17  Krister Walfridsson  <krister.walfridsson@gmail.com>

* config/netbsd-stdint.h: New.
* config.gcc (i[34567]86-*-netbsd): Add netbsd-stdint.h to tm_file.
(x86_64-*-netbsd*): Likewise.

From-SVN: r242533

re PR c/78285 (error on duplicate switch label where a note should be)

PR c/78285
* c-common.c (c_add_case_label): Turn error_at calls into inform.

* gcc.dg/switch-5.c: Turn several dg-errors into dg-messages.
* g++.dg/ext/case-range2.C: Likewise.

From-SVN: r242532

aarch64.opt (mverbose-cost-dump): New option.

2016-11-16  Andrew PInski  <apinski@cavium.com>

        * config/aarch64/aarch64.opt (mverbose-cost-dump): New option.
        * config/aarch64/aarch64.c (aarch64_rtx_costs): Use
        flag_aarch64_verbose_cost instead of checking for details dump.
        (aarch64_rtx_costs_wrapper): Likewise.

From-SVN: r242531

re PR fortran/58001 (Make it possible to silence "Extension: Tab character in format" warning)

2016-11-16  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/58001
* io.c (next_char_not_space): Update handling of a 'tab' in a FORMAT.
  (format_lex): Adjust invocations of next_char_not_space().

2016-11-16  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/58001
* gfortran.dg/fmt_tab_1.f90: Adjust testcase.
* gfortran.dg/fmt_tab_2.f90: Ditto.

From-SVN: r242530

Daily bump.

From-SVN: r242529

re PR rtl-optimization/78378 (wrong code when combining shift + mult + zero_extend)

PR rtl-optimization/78378
* combine.c (make_extraction): Use force_to_mode for non-{REG,MEM}
inner only if pos is 0.  Fix up formatting.

* gcc.c-torture/execute/pr78378.c: New test.

From-SVN: r242526

R_MIPS_JALR failures

This is a fix for my PR70890 patch, which incorrectly removed all
REG_EQUIV notes rather than just one regarding a reg that dies.

PR rtl-optimization/78325
PR rtl-optimization/70890
* ira.c (combine_and_move_insns): Only remove REG_EQUIV notes
for dead regno.

From-SVN: r242525

libiberty: Add Rust symbol demangling.

Adds Rust symbol demangler. Rust mangles symbols using GNU_V3 style,
adding a hash and various special character subtitutions. This adds
a new rust style to cplus_demangle and adds 3 helper functions
rust_demangle, rust_demangle_sym and rust_is_mangled.

rust-demangle.c was written by David. Mark did the code formatting to
GNU style and integration into the gcc/libiberty build system and
testsuite.

include/ChangeLog:

2016-11-03  David Tolnay <dtolnay@gmail.com>
           Mark Wielaard  <mark@klomp.org>

       * demangle.h (DMGL_RUST): New macro.
       (DMGL_STYLE_MASK): Add DMGL_RUST.
       (demangling_styles): Add dlang_rust.
       (RUST_DEMANGLING_STYLE_STRING): New macro.
       (RUST_DEMANGLING): New macro.
       (rust_demangle): New prototype.
       (rust_is_mangled): Likewise.
       (rust_demangle_sym): Likewise.

libiberty/ChangeLog:

2016-11-03  David Tolnay <dtolnay@gmail.com>
           Mark Wielaard  <mark@klomp.org>

       * Makefile.in (CFILES): Add rust-demangle.c.
       (REQUIRED_OFILES): Add rust-demangle.o.
       * cplus-dem.c (libiberty_demanglers): Add rust_demangling case.
       (cplus_demangle): Handle RUST_DEMANGLING.
       (rust_demangle): New function.
       * rust-demangle.c: New file.
       * testsuite/Makefile.in (really-check): Add check-rust-demangle.
       (check-rust-demangle): New rule.
       * testsuite/rust-demangle-expected: New file.

Co-Authored-By: Mark Wielaard <mark@klomp.org>
From-SVN: r242524

PR c++/78373 - ICE with TREE_CONSTANT reference

* decl.c (cp_finish_decl): Don't set TREE_CONSTANT on a reference.
* typeck2.c (store_init_value): Likewise.

From-SVN: r242523

* rtl.h: Declare gt_ggc_mx and gt_pch_nx.

From-SVN: r242522

Commentary corrections

From-SVN: r242521

re PR tree-optimization/77848 (Gimple if-conversion results in redundant comparisons)

2016-11-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

PR tree-optimization/77848
* tree-if-conv.c (version_loop_for_if_conversion): When versioning
an outer loop, only save basic block aux information for the inner
loop.
(versionable_outer_loop_p): New function.
(tree_if_conversion): Version the outer loop instead of the inner
one if the pattern will be recognized for outer-loop
vectorization.

From-SVN: r242520

gcc: remove unneeded global related to hot/cold partitioning

The `user_defined_section_attribute' is used as part of the condition to
determine if GCC should partition blocks within a function into hot and
cold blocks.  This global is initially false, and is set to true from
within the file parse phase of GCC, as part of the attribute handling
hook.

The `user_defined_section_attribute' is reset to false as part of the
final pass of GCC.  However, the final pass is part of the optimisation
phase of the compiler, and so if at any point during the file parse
phase any function, or data, has a section attribute the global
`user_defined_section_attribute' will be set to true.

When GCC performs the block partitioning pass on the first function, if
`user_defined_section_attribute' is true then the function will not be
partitioned.  Notice though, that due to the above, whether we partition
this first function or not has nothing to do with whether the function
has a section attribute, instead, if any function or data in the parsed
file has a section attribute then we don't partition the first
function.

After performing (or not) the block partitioning pass on the first
function we perform the final pass on the first function, at which point
we reset `user_defined_section_attribute' to false.  As parsing is
complete by this point, we will never set
`user_defined_section_attribute' to true after that, and so all of the
following functions will have the partition blocks pass performed on
them, even if the function has a section attribute, and will not be
partitioned.

Luckily we don't end up partitioning functions that should not be
partitioned though.  Due to the way that functions are selected during
the assembler writing phase, if a function has a section attribute this
takes priority over any hot/cold block partitioning that has been done.

What we see from the above then is that the
`user_defined_section_attribute' mechanism is broken.  It was originally
created when GCC parsed, optimised, and generated assembler function at
a time.  Now that we deal with the whole file in one go, we need to
update the mechanism used to gate the block partitioning pass.

This patch does this by looking specifically for a section attribute on
the function DECL, which removes the need for a global variable, and
will work whether we parse the whole file in one go, or one function at
a time.

A few new tests have been added.  These check for the case where a
function is not partitioned when it could be.

gcc/ChangeLog:

* gcc/bb-reorder.c: Remove 'toplev.h' include.
(pass_partition_blocks::gate): No longer check
user_defined_section_attribute, instead check the function decl
for a section attribute.
* gcc/c-family/c-attribs.c (handle_section_attribute): No longer
set user_defined_section_attribute.
* gcc/final.c (rest_of_handle_final): Likewise.
* gcc/toplev.c: Remove definition of user_defined_section_attribute.
* gcc/toplev.h: Remove declaration of
user_defined_section_attribute.

gcc/testsuiteChangeLog:

* gcc.dg/tree-prof/section-attr-1.c: New file.
* gcc.dg/tree-prof/section-attr-2.c: New file.
* gcc.dg/tree-prof/section-attr-3.c: New file.

From-SVN: r242519

re PR libfortran/51119 (MATMUL slow for large matrices)

2016-11-16  Jerry DeLisle  <jvdelisle@gcc.gnu.org>

PR libgfortran/51119
* Makefile.am: Remove -fno-protect-parens -fstack-arrays.
* Makefile.in: Regenerate.

From-SVN: r242518

MIPS16/GCC: Emit explicit JRC from `casesi_internal_mips16_<mode>' insn

gcc/
* config/mips/mips.md (casesi_internal_mips16_<mode>):
Explicitly switch between JR and JRC for the table jump.  Adjust
instruction count.

From-SVN: r242517

MIPS16/GCC: Improve `casesi_internal_mips16_<mode>'s instruction count estimate

gcc/
* config/mips/mips.md (casesi_internal_mips16_<mode>): Set
`insn_count' to 11 rather than 16.

From-SVN: r242516

MIPS16/GCC: Correct `casesi_internal_mips16_<mode>'s RTL pattern

gcc/
* config/mips/mips.md (casesi_internal_mips16_<mode>): Use the
`ltu' rather than `leu' operation in the RTL pattern

From-SVN: r242515

MIPS16/GCC: Fix DImode `casesi_internal_mips16_<mode>' assembly instructions

gcc/
* config/mips/mips.md (casesi_internal_mips16_<mode>): Add
missing <d> instruction prefixes throughout.  Correct
formatting.

gcc/testsuite/
* gcc.target/mips/code-readable-4.c (dg-final): Expect `dla'
rather than `la'.

From-SVN: r242514

Fix tuple decomposition decltype.

* decl.c (store_decomp_type, lookup_decomp_type): New.
(cp_finish_decomp): Call store_decomp_type.
* semantics.c (finish_decltype_type): Call lookup_decomp_type.
* cp-tree.h: Declare lookup_decomp_type.

From-SVN: r242513

microMIPS/GCC: Fix PIC call relaxation

gcc/
* config/mips/mips.c (mips_output_jump): Output R_MICROMIPS_JALR
rather than R_MIPS_JALR relocation in microMIPS code.  Do not
cancel short delay slots in PIC call relaxation.

gcc/testsuite/
* gcc.target/mips/call-1.c (dg-options): Add `-mno-micromips'.
(dg-final): Remove microMIPS JALRS mnemonic matching.
* gcc.target/mips/call-2.c (dg-options): Add `-mno-micromips'.
(dg-final): Remove microMIPS JALRS mnemonic matching.
* gcc.target/mips/call-3.c (dg-options): Add `-mno-micromips'.
(dg-final): Remove microMIPS JALRS mnemonic matching.
* gcc.target/mips/call-4.c (dg-options): Add `-mno-micromips'.
* gcc.target/mips/call-5.c (dg-options): Add `-mno-micromips'.
* gcc.target/mips/call-6.c (dg-options): Add `-mno-micromips'.
* gcc.target/mips/call-1u.c: New test case.
* gcc.target/mips/call-2u.c: New test case.
* gcc.target/mips/call-3u.c: New test case.
* gcc.target/mips/call-4u.c: New test case.
* gcc.target/mips/call-5u.c: New test case.
* gcc.target/mips/call-6u.c: New test case.

From-SVN: r242512

re PR bootstrap/72823 (r239175 causes build failure)

PR bootstrap/72823
* configure.ac (ENABLE_ASSERT_CHECKING): Define if gcc configure
would define that macro.
* configure: Regenerated.
* config.in: Regenerated.

From-SVN: r242510

runtime: replace runtime1.goc with Go and C code

    A step toward eliminating goc2c.

    Drop the exported parfor code; it was needed for tests in the past, but
    no longer is. The Go 1.7 runtime no longer uses parfor.

    Reviewed-on: https://go-review.googlesource.com/33324

From-SVN: r242509

Fix ICE on empty FIQ interrupt handler on ARM

2016-11-16  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm.md (arm_addsi3): Add alternative for addition of
    general register with general register or ARM constant into SP
    register.

    gcc/testsuite/
    * gcc.target/arm/empty_fiq_handler.c: New test.

From-SVN: r242508

re PR fortran/78299 (ICE in expand_omp_for_static_nochunk, at omp-low.c:9622)

PR fortran/78299
* omp-low.c (expand_omp_for_static_nochunk): Don't assert
that loop->header == body_bb if broken_loop.

* gfortran.dg/gomp/pr78299.f90: New test.

From-SVN: r242507

Looking at PR77308, one of the issues is that the bswap optimization phase doesn't work on ARM.

Looking at PR77308, one of the issues is that the bswap optimization
phase doesn't work on ARM.  This is due to an odd check that uses
SLOW_UNALIGNED_ACCESS (which is always true on ARM).  Since the testcase
in PR77308 generates much better code with this patch (~13% fewer
instructions), it seems best to remove this check.

    gcc/
* tree-ssa-math-opts.c (bswap_replace): Remove test
of SLOW_UNALIGNED_ACCESS.

    testsuite/
* gcc.dg/optimize-bswapdi-3.c: Remove xfail.
* gcc.dg/optimize-bswaphi-1.c: Likewise.
* gcc.dg/optimize-bswapsi-2.c: Likewise.

From-SVN: r242506

[PR libgfortran/78314] Fix ieee_support_halting

ieee_support_halting only checked the availability of status
flags, not trapping support.  On some targets the later can
only be checked at runtime: feenableexcept reports if
enabling traps failed.

So check trapping support by enabling/disabling it.

Updated the test that enabled trapping to check if it is
supported.

gcc/testsuite/

PR libgfortran/78314
* gfortran.dg/ieee/ieee_6.f90: Use ieee_support_halting.

libgfortran/

PR libgfortran/78314
* config/fpu-glibc.h (support_fpu_trap): Use feenableexcept.

From-SVN: r242505

ivopts-orig_biv-inc.c: Adjust test string according to updated dump info.

gcc/testsuite
* gcc.target/arm/ivopts-orig_biv-inc.c: Adjust test string
according to updated dump info.

From-SVN: r242504

nvptx backend prerequisites for OpenMP offloading

gcc/
* config/nvptx/mkoffload.c (main): Check that either OpenACC or OpenMP
is selected.  Pass -mgomp to offload compiler in OpenMP case.
* config/nvptx/nvptx-protos.h (nvptx_shuffle_kind): Move enum
declaration from nvptx.c.
(nvptx_gen_shuffle): Declare.
(nvptx_output_set_softstack): Declare.
* config/nvptx/nvptx.c (nvptx_shuffle_kind): Move to nvptx-protos.h.
(need_softstack_decl): New variable.
(need_unisimt_decl): New variable.
(diagnose_openacc_conflict): New.  Use it...
(nvptx_option_override): ...here.  Handle TARGET_GOMP.
(nvptx_encode_section_info): Handle "shared" attribute.
(write_as_kernel): Restrict to OpenACC target regions.
(init_softstack_frame): New.
(nvptx_init_unisimt_predicate): New.
(write_omp_entry): New.  Use it...
(nvptx_declare_function_name): ...here to emit OpenMP target region
entrypoints.  Handle TARGET_SOFT_STACK.  Call
nvptx_init_unisimt_predicate.
(nvptx_output_set_softstack): New.
(nvptx_get_drap_rtx): Return %argp as the DRAP if needed.
(nvptx_gen_shuffle): Export.
(nvptx_output_call_insn): Handle COND_EXEC patterns.  Emit instruction
predicate.
(nvptx_print_operand): Fix handling of instruction predicates.
(nvptx_get_unisimt_master): New helper function.
(nvptx_get_unisimt_predicate): Ditto.
(nvptx_call_insn_is_syscall_p): Ditto.
(nvptx_unisimt_handle_set): Ditto.
(nvptx_reorg_uniform_simt): New.  Transform code for -muniform-simt.
(nvptx_reorg): Call nvptx_reorg_uniform_simt.
(nvptx_handle_shared_attribute): New.  Use it...
(nvptx_attribute_table): ... here (new entry).
(nvptx_record_offload_symbol): Handle NULL attributes.
(nvptx_file_end): Handle need_softstack_decl and need_unisimt_decl.
(nvptx_simt_vf): New.
(TARGET_SIMT_VF): Define.
* config/nvptx/nvptx.h (TARGET_CPU_CPP_BUILTINS): Define
__nvptx_softstack or __nvptx_unisimt__ when -msoft-stack, or resp.
-muniform-simt option is active.
(STACK_SIZE_MODE): Define.
(FIXED_REGISTERS): Adjust.
(SOFTSTACK_SLOT_REGNUM): New.
(SOFTSTACK_PREV_REGNUM): New.
(REGISTER_NAMES): Adjust.
(struct machine_function): New fields.
* config/nvptx/nvptx.md (UNSPEC_SET_SOFTSTACK): New.
(UNSPEC_VOTE_BALLOT): Ditto.
(UNSPEC_LANEID): Ditto.
(UNSPECV_NOUNROLL): Ditto.
(atomic): New attribute.
(predicable): New attribute.  Generate predicated forms via
define_cond_exec.
(br_true): Mark as not predicable.
(br_false): Ditto.
(br_true_uni): Ditto.
(br_false_uni): Ditto.
(return): Ditto.
(trap_if_true): Ditto.
(trap_if_false): Ditto.
(nvptx_fork): Ditto.
(nvptx_forked): Ditto.
(nvptx_joining): Ditto.
(nvptx_join): Ditto.
(nvptx_barsync): Ditto.
(epilogue): Emit stack restore if TARGET_SOFT_STACK.
(allocate_stack): Implement for TARGET_SOFT_STACK.  Remove unused code.
(allocate_stack_<mode>): Remove unused pattern.
(set_softstack_insn): New pattern.
(restore_stack_block): Handle for TARGET_SOFT_STACK.
(nvptx_vote_ballot): New pattern.
(omp_simt_lane): Ditto.
(omp_simt_last_lane): Ditto.
(omp_simt_ordered): Ditto.
(omp_simt_vote_any): Ditto.
(omp_simt_xchg_bfly): Ditto.
(omp_simt_xchg_idx): Ditto.
(nvptx_nounroll): Ditto.
(atomic_compare_and_swap<mode>_1): Mark with atomic attribute.
(atomic_exchange<mode>): Ditto.
(atomic_fetch_add<mode>): Ditto.
(atomic_fetch_addsf): Ditto.
(atomic_fetch_<logic><mode>): Ditto.
* config/nvptx/nvptx.opt: (msoft-stack): New option.
(muniform-simt): Ditto.
(mgomp): Ditto.
* config/nvptx/t-nvptx (MULTILIB_OPTIONS): New.
* doc/extend.texi (Nvidia PTX Variable Attributes): New section.
* doc/invoke.texi (msoft-stack): Document.
(muniform-simt): Document
(mgomp): Document.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in: (TARGET_SIMT_VF): New hook.
* target.def: Define it.
* target-insns.def (omp_simt_lane): New.
(omp_simt_last_lane): New.
(omp_simt_ordered): New.
(omp_simt_vote_any): New.
(omp_simt_xchg_bfly): New.
(omp_simt_xchg_idx): New.

libgcc/
* config/nvptx/crt0.c (__main): Setup __nvptx_stacks and __nvptx_uni.
* config/nvptx/mgomp.c: New file.
* config/nvptx/t-nvptx: Add mgomp.c

gcc/testsuite/
* lib/target-supports.exp (check_effective_target_alloca): Use a
compile test.
* gcc.target/nvptx/softstack.c: New test.
* gcc.target/nvptx/decl-shared.c: New test.
* gcc.target/nvptx/decl-shared-init.c: New test.

From-SVN: r242503

MIPS/GCC: Mark text contents as code or data

gcc/
* config/mips/mips-protos.h (mips_set_text_contents_type): New
prototype.
* config/mips/mips.h (ASM_OUTPUT_BEFORE_CASE_LABEL): New macro.
(ASM_OUTPUT_CASE_END): Likewise.
* config/mips/mips.c (mips_set_text_contents_type): New
function.
(mips16_emit_constants): Record the pool's initial label number
with the `consttable' insn.  Emit a `consttable_end' insn at the
end.
(mips_final_prescan_insn): Call `mips_set_text_contents_type'
for `consttable' insns.
(mips_final_postscan_insn): Call `mips_set_text_contents_type'
for `consttable_end' insns.
* config/mips/mips.md (unspec): Add UNSPEC_CONSTTABLE_END enum
value.
(consttable): Add operand.
(consttable_end): New insn.

gcc/testsuite/
* gcc.target/mips/data-sym-jump.c: New test case.
* gcc.target/mips/data-sym-pool.c: New test case.
* gcc.target/mips/insn-pseudo-4.c: Adjust for constant pool
annotation.

From-SVN: r242502

Support non-masked epilogue vectoriziation

gcc/

2016-11-16  Yuri Rumyantsev  <ysrumyan@gmail.com>

* params.def (PARAM_VECT_EPILOGUES_NOMASK): New.
* tree-if-conv.c (tree_if_conversion): Make public.
* * tree-if-conv.h: New file.
* tree-vect-data-refs.c (vect_analyze_data_ref_dependences) Avoid
dynamic alias checks for epilogues.
* tree-vect-loop-manip.c (vect_do_peeling): Return created epilog.
* tree-vect-loop.c: include tree-if-conv.h.
(new_loop_vec_info): Add zeroing orig_loop_info field.
(vect_analyze_loop_2): Don't try to enhance alignment for epilogues.
(vect_analyze_loop): Add argument ORIG_LOOP_INFO which is not NULL
if epilogue is vectorized, set up orig_loop_info field of loop_vinfo
using passed argument.
(vect_transform_loop): Check if created epilogue should be returned
for further vectorization with less vf.  If-convert epilogue if
required. Print vectorization success for epilogue.
* tree-vectorizer.c (vectorize_loops): Add epilogue vectorization
if it is required, pass loop_vinfo produced during vectorization of
loop body to vect_analyze_loop.
* tree-vectorizer.h (struct _loop_vec_info): Add new field
orig_loop_info.
(LOOP_VINFO_ORIG_LOOP_INFO): New.
(LOOP_VINFO_EPILOGUE_P): New.
(LOOP_VINFO_ORIG_VECT_FACTOR): New.
(vect_do_peeling): Change prototype to return epilogue.
(vect_analyze_loop): Add argument of loop_vec_info type.
(vect_transform_loop): Return created loop.

gcc/testsuite/

2016-11-16  Yuri Rumyantsev  <ysrumyan@gmail.com>

* lib/target-supports.exp (check_avx2_hw_available): New.
(check_effective_target_avx2_runtime): New.
* gcc.dg/vect/vect-tail-nomask-1.c: New test.

From-SVN: r242501

Fix test names for trad.exp tests

 PR testsuite/78136
 * gcc.dg/cpp/trad/trad.exp
 (dg-runtest): Moved $srcdir/$subdir/ to DEFAULT_TRADCPPFLAGS.

From-SVN: r242500

df: Change defs in entry and uses in exit block during separate shrink-wrapping

So far all target implementations of the separate shrink-wrapping hooks
use the DF LIVE info to figure out around which basic blocks the non-
volatile registers need to be saved.  This is done by looking at the
IN+GEN+KILL sets of the basic blocks.  However, that doesn't work for
registers that DF says are defined in the entry block, or used in the
exit block.

This patch introduces a local flag DF_SCAN_EMPTY_ENTRY_EXIT that says
no registers should be defined in the entry block, and none used in the
exit block.  It also makes try_shrink_wrapping_separate use it.  The
rs6000 port is changed to use IN+GEN+KILL for the LR component.

* config/rs6000/rs6000.c (rs6000_components_for_bb): Mark the LR
component as used also if LR_REGNO is a live input to the bb.
* df-scan.c (df_get_entry_block_def_set): Return immediately after
clearing the set if DF_SCAN_EMPTY_ENTRY_EXIT is set.
(df_get_exit_block_use_set): Ditto.
* df.h (df_scan_flags): New enum.
* shrink-wrap.c (try_shrink_wrapping_separate): Set
DF_SCAN_EMPTY_ENTRY_EXIT in df_scan->local_flags, and call
df_update_entry_block_defs and df_update_exit_block_uses
at the start; clear the flag and call those functions at the end.

From-SVN: r242497

compiler: separate incomparable types from comparable ones

    Otherwise we can accidentally and incorrectly mark an actual user type
    as incomparable.  This fixes the gccgo version of
    https://golang.org/issue/17752.  The test case for gccgo is
    https://golang.org/cl/33249.

    Reviewed-on: https://go-review.googlesource.com/33292

From-SVN: r242494

Fix nb_iterations calculation in tree-vect-loop-manip.c

We previously stored the number of loop iterations rather
than the number of latch iterations.

gcc/
2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* tree-vect-loop-manip.c (slpeel_make_loop_iterate_ntimes): Set
nb_iterations to the number of latch iterations rather than the
number of loop iterations.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242493

An alternative fix for PR70944

The transformations made by make_compound_operation apply
only to scalar integer modes.  The fix for PR70944 had enforced
that by returning early for vector modes at the top of the
function.  However, the function is supposed to be recursive,
so we should continue to look at integer suboperands even if
the outer operation is a vector one.

This patch instead splits out the non-recursive parts
of make_compound_operation into a subroutine and checks
that the mode is a scalar integer before calling it.
The patch was originally written to help with the later
conversion to static type checking of mode classes, but it
also happened to reenable optimisation of things like
vec_duplicate operands.

Note that the gen_lowparts in the PLUS and MINUS cases
were redundant, since new_rtx already had mode "mode"
at those points.

gcc/
2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* combine.c (maybe_swap_commutative_operands): New function.
(combine_simplify_rtx): Use it.
(change_zero_ext): Likewise.
(make_compound_operation_int): New function, split out of...
(make_compound_operation): ...here.  Use
maybe_swap_commutative_operands for both.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242492

[arm] Add vfpv2 and neon-vfpv3

* arm/arm-fpus.def (vfpv2): New FPU, currently an alias for 'vfp'.
(neon-vfpv3): New FPU, currently an alias for 'neon'.
* arm/arm-tables.opt: Regenerated.
        * arm/t-aprofile (MULTILIB_REUSE): Add reuse rules for vfpv2 and
        neon-vfpv3.
* doc/invoke.texi (ARM: -mfpu): Document new options.  Note that 'vfp'
and 'neon' are aliases for specific implementations.

From-SVN: r242491

re PR fortran/78356 ([OOP] segfault allocating polymorphic variable with polymorphic component with allocatable component)

gcc/fortran/ChangeLog:

2016-11-16  Andre Vehreschild  <vehre@gcc.gnu.org>

PR fortran/78356
* class.c (gfc_is_class_scalar_expr): Prevent taking an array ref for
a component ref.
* trans-expr.c (gfc_trans_assignment_1): Ensure a reference to the
object to copy is generated, when assigning class objects.

gcc/testsuite/ChangeLog:

2016-11-16  Andre Vehreschild  <vehre@gcc.gnu.org>

PR fortran/78356
* gfortran.dg/class_allocate_23.f08: New test.

From-SVN: r242490

Fix vec_cmp comparison mode

vec_cmps assign the result of a vector comparison to a mask.
The optab was called with the destination having mode mask_mode
but with the source (the comparison) having mode VOIDmode,
which led to invalid rtl if the source operand was used directly.

gcc/
2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* optabs.c (vector_compare_rtx): Add a cmp_mode parameter
and use it in the final call to gen_rtx_fmt_ee.
(expand_vec_cond_expr): Update accordingly.
(expand_vec_cmp_expr): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242489

Use df_read_modify_subreg_p in cprop.c

local_cprop_find_used_regs punted on all multiword registers,
with the comment:

          /* Setting a subreg of a register larger than word_mode leaves
             the non-written words unchanged.  */

But this only applies if the outer mode is smaller than the
inner mode.  If they're the same size then writes to the subreg
are a normal full update.

This patch uses df_read_modify_subreg_p instead.  A later patch
adds more uses of the same routine, but this part had a (positive)
effect on code generation for the testsuite whereas the others
seemed to be simple clean-ups.

gcc/
2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* cprop.c (local_cprop_find_used_regs): Use df_read_modify_subreg_p.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242488

re PR middle-end/78333 (always-inline gnu-inline functions break -finstrument-functions)

2016-11-16  Richard Biener  <rguenther@suse.de>

PR middle-end/78333
* gimplify.c (gimplify_function_tree): Do not instrument
GNU extern inline functions.

* gcc.dg/pr78333.c: New testcase.

From-SVN: r242487

Fix PR sanitizer/78270 (part 2)

PR sanitizer/78270
* gimplify.c (gimplify_switch_expr): Always save previous
gimplify_ctxp->live_switch_vars.
PR sanitizer/78270
* gcc.dg/asan/pr78270.c: Update comment style.
* gcc.dg/asan/pr78270-2.c: New test.

From-SVN: r242485

[ARC] Fix LE tests for nps400 variant.

gcc/arc: New peephole2 and little endian arc test fixes

Resolve some test failures introduced for little endian arc as a result
of the recent arc/nps400 additions.

There's a new peephole2 optimisation to merge together two zero_extracts
in order that the movb instruction can be used.

One of the test cases is extended so that the test does something
meaningful in both big and little endian arc mode.

Other tests have their expected results updated to reflect improvements
in other areas of GCC.

gcc/ChangeLog:

 Andrew Burgess  <andrew.burgess@embecosm.com>

* config/arc/arc.md (movb peephole2): New peephole2 to merge two
zero_extract operations to allow a movb to occur.
* gcc.target/arc/movb-1.c: Update little endian arc results.
* gcc.target/arc/movb-2.c: Likewise.
* gcc.target/arc/movb-5.c: Likewise.
* gcc.target/arc/movh_cl-1.c: Extend test to cover little endian
arc.

From-SVN: r242484

Add revsison to libsanitizer/LOCAL_PATCHES

From-SVN: r242481

Fix PR78294 - thread sanitizer broken when using ld.gold

When one uses ld.gold to build gcc, the thread sanitizer doesn't work,
because gold is more conservative when applying TLS relaxations than
ld.bfd. In this case a missing initial-exec attribute on a declaration
causes gcc to assume the general dynamic model. With ld.bfd this gets
relaxed to initial exec when linking the shared library, so the missing
attribute doesn't matter. But ld.gold doesn't perform this optimization
and this leads to crashes on tsan instrumented binaries.

See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78294
and: https://sourceware.org/bugzilla/show_bug.cgi?id=20805

The fix is easy, just add the missing attribute.

  PR sanitizer/78294
  * tsan/tsan_rtl.cc: Add missing attribute.

From-SVN: r242480

LOCAL_PATCHES: New file.

libsanitizer/

* LOCAL_PATCHES: New file.

From-SVN: r242479

re PR sanitizer/78307 (missing symbols in libubsan without changing the soname)

PR sanitizer/78307
* ubsan/ubsan_handlers.cc (__ubsan_handle_cfi_bad_icall): New function.
( __ubsan_handle_cfi_bad_icall_abort): Likewise.
* ubsan/ubsan_handlers.h (struct CFIBadIcallData): New type.
* ubsan/ubsan_handlers_cxx.cc (__ubsan_handle_cfi_bad_type): New
function.
(__ubsan_handle_cfi_bad_type_abort): Likewise.
* ubsan/ubsan_handlers_cxx.h (struct CFIBadTypeData): New type.
(__ubsan_handle_cfi_bad_type): Export function.
(__ubsan_handle_cfi_bad_type_abort): Likewise.
* HOWTO_MERGE: Update documentation.

From-SVN: r242478

Optimise CONCAT handling in emit_group_load

The CONCAT handling in emit_group_load chooses between doing
an extraction from a single component or forcing the whole
thing to memory and extracting from there.  The condition for
the former (more efficient) option was:

  if ((bytepos == 0 && bytelen == slen0)
      || (bytepos != 0 && bytepos + bytelen <= slen))

On the one hand this seems dangerous, since the second line
allows bit ranges that start in the first component and leak
into the second.  On the other hand it seems strange to allow
references that start after the first byte of the second
component but not those that start after the first byte
of the first component.  This led to a pessimisation of
things like gcc.dg/builtins-54.c for hppa64-hp-hpux11.23.

This patch simply checks whether the reference is contained
within a single component.  It also makes sure that we do
an extraction on anything that doesn't span the whole
component (even if it's constant).

gcc/
2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* expr.c (emit_group_load_1): Tighten check for whether an
access involves only one operand of a CONCAT.  Use extract_bit_field
for constants if the bit range does span the whole operand.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242477

Fix handling of unknown sizes in rtx_addr_can_trap_p

If the size passed in to rtx_addr_can_trap_p was zero, the frame
handling would get the size from the mode instead.  However, this
too can be zero if the mode is BLKmode, i.e. if we have a BLKmode
memory reference with no MEM_SIZE (which should be rare these days).
This meant that the conditions for a 4-byte access at offset X were
stricter than those for an access of unknown size at offset X.

This patch checks whether the size is still zero, as the
SYMBOL_REF handling does.

gcc/
2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* rtlanal.c (rtx_addr_can_trap_p_1): Handle unknown sizes.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242476

Fix nb_iterations_estimate calculation in tree-vect-loop.c

vect_transform_loop has to reduce three iteration counts by
the vectorisation factor: nb_iterations_upper_bound,
nb_iterations_likely_upper_bound and nb_iterations_estimate.
All three are latch execution counts rather than loop body
execution counts.  The calculations were taking that into
account for the first two, but not for nb_iterations_estimate.

This patch updates the way the calculations are done to fix
this and to add a bit more commentary about what is going on.

gcc/
2016-11-15  Richard Sandiford  <richard.sandiford@arm.com>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

* tree-vect-loop.c (vect_transform_loop): Protect the updates of
all three iteration counts with an any_* test.  Use a single update
for each count.  Fix the calculation of nb_iterations_estimate.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r242475