yosys.git
4 years agokernel: guard include of signal.h more precisely.
whitequark [Sat, 13 Jun 2020 22:37:04 +0000 (22:37 +0000)]
kernel: guard include of signal.h more precisely.

Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)

4 years agoMerge pull request #2151 from whitequark/cxxrtl-fix-rzext
whitequark [Sat, 13 Jun 2020 22:18:35 +0000 (22:18 +0000)]
Merge pull request #2151 from whitequark/cxxrtl-fix-rzext

cxxrtl: fix rzext()

4 years agoMerge pull request #2145 from whitequark/cxxrtl-splitnets
whitequark [Sat, 13 Jun 2020 04:23:22 +0000 (04:23 +0000)]
Merge pull request #2145 from whitequark/cxxrtl-splitnets

cxxrtl: handle multipart signals

4 years agoMerge pull request #2152 from whitequark/cxxrtl-always-inline
whitequark [Sat, 13 Jun 2020 04:17:49 +0000 (04:17 +0000)]
Merge pull request #2152 from whitequark/cxxrtl-always-inline

cxxrtl: always inline internal cells and slice/concat operations

4 years agocxxrtl: always inline internal cells and slice/concat operations.
whitequark [Sat, 13 Jun 2020 01:50:53 +0000 (01:50 +0000)]
cxxrtl: always inline internal cells and slice/concat operations.

This can result in massive reduction in runtime, up to 50% depending
on workload. Currently people are using `-mllvm -inline-threshold=`
as a workaround (with clang++), but this solution is more portable.

4 years agocxxrtl: fix rzext().
whitequark [Sat, 13 Jun 2020 00:49:44 +0000 (00:49 +0000)]
cxxrtl: fix rzext().

This was a correctness issue, but one of the consequences is that it
resulted in jumps in generated machine code where there should have
been none. As a side effect of fixing the bug, Minerva SoC became 10%
faster.

4 years agoMerge pull request #2150 from whitequark/cxxrtl-elide-pmux
whitequark [Fri, 12 Jun 2020 08:50:57 +0000 (08:50 +0000)]
Merge pull request #2150 from whitequark/cxxrtl-elide-pmux

cxxrtl: elide $pmux cells

4 years agocxxrtl: elide $pmux cells.
whitequark [Fri, 12 Jun 2020 02:40:30 +0000 (02:40 +0000)]
cxxrtl: elide $pmux cells.

On Minerva, this improves runtime by around 10%, mostly by ensuring
that the logic driving FFs is packed into edge conditionals.

4 years agoMerge pull request #2149 from whitequark/cxxrtl-unbuffer-outputs
whitequark [Fri, 12 Jun 2020 01:59:35 +0000 (01:59 +0000)]
Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputs

cxxrtl: unbuffer output wires of toplevel module

4 years agocxxrtl: annotate port direction as comments.
whitequark [Fri, 12 Jun 2020 00:35:18 +0000 (00:35 +0000)]
cxxrtl: annotate port direction as comments.

4 years agocxxrtl: unbuffer output wires of toplevel module.
whitequark [Fri, 12 Jun 2020 00:05:05 +0000 (00:05 +0000)]
cxxrtl: unbuffer output wires of toplevel module.

Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.

This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.

4 years agocxxrtl: simplify unbuffering of input wires.
whitequark [Thu, 11 Jun 2020 22:21:30 +0000 (22:21 +0000)]
cxxrtl: simplify unbuffering of input wires.

This also fixes an edge case with (*keep*) input ports.

4 years agocxxrtl: handle multipart signals.
whitequark [Thu, 11 Jun 2020 13:31:16 +0000 (13:31 +0000)]
cxxrtl: handle multipart signals.

This avoids losing design visibility when using the `splitnets` pass.

4 years agointel_alm: fix DFFE matching
Dan Ravensloft [Thu, 11 Jun 2020 17:06:39 +0000 (18:06 +0100)]
intel_alm: fix DFFE matching

4 years agocxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.
whitequark [Thu, 11 Jun 2020 12:42:37 +0000 (12:42 +0000)]
cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.

4 years agoMerge pull request #2141 from whitequark/cxxrtl-cxx11
whitequark [Wed, 10 Jun 2020 17:10:15 +0000 (17:10 +0000)]
Merge pull request #2141 from whitequark/cxxrtl-cxx11

cxxrtl: various compiler compatibility fixes

4 years agoMerge pull request #2140 from whitequark/cxxrtl-aliases
whitequark [Wed, 10 Jun 2020 16:09:27 +0000 (16:09 +0000)]
Merge pull request #2140 from whitequark/cxxrtl-aliases

cxxrtl: disambiguate values/wires and their aliases in debug info

4 years agocxxrtl: restore C++11 compatibility.
whitequark [Wed, 10 Jun 2020 15:49:28 +0000 (15:49 +0000)]
cxxrtl: restore C++11 compatibility.

This is necessary to be able to build CXXRTL models via yosys-config.

4 years agocxxrtl: fix a few gcc warnings.
whitequark [Wed, 10 Jun 2020 15:57:01 +0000 (15:57 +0000)]
cxxrtl: fix a few gcc warnings.

4 years agoFix formatting. NFC.
whitequark [Wed, 10 Jun 2020 15:48:40 +0000 (15:48 +0000)]
Fix formatting. NFC.

4 years agocxxrtl: disambiguate values/wires and their aliases in debug info.
whitequark [Wed, 10 Jun 2020 14:39:45 +0000 (14:39 +0000)]
cxxrtl: disambiguate values/wires and their aliases in debug info.

With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).

4 years agoMerge pull request #2134 from whitequark/cxxrtl-opt-debug
whitequark [Wed, 10 Jun 2020 11:51:04 +0000 (11:51 +0000)]
Merge pull request #2134 from whitequark/cxxrtl-opt-debug

cxxrtl: introduce -Og optimization level

4 years agoMerge pull request #2131 from YosysHQ/claire/preserveffs
clairexen [Wed, 10 Jun 2020 10:44:23 +0000 (12:44 +0200)]
Merge pull request #2131 from YosysHQ/claire/preserveffs

Do not optimize away FFs in "prep" and Verific front-end

4 years agoMerge pull request #2139 from YosysHQ/verific_missing_memory
clairexen [Wed, 10 Jun 2020 10:42:43 +0000 (12:42 +0200)]
Merge pull request #2139 from YosysHQ/verific_missing_memory

verific - detect missing memory to prevent crash.

4 years agoverific - detect missing memory to prevent crash.
Miodrag Milanovic [Wed, 10 Jun 2020 09:27:44 +0000 (11:27 +0200)]
verific - detect missing memory to prevent crash.

4 years agocxxrtl: allow unbuffering without localizing.
whitequark [Tue, 9 Jun 2020 21:50:09 +0000 (21:50 +0000)]
cxxrtl: allow unbuffering without localizing.

Although logically two separate steps, these were treated as one for
historic reasons. Splitting the two makes it possible to have designs
that are only 2× slower than fastest possible (and are without extra
delta cycles) that allow probing all public wires.

4 years agocxxrtl: order -On levels as localize, elide instead of the reverse.
whitequark [Tue, 9 Jun 2020 20:55:40 +0000 (20:55 +0000)]
cxxrtl: order -On levels as localize, elide instead of the reverse.

Historically, elision was implemented before localization, so levels
with elision are lower than corresponding levels with localization.
This is unfortunate for two reasons:
  1. Elision is a logical subset of localization, since it equals to
     not giving a name to a temporary.
  2. "Localize" currently actually means "unbuffer and localize",
     and it would be useful to split those steps (at least for
     public wires) for improved design visibility.

4 years agoFix tests/opt/opt_rmdff
Claire Wolf [Tue, 9 Jun 2020 17:14:36 +0000 (19:14 +0200)]
Fix tests/opt/opt_rmdff

This only passed before because "prep" was also running opt_rmdff

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoDrive-by modernization in sat.cc
Claire Wolf [Tue, 9 Jun 2020 19:49:43 +0000 (21:49 +0200)]
Drive-by modernization in sat.cc

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agocxxrtl: factor out -noproc/-noflatten from -O.
whitequark [Tue, 9 Jun 2020 20:18:07 +0000 (20:18 +0000)]
cxxrtl: factor out -noproc/-noflatten from -O.

Although these options can be thought of as optimizations, they are
essentially orthogonal to the core of -O, which is managing signal
buffering and scope. Going from -O4 to -O2 means going from limited
to complete design visibility, yet in both cases proc and flatten
are desirable.

4 years agoMerge pull request #2112 from YosysHQ/claire/fix2040
clairexen [Tue, 9 Jun 2020 16:27:59 +0000 (18:27 +0200)]
Merge pull request #2112 from YosysHQ/claire/fix2040

Add latch detection for use_case_method in part-select write

4 years agoDo not optimize away FFs in "prep" and Verific fron-end
Claire Wolf [Tue, 9 Jun 2020 13:54:14 +0000 (15:54 +0200)]
Do not optimize away FFs in "prep" and Verific fron-end

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #2128 from whitequark/flatten-processes
whitequark [Tue, 9 Jun 2020 12:41:02 +0000 (12:41 +0000)]
Merge pull request #2128 from whitequark/flatten-processes

flatten: accept processes

4 years agoMerge pull request #2130 from whitequark/cxxrtl-fix-split_by
whitequark [Tue, 9 Jun 2020 11:59:17 +0000 (11:59 +0000)]
Merge pull request #2130 from whitequark/cxxrtl-fix-split_by

cxxrtl: fix two buggy split_by functions

4 years agocxxrtl: fix two buggy split_by functions.
whitequark [Tue, 9 Jun 2020 11:05:35 +0000 (11:05 +0000)]
cxxrtl: fix two buggy split_by functions.

4 years agoflatten: accept processes.
whitequark [Tue, 9 Jun 2020 09:56:23 +0000 (09:56 +0000)]
flatten: accept processes.

4 years agoRTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.
whitequark [Tue, 9 Jun 2020 09:55:48 +0000 (09:55 +0000)]
RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.

4 years agoMerge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops
whitequark [Tue, 9 Jun 2020 09:54:09 +0000 (09:54 +0000)]
Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops

cxxrtl: ignore cell input signedness when it is irrelevant

4 years agoMerge pull request #2125 from whitequark/cxxrtl-fix-namespace
whitequark [Tue, 9 Jun 2020 07:52:27 +0000 (07:52 +0000)]
Merge pull request #2125 from whitequark/cxxrtl-fix-namespace

cxxrtl: add missing namespace

4 years agocxxrtl: ignore cell input signedness when it is irrelevant.
whitequark [Tue, 9 Jun 2020 07:26:13 +0000 (07:26 +0000)]
cxxrtl: ignore cell input signedness when it is irrelevant.

Before this commit, Verilog expressions like `x && 1` would result in
references to `logic_and_us` in generated CXXRTL code, which would
not compile. After this commit, since cells like that actually behave
the same regardless of signedness attributes, the signedness is
ignored, which also reduces the template instantiation pressure.

4 years agocxxrtl: add missing namespace.
whitequark [Tue, 9 Jun 2020 06:26:17 +0000 (06:26 +0000)]
cxxrtl: add missing namespace.

Fixes #2124.

4 years agoMerge pull request #2107 from whitequark/flatten-hdlname
whitequark [Tue, 9 Jun 2020 06:26:02 +0000 (06:26 +0000)]
Merge pull request #2107 from whitequark/flatten-hdlname

flatten: preserve original object names

4 years agocxxrtl: fix format of hdlnames.
whitequark [Mon, 8 Jun 2020 19:50:09 +0000 (19:50 +0000)]
cxxrtl: fix format of hdlnames.

The CXXRTL code that handled the `hdlname` attribute implemented
outdated semantics.

4 years agoflatten: preserve original object names via hdlname attribute.
whitequark [Thu, 4 Jun 2020 10:46:54 +0000 (10:46 +0000)]
flatten: preserve original object names via hdlname attribute.

4 years agoflatten: only prepend $flatten once per wire.
whitequark [Mon, 8 Jun 2020 19:18:11 +0000 (19:18 +0000)]
flatten: only prepend $flatten once per wire.

4 years agoRTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.
whitequark [Mon, 8 Jun 2020 19:02:48 +0000 (19:02 +0000)]
RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.

The only difference in behavior is that this removes the attribute
when the pool becomes empty.

4 years agoMerge pull request #2120 from whitequark/flatten-hygiene
whitequark [Mon, 8 Jun 2020 20:19:18 +0000 (20:19 +0000)]
Merge pull request #2120 from whitequark/flatten-hygiene

flatten: make hygienic

4 years agoflatten: make hygienic.
whitequark [Thu, 4 Jun 2020 10:13:48 +0000 (10:13 +0000)]
flatten: make hygienic.

Before this commit, `flatten` matched the template objects with
the newly created objects solely by their name. Because of this,
it could be confused by code such as:

    module bar();
      $dff a();
    endmodule

    module foo();
      bar b();
      $dff \b.a ();
    endmodule

After this commit, `flatten` avoids every possible case of name
collision.

Fixes #2106.

4 years agoMerge pull request #2121 from whitequark/cxxrtl-debug-aliases
whitequark [Mon, 8 Jun 2020 18:24:32 +0000 (18:24 +0000)]
Merge pull request #2121 from whitequark/cxxrtl-debug-aliases

cxxrtl: improve design visibility

4 years agocxxrtl: don't check immutable values for changes in VCD writer.
whitequark [Mon, 8 Jun 2020 17:38:11 +0000 (17:38 +0000)]
cxxrtl: don't check immutable values for changes in VCD writer.

This commit changes the VCD writer such that for all signals that
have `debug_item.type == VALUE && debug_item.next == nullptr`, it
would only sample the value once.

Commit f2d7a187 added more debug information by including constant
wires, and decreased the performance of VCD writer proportionally
because the constant wires were still repeatedly sampled; this commit
eliminates the performance hit.

4 years agocxxrtl: emit debug information for constant wires.
whitequark [Mon, 8 Jun 2020 17:29:08 +0000 (17:29 +0000)]
cxxrtl: emit debug information for constant wires.

Constant wires can represent a significant chunk of the design in
generic designs or after optimization. Emitting them in VCD files
significantly improves usability because gtkwave removes all traces
that are not present in the VCD file after reload, and iterative
development suffers if switching a varying signal to a constant
disrupts the workflow.

4 years agocxxrtl: track aliases in VCD writer.
whitequark [Mon, 8 Jun 2020 16:36:26 +0000 (16:36 +0000)]
cxxrtl: track aliases in VCD writer.

This commit changes the VCD writer such that for all signals that
share `debug_item.curr`, it would only emit a single VCD identifier,
and sample the value once.

Commit 9b39c6f7 added redundancy to debug information by including
alias wires, and increased the size of VCD files proportionally; this
commit eliminates the redundancy from VCD files so that their size
is the same as before.

4 years agocxxrtl: emit debug information for alias wires.
whitequark [Mon, 8 Jun 2020 16:22:30 +0000 (16:22 +0000)]
cxxrtl: emit debug information for alias wires.

Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.

4 years agoMerge pull request #2085 from rswarbrick/select
clairexen [Mon, 8 Jun 2020 13:55:52 +0000 (15:55 +0200)]
Merge pull request #2085 from rswarbrick/select

Silence warning in select.cc and pass some more args by ref

4 years agoMerge pull request #2089 from rswarbrick/modports
clairexen [Mon, 8 Jun 2020 13:48:11 +0000 (15:48 +0200)]
Merge pull request #2089 from rswarbrick/modports

Simplify a modport check in hierarchy.cc

4 years agoMerge pull request #2105 from whitequark/split-flatten-off-techmap
clairexen [Mon, 8 Jun 2020 13:27:15 +0000 (15:27 +0200)]
Merge pull request #2105 from whitequark/split-flatten-off-techmap

Split `flatten` from `techmap` and simplify it

4 years agoMerge pull request #2117 from PeterCrozier/struct_array
clairexen [Mon, 8 Jun 2020 13:22:09 +0000 (15:22 +0200)]
Merge pull request #2117 from PeterCrozier/struct_array

Support packed arrays in struct/union.

4 years agoMerge pull request #2119 from YosysHQ/mwk/fix-fsm-idstring
clairexen [Mon, 8 Jun 2020 13:18:32 +0000 (15:18 +0200)]
Merge pull request #2119 from YosysHQ/mwk/fix-fsm-idstring

fsm_extract: avoid calling log_signal to determine wire name

4 years agocxxrtl: add missing installs of include files.
whitequark [Mon, 8 Jun 2020 12:55:11 +0000 (12:55 +0000)]
cxxrtl: add missing installs of include files.

4 years agocxxrtl: fix typo in comment. NFC.
whitequark [Mon, 8 Jun 2020 04:08:09 +0000 (04:08 +0000)]
cxxrtl: fix typo in comment. NFC.

4 years agocxxrtl: minor debug-related improvements.
whitequark [Mon, 8 Jun 2020 03:21:08 +0000 (03:21 +0000)]
cxxrtl: minor debug-related improvements.

4 years agofsm_extract: avoid calling log_signal to determine wire name
Marcelina Kościelnicka [Mon, 8 Jun 2020 01:48:09 +0000 (03:48 +0200)]
fsm_extract: avoid calling log_signal to determine wire name

log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.

Fixes #2118

4 years agoMerge pull request #2116 from whitequark/cxxrtl-vcd
whitequark [Sun, 7 Jun 2020 20:32:00 +0000 (20:32 +0000)]
Merge pull request #2116 from whitequark/cxxrtl-vcd

cxxrtl: add a VCD writer using debug information

4 years agoSupport packed arrays in struct/union.
Peter Crozier [Sun, 7 Jun 2020 17:28:45 +0000 (18:28 +0100)]
Support packed arrays in struct/union.

4 years agocxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.
whitequark [Sun, 7 Jun 2020 03:48:40 +0000 (03:48 +0000)]
cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.

To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.

4 years agocxxrtl: add a C API for writing VCD dumps.
whitequark [Sun, 7 Jun 2020 03:45:53 +0000 (03:45 +0000)]
cxxrtl: add a C API for writing VCD dumps.

This C API is fully featured.

4 years agocxxrtl: only write VCD values that were actually updated.
whitequark [Sat, 6 Jun 2020 21:55:53 +0000 (21:55 +0000)]
cxxrtl: only write VCD values that were actually updated.

On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.

4 years agocxxrtl: add a VCD writer using debug information.
whitequark [Sat, 6 Jun 2020 20:37:29 +0000 (20:37 +0000)]
cxxrtl: add a VCD writer using debug information.

4 years agoMerge pull request #2115 from whitequark/cxxrtl-introspection
whitequark [Sat, 6 Jun 2020 22:31:52 +0000 (22:31 +0000)]
Merge pull request #2115 from whitequark/cxxrtl-introspection

cxxrtl: add debug information to the C++ API, and add introspection via a new C API

4 years agocxxrtl: add a C API for driving and introspecting designs.
whitequark [Fri, 5 Jun 2020 13:52:30 +0000 (13:52 +0000)]
cxxrtl: add a C API for driving and introspecting designs.

Compared to the C++ API, the C API currently has two limitations:
  1. Memories cannot be updated in a race-free way.
  2. Black boxes cannot be implemented in C.

4 years agocxxrtl: generate debug information for non-localized public wires.
whitequark [Wed, 27 May 2020 00:21:15 +0000 (00:21 +0000)]
cxxrtl: generate debug information for non-localized public wires.

Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.

The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.

4 years agoMerge pull request #2110 from BracketMaster/master
whitequark [Sat, 6 Jun 2020 12:23:06 +0000 (12:23 +0000)]
Merge pull request #2110 from BracketMaster/master

MacOS has even stricter stack limits in catalina.

4 years agoMerge pull request #2113 from whitequark/cxxrtl-fix-sshr
whitequark [Fri, 5 Jun 2020 10:24:25 +0000 (10:24 +0000)]
Merge pull request #2113 from whitequark/cxxrtl-fix-sshr

cxxrtl: fix implementation of $sshr cell

4 years agoMerge pull request #2109 from nakengelhardt/btor_internal_names
N. Engelhardt [Fri, 5 Jun 2020 09:36:08 +0000 (11:36 +0200)]
Merge pull request #2109 from nakengelhardt/btor_internal_names

btor backend: make not printing internal names default

4 years agocxxrtl: fix implementation of $sshr cell.
whitequark [Fri, 5 Jun 2020 01:31:53 +0000 (01:31 +0000)]
cxxrtl: fix implementation of $sshr cell.

Fixes #2111.

4 years agoAdd latch detection for use_case_method in part-select write, fixes #2040
Claire Wolf [Thu, 4 Jun 2020 21:10:03 +0000 (23:10 +0200)]
Add latch detection for use_case_method in part-select write, fixes #2040

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agomore reasonable numbers for memory
Yehowshua Immanuel [Thu, 4 Jun 2020 21:00:04 +0000 (17:00 -0400)]
more reasonable numbers for memory

4 years agoAdd missing .gitignore file
Claire Wolf [Thu, 4 Jun 2020 20:25:47 +0000 (22:25 +0200)]
Add missing .gitignore file

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMacOS has even stricter stack limits in catalina.
Yehowshua Immanuel [Thu, 4 Jun 2020 18:01:56 +0000 (14:01 -0400)]
MacOS has even stricter stack limits in catalina.

Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.

4 years agoMerge pull request #2041 from PeterCrozier/struct
clairexen [Thu, 4 Jun 2020 16:26:07 +0000 (18:26 +0200)]
Merge pull request #2041 from PeterCrozier/struct

Implementation of  SV structs.

4 years agoMerge pull request #2099 from Xiretza/manual-include-path
clairexen [Thu, 4 Jun 2020 16:23:33 +0000 (18:23 +0200)]
Merge pull request #2099 from Xiretza/manual-include-path

Use in-tree include directory in manual build

4 years agoAdd codeowners file (#2098)
N. Engelhardt [Thu, 4 Jun 2020 16:20:08 +0000 (18:20 +0200)]
Add codeowners file (#2098)

4 years agoMerge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
Eddie Hung [Thu, 4 Jun 2020 15:15:25 +0000 (08:15 -0700)]
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve

abc9: -dff improvements

4 years agobtor backend: make not printing internal names default
N. Engelhardt [Thu, 4 Jun 2020 14:24:16 +0000 (16:24 +0200)]
btor backend: make not printing internal names default

4 years agoAdd printf format attributes to btorf/infof helper functions
Claire Wolf [Thu, 4 Jun 2020 13:53:28 +0000 (15:53 +0200)]
Add printf format attributes to btorf/infof helper functions

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #2108 from nakengelhardt/btor_internal_names
clairexen [Thu, 4 Jun 2020 13:48:40 +0000 (15:48 +0200)]
Merge pull request #2108 from nakengelhardt/btor_internal_names

btor backend: add option to not include internal names

4 years agoflatten: clean up log messages.
whitequark [Wed, 3 Jun 2020 20:06:04 +0000 (20:06 +0000)]
flatten: clean up log messages.

4 years agoflatten: topologically sort modules.
whitequark [Wed, 3 Jun 2020 20:04:51 +0000 (20:04 +0000)]
flatten: topologically sort modules.

4 years agobtor backend: add option to not include internal names
N. Engelhardt [Thu, 4 Jun 2020 12:00:52 +0000 (14:00 +0200)]
btor backend: add option to not include internal names

4 years agoMerge pull request #2006 from jersey99/signed-in-rtlil-wire
whitequark [Thu, 4 Jun 2020 11:23:06 +0000 (11:23 +0000)]
Merge pull request #2006 from jersey99/signed-in-rtlil-wire

Preserve 'signed'-ness of a verilog wire through RTLIL

4 years agoMerge pull request #2070 from hackfin/master
N. Engelhardt [Thu, 4 Jun 2020 09:17:08 +0000 (11:17 +0200)]
Merge pull request #2070 from hackfin/master

Pyosys API: idict type handling

4 years agoMerge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes no_loop
Eddie Hung [Thu, 4 Jun 2020 00:35:46 +0000 (17:35 -0700)]
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes

abc9: fixes around handling combinatorial loops

4 years agoflatten: simplify.
whitequark [Wed, 3 Jun 2020 17:41:45 +0000 (17:41 +0000)]
flatten: simplify.

`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.

4 years agoflatten: simplify. NFC.
whitequark [Wed, 3 Jun 2020 16:25:46 +0000 (16:25 +0000)]
flatten: simplify. NFC.

Remove redundant sigmaps.

4 years agoflatten: simplify.
whitequark [Wed, 3 Jun 2020 16:00:40 +0000 (16:00 +0000)]
flatten: simplify.

Flattening does not benefit from topologically sorting cells within
a module when processing them.

4 years agoflatten: simplify. NFC.
whitequark [Wed, 3 Jun 2020 02:28:39 +0000 (02:28 +0000)]
flatten: simplify. NFC.

Flatten is non-recursive and doesn't need to keep track of handled
cells.

4 years agoflatten: simplify. NFC.
whitequark [Wed, 3 Jun 2020 02:11:04 +0000 (02:11 +0000)]
flatten: simplify. NFC.

Flattening always does "non-recursive" mapping.

4 years agoflatten: simplify. NFC.
whitequark [Wed, 3 Jun 2020 02:09:09 +0000 (02:09 +0000)]
flatten: simplify. NFC.

The `celltypeMap` always maps `x` to `{x}`.

4 years agoflatten: simplify. NFC.
whitequark [Wed, 3 Jun 2020 01:19:55 +0000 (01:19 +0000)]
flatten: simplify. NFC.

The `design` and `map` designs are always the same when flattening.

4 years agoRTLIL: factor out RTLIL::Module::addMemory. NFC.
whitequark [Wed, 3 Jun 2020 14:35:27 +0000 (14:35 +0000)]
RTLIL: factor out RTLIL::Module::addMemory. NFC.