Jonathan Marek [Fri, 10 Apr 2020 12:37:48 +0000 (08:37 -0400)]
nir: convert_ycbcr: preserve alpha channel
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4528>
Jonathan Marek [Fri, 10 Apr 2020 12:34:53 +0000 (08:34 -0400)]
nir: add common convert_ycbcr for vulkan csc
Copied from anv, replaced state with passing model/range directly.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4528>
Dave Airlie [Mon, 20 Apr 2020 01:23:45 +0000 (11:23 +1000)]
nir/linking: fix issue with two compact variables in a row. (v2)
If we have a clip dist float[1] compact followed by a tess factor
float[2] we don't want to overlap them, but the partial check
only happens for non-compact vars.
This fixes some issues seen with my sw vulkan layer with
dEQP-VK.clipping.user_defined.clip_distance*
v2: v1 failed with clip/cull mixtures, since in that
case the cull has a location_frac to follow after the clip
so only reset if we get a location_frac of 0 in a subsequent
clip var
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4635>
Eric Engestrom [Wed, 11 Mar 2020 13:39:48 +0000 (14:39 +0100)]
pick-ui: auto-scroll the feedback window
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4650>
Dylan Baker [Wed, 16 Oct 2019 18:32:49 +0000 (11:32 -0700)]
bin/pick-ui: Add a new maintainer script for picking patches
In the long term the goal of this script is to nearly completely
automate the process of picking stable nominations, in a well tested
way.
In the short term the goal is to provide a better, faster UI to interact
with stable nominations.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3608>
Dylan Baker [Thu, 5 Mar 2020 22:04:04 +0000 (14:04 -0800)]
bin/gen_release_notes.py: Fix version detection for .0 release
The previous version is being calculated incorrectly, resulting in
20.0.0 deciding it's version is 19.3.x+1. This fixes that.
Fixes: 3226b12a09bbcbd25526fd6da6257057d26ddb31
("release: Add an update_release_calendar.py script")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4070>
Rafael Antognolli [Fri, 18 Jan 2019 23:05:55 +0000 (15:05 -0800)]
anv: Add support for new MMAP_OFFSET ioctl.
v2: Update getparam check (Ken).
[jordan.l.justen@intel.com: use 0 offset for MMAP_OFFSET]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
Rafael Antognolli [Wed, 20 Feb 2019 23:26:43 +0000 (15:26 -0800)]
anv: Add anv_device parameter to anv_gem_munmap.
Also update all of its callers.
On the next commit, the device will be used by anv_gem_munmap to choose
whether we need to call the valgrind code or not, depending on which
type of mmap we are using.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
Rafael Antognolli [Wed, 13 Feb 2019 19:51:50 +0000 (11:51 -0800)]
iris/bufmgr: Add support for MMAP_OFFSET ioctl.
Use the new DRM_IOCTL_I915_GEM_MMAP_OFFSET ioctl when available.
[jordan.l.justen@intel.com: iris port]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
v2: Update getparam check (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
Rafael Antognolli [Fri, 14 Dec 2018 22:02:04 +0000 (14:02 -0800)]
i965/bufmgr: Add support for MMAP_OFFSET ioctl.
Use the new DRM_IOCTL_I915_GEM_MMAP_OFFSET ioctl when available.
v2: update getparam check (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
Rafael Antognolli [Wed, 13 Feb 2019 19:32:17 +0000 (11:32 -0800)]
iris/bufmgr: Factor out GEM_MMAP ioctl from mmap_cpu and mmap_wc.
We want to add a new ioctl for mmap'ing buffers, so let's avoid
duplicating that code on both functions by extracting it from them
first.
[jordan.l.justen@intel.com: iris port]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
v2: Rename helper function names (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
Rafael Antognolli [Fri, 14 Dec 2018 21:20:45 +0000 (13:20 -0800)]
i965/bufmgr: Factor out GEM_MMAP ioctl from mmap_cpu and mmap_wc.
We want to add a new ioctl for mmap'ing buffers, so let's avoid
duplicating that code on both functions by extracting it from them
first.
v2: Update helper function names (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
Rafael Antognolli [Mon, 13 Apr 2020 17:26:14 +0000 (10:26 -0700)]
drm-uapi: Update headers from Linux 5.7-rc1.
commit
8f3d9f354286745c751374f5f1fcafee6b3f3136
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Apr 12 12:35:55 2020 -0700
Linux 5.7-rc1
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
Caio Marcelo de Oliveira Filho [Fri, 17 Apr 2020 21:44:12 +0000 (14:44 -0700)]
spirv: Fix propagation of OpVariable access flags
After the decorations of a variable are evaluated, propagate the
access flag to the associated vtn_pointer. This was done when
creating the pointer but at that point there was no access flags for
the variable.
Inline the pointer creation to make this point clearer, in isolation
the helper made the impression that the value was being propagated.
Issue found by Ken.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4620>
Caio Marcelo de Oliveira Filho [Fri, 3 Jan 2020 18:05:39 +0000 (10:05 -0800)]
intel/fs,vec4: Properly account SENDs in IVB memory fence
Change brw_memory_fence to return the number of messages emitted, and
use that to update the send_count statistic in code generation.
This will fix the book-keeping for IVB since the memory fences will
result in two SEND messages.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4646>
Daniel Schürmann [Mon, 20 Apr 2020 12:02:26 +0000 (13:02 +0100)]
aco: move src1 to vgpr instead of using VOP3 for VOP2 instructions during isel
Is simpler and helps a couple of shaders.
Totals from affected shaders: (Vega)
Code Size:
16341296 ->
16335460 (-0.04 %) bytes
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4642>
Daniel Schürmann [Mon, 20 Apr 2020 11:59:21 +0000 (12:59 +0100)]
aco: fix 64bit fsub
Fixes: 425558bfd595ed3a7a049ad0f47a46b8b3c4691e ('aco: use v_subrev_f32 for fsub with an sgpr operand in src1')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4642>
Tomeu Vizoso [Wed, 1 Apr 2020 07:17:25 +0000 (09:17 +0200)]
gitlab-ci: Test virgl driver
Add virglrenderer to the container and use the vtest transport to test
the Gallium driver. On the "host", llvmpipe is used.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4433>
Erik Faye-Lund [Wed, 15 Apr 2020 18:35:46 +0000 (20:35 +0200)]
meson: do not disable incremental linking for debug-builds
Meson specifies /EDITANDCONTINUE for MSVC projects when using the debug
build-type. This collides with our across-the-board disabling of
incremental linking.
It's clear that we don't want to do incremental linking for
release-builds; it increase the code-size, and adds some needless jumps
to be able to patch in new code. But for debug-builds this seems like a
good thing; we can now debug and on-the-fly recompile changes if we want
to.
This flag seems to have been simply forwarded from the SCons build
system, where it makes a bit more sense; SCons doesn't really integrate
with visual studio, so you can't properly debug with it. But Meson does,
so let's keep some bells-and-whistles here.
So let's avoid disabling incremental linking for debug-builds. For other
builds we still want to do this, because Meson only disables it
automatically for minsize-builds.
This avoids a boat-loads of warnings on the form:
warning LNK4075: ignoring '/EDITANDCONTINUE' due to '/INCREMENTAL:NO' specification
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4572>
Erik Faye-Lund [Wed, 15 Apr 2020 20:36:04 +0000 (22:36 +0200)]
gtest: Update to 1.10.0
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4576>
Samuel Pitoiset [Wed, 15 Apr 2020 14:55:31 +0000 (16:55 +0200)]
nir/opt_algebraic: lower 64-bit fmin3/fmax3/fmed3
This unconditionally lowers 64-bit fmin3/fmax3/fmed3 because
AMD hardware doesn't have native instructions, and no drivers
except RADV uses these instructions.
Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.*.f64.*
with ACO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4570>
Samuel Pitoiset [Wed, 15 Apr 2020 14:15:11 +0000 (16:15 +0200)]
nir/lower_int64: lower imin3/imax3/umin3/umax3/imed3/umed3
Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.*.i64.*
with ACO because this backend compiler expects most of the 64-bit
operations to be lowered.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4570>
Pierre-Eric Pelloux-Prayer [Tue, 14 Apr 2020 16:04:35 +0000 (18:04 +0200)]
radeonsi: skip vs output optimizations for some outputs
If PT_SPRITE_TEX is enabled, PS inputs are overriden at runtime so
we can't apply the vs output optim.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2747
Fixes: 3ec9975555d ("radeonsi: eliminate trivial constant VS outputs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4559>
Timothy Arceri [Fri, 22 Mar 2019 02:01:03 +0000 (13:01 +1100)]
nir/gcm: dont move movs unless we can replace them later with their src
This helps us avoid moving the movs outside if branches when there
src can't be scalarized.
For example it avoids:
vec4 32 ssa_7 = tex ssa_6 (coord), 0 (texture), 0 (sampler),
if ... {
r0 = imov ssa_7.z
r1 = imov ssa_7.y
r2 = imov ssa_7.x
r3 = imov ssa_7.w
...
} else {
...
if ... {
r0 = imov ssa_7.x
r1 = imov ssa_7.w
...
else {
r0 = imov ssa_7.z
r1 = imov ssa_7.y
...
}
r2 = imov ssa_7.x
r3 = imov ssa_7.w
}
...
vec4 32 ssa_36 = vec4 r0, r1, r2, r3
Becoming something like:
vec4 32 ssa_7 = tex ssa_6 (coord), 0 (texture), 0 (sampler),
r0 = imov ssa_7.z
r1 = imov ssa_7.y
r2 = imov ssa_7.x
r3 = imov ssa_7.w
if ... {
...
} else {
if ... {
r0 = imov r2
r1 = imov r3
...
else {
...
}
...
}
While this is has a smaller instruction count it requires more work
for the same result. With more complex examples we can also end up
shuffling the registers around in a way that requires more registers
to use as temps so that we don't overwrite our original values along
the way.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Timothy Arceri [Mon, 25 Mar 2019 08:38:54 +0000 (19:38 +1100)]
nir/gcm: be more conservative about moving instructions from loops
Here we only pull instructions further up control flow if they are
constant or texture instructions. See the code comment for more
information.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Timothy Arceri [Fri, 22 Mar 2019 04:32:22 +0000 (15:32 +1100)]
nir/gcm: allow derivative dependent intrinisics to be moved earlier
We can't move them later as we could move them into non-uniform
control flow, but moving them earlier should be fine.
This helps avoid a bunch of spilling in unigine shaders due to
moving the tex instructions sources earlier (outside if branches)
but not the instruction itself.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Jason Ekstrand [Wed, 18 Jan 2017 02:38:41 +0000 (18:38 -0800)]
nir/gcm: Prefer the instruction's original block
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Jason Ekstrand [Wed, 18 Jan 2017 02:38:40 +0000 (18:38 -0800)]
nir/gcm: Delete dead instructions
Classically, global code motion is also a dead code pass. However, in
the initial implementation, the decision was made to place every
instruction and let conventional DCE clean up the dead ones. Because
any uses of a dead instruction are unreachable, we have no late block
and the dead instructions are always scheduled early. The problem is
that, because we place the dead instruction early, it pushes the
placement of any dependencies of the dead instruction earlier than they
may need to be placed. In order prevent dead instructions from
affecting the placement of live ones, we need to delete them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Jason Ekstrand [Wed, 18 Jan 2017 02:38:39 +0000 (18:38 -0800)]
nir/gcm: Add a real concept of "progress"
Now that the GCM pass is more conservative and only moves instructions
to different blocks when it's advantageous to do so, we can have a
proper notion of what it means to make progress.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Jason Ekstrand [Wed, 18 Jan 2017 02:38:38 +0000 (18:38 -0800)]
nir/gcm: Move block choosing into a helper function
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Jason Ekstrand [Wed, 18 Jan 2017 02:38:37 +0000 (18:38 -0800)]
nir/gcm: Use an array for storing the early block
We are about to adjust our instruction block assignment algorithm and we
will want to know the current block that the instruction lives in. In
order to allow for this, we can't overwrite nir_instr::block in the
early scheduling pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Jason Ekstrand [Wed, 18 Jan 2017 02:38:36 +0000 (18:38 -0800)]
nir/gcm: Loop over blocks in pin_instructions
Now that we have the new block iterators, we can simplify things a bit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Jason Ekstrand [Wed, 18 Jan 2017 02:38:35 +0000 (18:38 -0800)]
nir/dominance: Better handle unreachable blocks
v2: Fix minor comments (Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
Daniel Schürmann [Sun, 19 Apr 2020 15:17:04 +0000 (16:17 +0100)]
aco: use v_subrev_f32 for fsub with an sgpr operand in src1
This fixes an accidentally introduced regression.
Fixes: 9be4be515f2a08b9c9e5ae1fc4c5dc9a830c2337 ('aco: implement 16-bit nir_op_fsub/nir_op_fadd')
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4633>
Daniel Stone [Sun, 19 Apr 2020 11:57:04 +0000 (12:57 +0100)]
CI: Disable Lima jobs due to lab unhealthiness
The BayLibre LAVA host appears to be down.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4631>
Daniel Stone [Thu, 16 Apr 2020 22:31:47 +0000 (23:31 +0100)]
ci/windows: Make Chocolatey installs more reliable
Chocolatey installs depend on downloading binaries from SourceForge,
which is an unreliable host: container builds often fail because it
cannot pick up winflexbison.
Add a loop to retry chocolatey installs if any installs have failed, and
ensure Python is in the accessible PowerShell path rather than relying
on the path being externally refreshed.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4631>
Arcady Goldmints-Orlov [Thu, 16 Apr 2020 21:28:12 +0000 (16:28 -0500)]
nir: Lower returns correctly inside nested loops
Inside nested flow control, nir_lower_returns inserts predicated breaks
in the outer block. However, it would omit doing this if the remainder
of the outer block (after the inner block) was empty. This is not
correct in the case of loops, as execution just wraps back around to the
start of the loop, so this change doesn't skip the predication inside
loops.
Fixes: 79dec93ead6e (nir: Add return lowering pass)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2724
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4603>
Jason Ekstrand [Thu, 16 Apr 2020 20:33:43 +0000 (15:33 -0500)]
anv: Apply any needed PIPE_CONTROLs before emitting state
Push constants in particular can get picked up by the hardware at weird
times that happen *before* 3DPRIMITIVE. Therefore, we need to flush
before we emit all our state to ensure that any data they may pick up is
in memory in time. This fixes an app which does vkCmdCopyBuffers
immediately followed by a vkCmdBeginRenderPass and vkCmdDraw which uses
the destination of the copy as a UBO which we push.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4601>
Jason Ekstrand [Thu, 16 Apr 2020 20:31:15 +0000 (15:31 -0500)]
anv: Move vb_emit setup closer to where it's used in flush_state
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4601>
Albert Astals Cid [Wed, 26 Feb 2020 22:05:51 +0000 (23:05 +0100)]
Fix promotion of floats to doubles
Use the f variants of the math functions if the input parameter is a
float, saves converting from float to double and running the double
variant of the math function for gaining no precision at all
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3969>
Connor Abbott [Fri, 17 Apr 2020 17:31:56 +0000 (19:31 +0200)]
ir3/ra: Fix off-by-one issues with live-range extension
The intersects() function assumes that inside each instruction values
always die before they are defined, so that if the end of one range is
the same instruction as the beginning of the next then they don't
intersect. However, this isn't the case for values that become live at
the beginning of a basic block, which become live *before* the first
instruction, or instructions that die at the end of a basic block which
die after the last instruction.
For example, imagine that we have two values, A which is defined earlier
in the block and B which is defined in the last instruction of the block
and both die at the end of the basic block (e.g. are used in the next
iteration of a loop). We would compute a range for A of, say, (10, 20)
and for B of (20, 20) since each block's end_ip is the same as the ip of
the last instruction, and RA would consider them to not interfere.
There's a similar problem with values that become live at the beginning.
The fix is to offset the block's start_ip and end_ip by one so that they
don't correspond to any actual instruction. One way to think about this
is that we're adding fake instructions at the beginning and end of a
block where values become live & die. We could invert the order, so that
values consumed by each instruction are considered dead at the end of
the previous instruction, but then values that become dead at the
beginning of the basic block would incorrectly have an empty live range,
with a similar problem at the end of the basic block if we try to say
that values are defined at the beginning of the next instruction. So
the extra padding instructions are unavoidable.
This fixes an accidental infinite loop in the shader for
dEQP-VK.spirv_assembly.type.scalar.u32.switch_vert.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4614>
Lionel Landwerlin [Fri, 17 Apr 2020 17:42:41 +0000 (20:42 +0300)]
util/sparse_free_list: manipulate node pointers using atomic primitives
Probably doesn't fix anything but those should be accessed in an
atomic way just like the head pointer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e4f01eca3b3cd1 ("util: Add a free list structure for use with util_sparse_array")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4613>
Timothy Arceri [Thu, 12 Mar 2020 23:17:08 +0000 (10:17 +1100)]
glsl: only set stage ref when uniforms referenced in stage
This updates the NIR uniform linker to behave like the GLSL IR
linker and fixes a number of CTS tests once we enable the NIR
linker for glsl.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Tue, 31 Mar 2020 02:49:30 +0000 (13:49 +1100)]
glsl: pull mark_array_elements_referenced() out into common helper
We will reuse this helper in the NIR linker in the following
patches.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Tue, 10 Mar 2020 01:55:53 +0000 (12:55 +1100)]
glsl: fix block index in NIR uniform linker
We only want to set the index for the first block of an array. Also
add a comment about why we do not break here.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Thu, 5 Mar 2020 23:27:44 +0000 (10:27 +1100)]
glsl: error check max user assignable uniform locations
This adds the error check to the NIR uniform linker.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Thu, 5 Mar 2020 03:46:26 +0000 (14:46 +1100)]
glsl: fix explicit locations for the glsl linker
We already reserved explicit locations in the GLSL linker.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Thu, 5 Mar 2020 03:51:20 +0000 (14:51 +1100)]
Revert "glsl: fix resizing of the uniform remap table"
This reverts commit
e0aa0a839f9c168784a1f50013c83877cc876094.
Instead we fix it correctly in the following patch.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Wed, 26 Feb 2020 02:17:02 +0000 (13:17 +1100)]
glsl: tidy up uniform storage value count code in NIR linker
This makes the code cleaner and better reflects what the existing
glsl IR linker does possibly fixing subtle bugs.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Thu, 6 Feb 2020 23:55:03 +0000 (10:55 +1100)]
glsl: fix struct offsets in the nir uniform linker
This change properly applies layouts to structs of uniforms in a
similar way to the GLSL IR linker.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Timothy Arceri [Fri, 13 Mar 2020 03:18:27 +0000 (14:18 +1100)]
nir: add matrix_layout to nir_variable data
This will be used by the following patch.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
Lionel Landwerlin [Fri, 17 Apr 2020 06:51:22 +0000 (09:51 +0300)]
anv: skip writing perfcntr in results on Gen12+
We were not capturing the register already so don't bother writing the
delta in the results (we were previously doing a delta between two 0
values).
v2: Fix unused function warning
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4586>
Lionel Landwerlin [Thu, 16 Apr 2020 10:03:47 +0000 (13:03 +0300)]
intel/perf: Enable MDAPI queries for Gen12
We're missing the cases for gen12 leading to those metrics going
missing.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 15b7b56eb2fb41 ("intel/perf: add TGL support")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4586>
Alyssa Rosenzweig [Fri, 17 Apr 2020 19:40:12 +0000 (15:40 -0400)]
pan/bit: Add fp16 min/max tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Wed, 15 Apr 2020 15:40:59 +0000 (11:40 -0400)]
pan/bit: Add constants test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 21:00:31 +0000 (17:00 -0400)]
pan/bit: Add fexp2_fast test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 20:59:41 +0000 (16:59 -0400)]
pan/bit: Add fexp2_fast interp
Kind of a hack and not at all how the h/w does it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 20:45:22 +0000 (16:45 -0400)]
pan/bit: Add FMA_MSCALE test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 20:21:14 +0000 (16:21 -0400)]
pan/bit: _MSCALE interp
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 19:25:27 +0000 (15:25 -0400)]
pan/bit: Add BI_TABLE test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 19:25:17 +0000 (15:25 -0400)]
pan/bit: Add log2 helper interp
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 17:19:13 +0000 (13:19 -0400)]
pan/bit: Add FMA_REDUCE test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 17:14:51 +0000 (13:14 -0400)]
pan/bit: Add BI_REDUCE_FMA interp
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:55:02 +0000 (12:55 -0400)]
pan/bit: Add frexp_log test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:50:48 +0000 (12:50 -0400)]
pan/bit: Add FREXP interp support
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Fri, 17 Apr 2020 19:52:18 +0000 (15:52 -0400)]
pan/bi: Lower special ops to 32-bit
We don't have 16-bit tables. We could probably do a bit better to avoid
so many conversions but hey.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Fri, 17 Apr 2020 19:52:03 +0000 (15:52 -0400)]
pan/bi: Round constants to 32-bit
We can only access lo/hi at 32-bit intervals.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Fri, 17 Apr 2020 19:40:00 +0000 (15:40 -0400)]
pan/bi: Dump extra bits for disasm
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Fri, 17 Apr 2020 19:37:21 +0000 (15:37 -0400)]
pan/bi: Pack MAX.v2f16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Fri, 17 Apr 2020 19:21:08 +0000 (15:21 -0400)]
pan/bi: Pack ADD.v2f16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Fri, 17 Apr 2020 19:20:50 +0000 (15:20 -0400)]
pan/bi: Structify add and min/max fp16 ADD
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Wed, 15 Apr 2020 15:45:49 +0000 (11:45 -0400)]
pan/bi: Workaround constant packing errata
Incomplete fix.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Wed, 15 Apr 2020 14:39:42 +0000 (10:39 -0400)]
pan/bi: Try to reuse constants in ALU
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Wed, 15 Apr 2020 00:20:37 +0000 (20:20 -0400)]
pan/bi: Handle st_vary with <4 components
Still no writemasks.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Wed, 15 Apr 2020 00:20:16 +0000 (20:20 -0400)]
pan/bi: Fix vec2/3 handling
Otherwise we get moves from null.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 23:50:24 +0000 (19:50 -0400)]
pan/bi: Implement flog2
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 22:52:21 +0000 (18:52 -0400)]
pan/bi: Add fexp2 implementation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 22:51:55 +0000 (18:51 -0400)]
pan/bi: Fix lower_combine swizzle rewrite
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 22:36:28 +0000 (18:36 -0400)]
pan/bi: Fix packing with low-nibble-set on hi constant
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 22:32:31 +0000 (18:32 -0400)]
pan/bi: Fix packing with multiple constants
Need to use bottom nibble of the 64, not the half.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 22:29:36 +0000 (18:29 -0400)]
pan/bi: Fix bi_get_immediate with multiple imms
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Wed, 15 Apr 2020 00:09:00 +0000 (20:09 -0400)]
pan/bi: Ensure CONSTANT srcs have types
So the next commit is valid.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 22:29:08 +0000 (18:29 -0400)]
pan/bi: Split src/dest index printing
So we can handle constant printing correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 20:59:19 +0000 (16:59 -0400)]
pan/bi: Add fexp2_fast packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 20:44:44 +0000 (16:44 -0400)]
pan/bi: Pack FMA_MSCALE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 20:31:34 +0000 (16:31 -0400)]
pan/bi: Structify FMA_MSCALE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 20:13:53 +0000 (16:13 -0400)]
pan/bi: Add _MSCALE flag for FMA/ADD
So we can bias by exponents.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 19:25:04 +0000 (15:25 -0400)]
pan/bi: Add log2_help packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 17:14:29 +0000 (13:14 -0400)]
pan/bi: Pack ADD_FREXPM
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 17:14:05 +0000 (13:14 -0400)]
pan/bi: Add bi_pack_fma_2src helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:54:17 +0000 (12:54 -0400)]
pan/bi: Add frexp_log packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:37:29 +0000 (12:37 -0400)]
pan/bi: Add log_frexpe op to IR
As part of BI_FREXP
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:34:42 +0000 (12:34 -0400)]
pan/bi: Add FLOG2_U op to disassembler
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:33:08 +0000 (12:33 -0400)]
pan/bi: Add op for ADD_FREXPM
Used in log2. Needs a new class as well due to scheduling silliness.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:22:28 +0000 (12:22 -0400)]
pan/bi: Add special op for exp2
Needs some extra help but basically exp2_fast
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 16:21:25 +0000 (12:21 -0400)]
pan/bi: Add BI_TABLE for fast table accesses
Used to implement SPECIAL ops. Separate class since they are faster
which means you can pair them with actual work on FMA.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Tue, 14 Apr 2020 00:03:48 +0000 (20:03 -0400)]
pan/bi: Disable FMA scheduling for CONVERT
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Alyssa Rosenzweig [Mon, 13 Apr 2020 22:28:29 +0000 (18:28 -0400)]
pan/bi: Add disasm for ADD.i8
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
Jason Ekstrand [Thu, 9 Apr 2020 22:09:10 +0000 (17:09 -0500)]
spirv,nir: Move the SPIR-V vector insert code to NIR
This also makes spirv_to_nir a bit simpler because the new
nir_vector_insert helper automatically handles a constant component
selector like nir_vector_extract does.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>
Jason Ekstrand [Thu, 9 Apr 2020 22:03:37 +0000 (17:03 -0500)]
spirv: Call nir_builder directly for vector_extract
The nir_builder helper already handles checking if the component
selector is an immediate and returns an undef in the OOB case.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>