radv: factor out si_emit_wait_fence code.

This code was in a few places, consolidate into one.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

intel/blorp: Handle gen6 stencil/HiZ offsets in the back-end

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add a helper for getting the byte/tile offset of a subimage

Frequently, get_image_offset_sa is combined with get_intratile_offset_sa
so it makes sense to have a single helper to do both.  If the caller
doesn't want the intratile offsets, it can simply pass NULL and ISL will
assert that they are 0.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Make get_intratile_offset_el take the element size in bits

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add a new layout for HiZ and stencil on Sandy Bridge

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Generate phys_total_el from isl_calc_phys_extent

The only surface layout for which slice0 makes any sense is GEN4_2D.
Move all of the slice0 stuff into isl_calc_phys_total_extent_el_gen4_2d
and make the others trivially return the total size in surface elements.
As a side-effect, array_pitch_el_rows is now returned from these helpers
as well.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Don't check array pitch for gen4 3D textures

Array pitch doesn't matter in this layout.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Refactor to use a phys_total_el extent.

We've already implicitly been using a physical total size in surface
elements.  This just centralizes things a bit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add an isl_assert_div helper

This is a fairly common operation and it's nice to be able to just call
the one little function.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Refactor isl_calc_array_pitch_el_rows

Over 90% of the function only applies to ISL_DIM_LAYOUT_GEN4_2D anyway
so we can just handle the other two as special cases at the top.  The
two "generic" cases below the switch only apply on gen9 and above and
only to 3D or CCS surfaces.  This implies that they only apply to
surfaces with ISL_DIM_LAYOUT_GEN4_2D.  Making them look generic is a
lie.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Move isl_calc_array_pitch_el_rows higher up

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Remove the device parameter from isl_tiling_get_info

We were only using it for validating that we don't use Ys/Yf on gen8 and
earlier.  Removing it from isl_tiling_get_info lets us remove it from a
bunch of other things that had no business needing a hardware
generation.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Rework Sandy Bridge HiZ and stencil layouts

Sandy Bridge does not technically support mipmapped depth/stencil.  In
order to work around this, we allocate what are effectively completely
separate images for each miplevel, ensure that they are page-aligned,
and manually offset to them.  Prior to layered rendering, this was a
simple matter of setting a large enough halign/valign.

With the advent of layered rendering, however, things got more
complicated.  Now, things weren't as simple as just handing a surface
off to the hardware.  Any miplevel of a normally mipmapped surface can
be considered as just an array surface given the right qpitch.  However,
the hardware gives us no capability to specify qpitch so this won't
work.  Instead, the chosen solution was to use a new "all slices at each
LOD" layout which laid things out as a mipmap of arrays rather than an
array of mipmaps.  This way you can easily offset to any of the
miplevels and each is a valid array.

Unfortunately, the "all slices at each lod" concept missed one
fundamental thing about SNB HiZ and stencil hardware:  It doesn't just
always act as if you're always working with a non-mipmapped surface, it
acts as if you're always working on a non-mipmapped surface of the same
size as LOD0.  In other words, even though it may only write the
upper-left corner of each array slice, the qpitch for the array is for a
surface the size of LOD0 of the depth surface.  This mistake causes us
to under-allocate HiZ and stencil in some cases and also to accidentally
allow different miplevels to overlap.  Sadly, piglit test coverage
didn't quite catch this until I started making changes to the resolve
code that caused additional HiZ resolves in certain tests.

This commit switches Sandy Bridge HiZ and stencil over to a new scheme
that lays out the non-zero miplevels horizontally below LOD0.  This way
they can all have the same qpitch without interfering with each other.
Technically, the miplevels still overlap, but things are spaced out
enough that each page is only in the "written area" of one LOD.

Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Drop duplicate shadow variable.

We already initialized this at the top of the function.

Trivial.

automake: Link all libGL.so variants with -Bsymbolic.

We were linking src/glx with -Bsymbolic, but not the classic/gallium X11
libGL.so.

But it's always a good idea to build all libGL.so and all DRI drivers
with -Bsymbolic, otherwise they might resolve symbols from the 3rd party
application executable or shared libraries, which is _never_ what we
want.

In particular, this can happen when intercepting OpenGL calls with
apitrace, before
https://github.com/apitrace/apitrace/commit/63194b2573176ef34efce1a5c8b08e624b8dddf5

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer()

This function never occurs in the callchain of a GL function. It occurs
only in the callchain of eglCreate*Surface and the analogous paths for
GLX.  Therefore, even if a  thread does have a bound GL context,
emitting a GL error here is wrong. A misplaced GL error, when no GL
call is made, can confuse clients.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Cleanup in intel_create_winsys_renderbuffer()

Combine variable declarations and assignments.
Trivial cleanup.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Remove bad assert on isl_format

translate_tex_format() asserted that isl_format != 0. But 0 is a valid
format, ISL_FORMAT_R32G32B32A32_FLOAT.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Fix return type of translate_tex_format()

It returns an isl_format, not GLuint BRW_FORMAT.  I updated every
translate_tex_format() found by git-grep.

No change in behavior.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Fix return type of brw_isl_format_for_mesa_format() [v2]

It returns an isl_format, not uint32_t BRW_FORMAT.
I updated every brw_isl_format_for_mesa_format() found by git-grep.

No change in behavior.

v2: Rebased atop Anuj's patch, which has some of the same fixes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)

i965: Remove an extra semicolon

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

i965: Rename brw_format variable names to isl_format

This patch makes non functional changes. Renaming is just to
make the code more readable.

V2: update the types to "enum isl_format"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Reject unsupported formats in glEGLImageTargetTexture2D()

If the EGLImage's format is not a supported texture format according to
brw_surface_formats.c, then refuse to create the miptree. This follows
the precedent in glEGLImageRenderbufferStorage (implemented by
intel_image_target_renderbuffer_storage), which rejects the EGLImage's
format if is not renderable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.

This will let us initialize the constant buffers with loops.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

genxml: Fix decoder to print the array element on field members.

Previously we'd print things like:

   0xfffbb568:  0x00010000 : Dword 1
       ReadLength: 0
       ReadLength: 1
   0xfffbb568:  0x00000001 : Dword 1
       ReadLength: 1
       ReadLength: 0

instead of the more obvious:

   0xfffbb568:  0x00010000 : Dword 1
       ReadLength[0]: 0
       ReadLength[1]: 1
   0xfffbb568:  0x00000001 : Dword 1
       ReadLength[2]: 1
       ReadLength[3]: 0

(Yes, the ralloc context here is bogus - the decoder leaks just about
everything.  We need to use proper ralloc contexts someday...)

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

genxml: Fix decoding of array groups.

If you had a group as the first element of a struct, i.e.

  <struct name="3DSTATE_CONSTANT_BODY" length="10">
    <group count="4" start="0" size="16">
      <field name="ReadLength" start="0" end="15" type="uint"/>
    </group>
    ...
  </struct>

we would get a group_offset of 0, causing create_field() to think the
field wasn't in a group, and fail to offset forward for successive array
elements.  So we'd mark all the array elements as offset 0.

Using ctx->group->elem_size is a better check for "are we in a group?".

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

genxml: Fix decoder for groups with multiple fields.

If you have something like:

    <group count="0" start="96" size="32">
      <field name="Entry_0" start="0" end="15" type="GATHER_CONSTANT_ENTRY"/>
      <field name="Entry_1" start="16" end="31" type="GATHER_CONSTANT_ENTRY"/>
    </group>

We would reset ctx->group_count to 0 after processing the first field,
so the second would not have a group count.

This is largely untested, as the only groups with multiple fields are
packets we don't emit in Mesa.  Found by inspection.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

genxml: Fix parsing of address fields in groups.

For example,

    <group count="4" start="64" size="64">
      <field name="Pointer" start="5" end="63" type="address"/>
    </group>

used to generate:

   const uint64_t v2_address =
      __gen_combine_address(data, &dw[2], values->Pointer, 0);
   ...
   const uint64_t v4_address =
      __gen_combine_address(data, &dw[4], values->Pointer, 0);
   ...

but now generates code with proper subscripts:

   const uint64_t v2_address =
      __gen_combine_address(data, &dw[2], values->Pointer[0], 0);
   ...
   const uint64_t v4_address =
      __gen_combine_address(data, &dw[4], values->Pointer[1], 0);
   ...

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

configure.ac: simplify --enable-libunwind=auto check

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

util/rand_xor: add missing include statements

Fixes for:

src/util/rand_xor.c:60:13: error: implicit declaration of function 'open' [-Werror=implicit-function-declaration]
    int fd = open("/dev/urandom", O_RDONLY);
             ^~~~
src/util/rand_xor.c:60:34: error: 'O_RDONLY' undeclared (first use in this function)
    int fd = open("/dev/urandom", O_RDONLY);
                                  ^~~~~~~~

Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

etnaviv: always do cpu_fini in transfer_unmap

The cpu_fini() call pushes the buffer back into the GPU domain, which needs
to be done for all buffers, not just the ones with CPU written content. The
etnaviv kernel driver currently doesn't validate this, but may start to do
so at a later point in time. If there is a temporary resource the fini needs
to happen before the RS uses this one as the source for the upload.

Also remove an invalid comment about flushing CPU caches, cpu_fini takes
care of everything involved in this.

Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com>

docs: update calendar, add news item and link release notes for 17.0.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 17.0.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit bdfd5658e7cd4c6925afa06bb858c0601865a1ea)

docs: add release notes for 17.0.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 46cc7a1746e03b1672c8508af49eb60546d5b61d)

glsl: fix a crash in ir_print_visitor() for bindless samplers/images

Bindless samplers/images are represented with 64-bit unsigned
integers and they can be assigned with explicit constructors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: teach opt_array_splitting about bindless images

Memory/format layout qualifiers shouldn't be lost when arrays
of images are splitted by this pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: teach opt_structure_splitting about images in structures

GL_ARB_bindless_texture allows images to be declared inside
structures, but when memory/format qualifiers are used, they
should be propagated when structures are splitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: fix broken indentation in do_structure_splitting()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: handle format layout qualifiers for struct with array of images

This handles a situation like:

struct {
   layout (r32f) image2D imgs[6];
} s;

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: handle memory qualifiers for struct with array of images

This handles a situation like:

struct {
   image2D imgs[6];
} s;

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

nvc0: Clean up unnecessary includes from gallium/auxiliary/vl/

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Simplify SO_DECL handling.

We can initialize structs directly, avoid some temporaries, and cut out
about half of the skip component handling.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

i965: Make a local for linked_xfb->Outputs[i], to shorten things.

This seems a bit more readable.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

i965: Move SOL PSIZ hacks from draw time to link time.

We can just update the gl_transform_feedback_info fields at link time
to make the VUE header fields have the right location and component.
Then we don't need to handle them specially at draw time, which is
expensive.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

mesa/main: replace remaining uses of IROUND() in GetUniform*() by round()

These were correct since they were used only in conversions to signed integers,
however this makes the implementation a bit more is more consistent and reduces
chances of propagating use of these macros to unsigned cases in the future, which
would not be correct.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/main: conversion from float in GetUniformi64v requires rounding to nearest

As we do for all other cases of float/double conversions to integers.

v2: use round() instead of IROUND() macros (Iago)

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/main: Add conversion from double to uint64/int64 in GetUniform*i64v()

v2:
  - need unsigned rounding for double->uint64 conversion (Nicolai)
  - use round() instead of IROUND() macros (Iago)

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/main: Clamp GetUniformui64v values to be >= 0

Like we do for the 32-bit case.

v2:
  - need unsigned rounding for float->uint64 conversion (Nicolai)
  - use roundf() instead of IROUND() macros (Iago)

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/main: Clamp GetUniformuiv values to be >= 0

Section 2.2.2 (Data Conversions For State Query Commands) of the
OpenGL 4.5 October 24th 2016 specification says:

"If a command returning unsigned integer data is called, such as
 GetSamplerParameterIuiv, negative values are clamped to zero."

v2: uint to int conversion should clamp to INT_MAX (Nicolai)

v3 (Iago)
  - Add conversions conversions from 64-bit integer paths
  - Rebase on master

v4:
  - need unsigned rounding for float/double->uint conversions (Nicolai)
  - use round{f}() instead of IROUND() macros (Iago)

Fixes:
KHR-GL45.gpu_shader_fp64.state_query

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v2)
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/main: fix indentation in _mesa_get_uniform()

v2: also change the style of the large conditional in that function
    to follow the style from most other parts of Mesa (Nicolai)

Reviewed-by: Matt Turner <mattst88@gmail.com>

r100: Silence numerous unused this or that warnings

radeon_fbo.c: In function ‘radeon_map_renderbuffer_s8z24’:
radeon_fbo.c:147:50: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 radeon_map_renderbuffer_s8z24(struct gl_context *ctx,
                                                  ^~~
radeon_fbo.c: In function ‘radeon_map_renderbuffer_z16’:
radeon_fbo.c:186:48: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 radeon_map_renderbuffer_z16(struct gl_context *ctx,
                                                ^~~
radeon_fbo.c: In function ‘radeon_unmap_renderbuffer_s8z24’:
radeon_fbo.c:344:52: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 radeon_unmap_renderbuffer_s8z24(struct gl_context *ctx,
                                                    ^~~
radeon_fbo.c: In function ‘radeon_unmap_renderbuffer_z16’:
radeon_fbo.c:377:50: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 radeon_unmap_renderbuffer_z16(struct gl_context *ctx,
                                                  ^~~
radeon_fbo.c: In function ‘radeon_nop_alloc_storage’:
radeon_fbo.c:624:75: warning: unused parameter ‘rb’ [-Wunused-parameter]
 radeon_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
                                                                           ^~
radeon_fbo.c:625:12: warning: unused parameter ‘internalFormat’ [-Wunused-parameter]
     GLenum internalFormat, GLuint width, GLuint height)
            ^~~~~~~~~~~~~~
radeon_fbo.c:625:35: warning: unused parameter ‘width’ [-Wunused-parameter]
     GLenum internalFormat, GLuint width, GLuint height)
                                   ^~~~~
radeon_fbo.c:625:49: warning: unused parameter ‘height’ [-Wunused-parameter]
     GLenum internalFormat, GLuint width, GLuint height)
                                                 ^~~~~~
radeon_fbo.c: In function ‘radeon_bind_framebuffer’:
radeon_fbo.c:696:74: warning: unused parameter ‘fbread’ [-Wunused-parameter]
                        struct gl_framebuffer *fb, struct gl_framebuffer *fbread)
                                                                          ^~~~~~
radeon_fbo.c: In function ‘radeon_validate_framebuffer’:
radeon_fbo.c:832:19: warning: unused variable ‘radeon’ [-Wunused-variable]
  radeonContextPtr radeon = RADEON_CONTEXT(ctx);
                   ^~~~~~

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r100: Use _mesa_get_format_base_format in radeon_update_wrapper

The wrapper is for a renderbuffer around a texture.  Textures can have
formats (e.g., 3) that aren't valide for API generated renderbuffers.
_mesa_base_fbo_format will return 0, but _mesa_get_format_base_format
will return the base format of RGB.

Fixes a crashes in piglit tests fbo-alphatest-formats (all subtests
pass) and fbo-colormask-formats (some subtests pass, some fail).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r100,r200: Don't assume glVisual is non-NULL during context creation

Thanks to EGL_MESA_configless_context, the visual pointer can be NULL.

Fixes a segfault (or assertion failure) in piglit's
egl-configless-context test.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r100: Don't assume that the base mipmap of a texture exists

Fixes crashes in piglit's gl-1.2-texture-base-level.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r600/eg: add support for tracing IBs after a hang.

This is a poor man's version of radeonsi ddebug stuff, this
should get hooked into that infrastructure, and grow more stuff,
but for now, just create R600_TRACE var that points to a file
that you want to dump the last IB to.

Signed-off-by: Dave Airlie <airlied@redhat.com>

glsl/lower_int64: only set progress when something is lowered.

Otherwise we'd get progress continually set if we had non 64-bit
versions of these ops.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Revert HTILE reset word to 0xFFFFFFFF.

0x30f regressed mad max.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Fixes: df91abfe5af "radv: Use correct clear words for HTILE."

Android: major/minor/makedev live in <sys/sysmacros.h>

sysmacros.h was getting implicitly included in types.h until recently in
AOSP master. Define MAJOR_IN_SYSMACROS to explicitly include sysmacros.h.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>

egl/android: Drop unused 'format' param in get_back_bo()

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/android: Align channel masks in HAL_PIXEL_FORMAT table

Improves readability. No change in behavior.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/drm: remove temporary fd variable

In all codepaths, this var ends up assigned to the struct, except one:
a cleanup codepath, where the `close()` was removed, leading to fd leaks.
Remove the temp fd and assign to the struct field directly instead.

CovID: 1213930
Fixes: 7ec07beedf486d8ab901 ("egl/drm: make use of the
                              dri2_display_destroy() helper")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa: throw an INVALID_OPERATION error in get_texobj_by_name()

Because get_texobj_by_name() can already throw a INVALID_ENUM
error, it makes more sense to add a check directly there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add new 'name' parameter to get_texobj_by_name()

To display better function names when INVALID_OPERATION is
returned. Requested by Timothy.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: remove unused si_pm4_state::compute_pkt

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: remove chip_class define from si_pm4.h

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: merge si_pm4_free_state_simple() into si_pm4_free_state()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/util: fix arithmetic use of 'void *' in u_vector_foreach

u_vector_foreach is currently only used by the Intel Vulkan
driver but when this macro is used in mesa core, GCC reports
a compile-time error. Probably because some compiler options
are different.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: remove _mesa from static function names

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/st: indentation tidy-up

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

freedreno/a5xx: drop WFIs in emit_marker5()

Results in always having at least one WFI between draws, which was
slowing stk down by ~5% and ~10% in xonotic.

(also drop bogus assert while we're at it.)

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: timestamp / time-elapsed queries

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: rename query result struct

Going to want the same thing for timestamp queries.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

i965: Delete dead old-school packing structs.

Trivial.

swr/rast: code cleanup (no functional change)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: whitespace changes

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: code cleanup (no functional change)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: allow early-z if shader uses depth value

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: move wireframe/point triangle binning after culling

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: remove unused functions

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: code cleanup (no functional change)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: move binner utility functions to binner.h

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE - fix/use SIMD16 calcDeterminantIntVertical()

Stop double pumping the SIMD8 version.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add renderTargetArrayIndex to SWR_PS_CONTEXT

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: make simd16 logicops avx512f safe

Express the simd16 logicops in terms of avx512f instructions.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE - add SIMD16 types to jitter

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE - fix PA_STATE_OP::Reset()

Fixes instanced GS.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE - simplify/refactor StreamOut

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE - fix conservative rasterization

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE - interleaved simdvertex output in GS

Eliminates conversion copies on GS output from simdvertex to simd16vertex.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: fix _simd16_movemask_(ps,pd) native AVX512 intrinsics

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE - primitive assembly simplification

Reduce/simplify vertex storage usage in PA_STATE_OPT, fix PA
GetNextVSOutput wrap-around behaviour and eliminate unnecessary
SIMDVERTEX copies/storage for tri fan in PA_STATE_OPT

Fixes the OpenGL tri fan test failure under SIMD16 -
triangle-rasterization-overdraw.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: silence write of cfg graph

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add CreateDirectoryPath to recursively create directories

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add support for DX1_RGB{_SRGB} formats

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: clean up whitespace

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: adjust BinPostSetupPoints* function signature

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: remove extra pixel center adjustment in BinPostSetupPoints

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

anv: Port over CACHE_MODE_1 optimization fix enables from brw.

Ben and I haven't observed these to help anything, but they enable
hardware optimizations for particular cases.  It's probably best to
enable them ahead of time, before we run into such a case.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

genxml: Add Gen9 CACHE_MODE_1 definitons.

These were already in gen8.xml but not gen9.xml.  There are a few new
fields and a couple that have changed.  These are all documented in the
Skylake PRM, Volume 2c Command Reference: Registers, Part 1.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>