microwatt.git
3 years agocore: Add a short multiplier
Paul Mackerras [Sat, 11 Sep 2021 07:10:20 +0000 (17:10 +1000)]
core: Add a short multiplier

This adds an optional 16 bit x 16 bit signed multiplier and uses it
for multiply instructions that return the low 64 bits of the product
(mull[dw][o] and mulli, but not maddld) when the operands are both in
the range -2^15 .. 2^15 - 1.   The "short" 16-bit multiplier produces
its result combinatorially, so a multiply that uses it executes in one
cycle.  This improves the coremark result by about 4%, since coremark
does quite a lot of multiplies and they almost all have operands that
fit into 16 bits.

The presence of the short multiplier is controlled by a generic at the
execute1, SOC, core and top levels.  For now, it defaults to off for
all platforms, and can be enabled using the --has_short_mult flag to
fusesoc.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoMerge pull request #324 from paulusmack/master
Michael Neuling [Mon, 13 Sep 2021 02:11:24 +0000 (12:11 +1000)]
Merge pull request #324 from paulusmack/master

Performance and timing improvements

3 years agocore: Predict not-taken conditional branches using BTC
Paul Mackerras [Tue, 7 Sep 2021 10:38:00 +0000 (20:38 +1000)]
core: Predict not-taken conditional branches using BTC

This adds a bit to the BTC to store whether the corresponding branch
instruction was taken last time it was encountered.  That lets us pass
a not-taken prediction down to decode1, which for backwards direct
branches inhibits it from redirecting fetch to the target of the
branch.  This increases coremark by about 2%.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoxilinx-mult: Move some registers later in the data flow
Paul Mackerras [Mon, 6 Sep 2021 23:32:30 +0000 (09:32 +1000)]
xilinx-mult: Move some registers later in the data flow

This changes s0 to use the P register rather than the A/B/C input
registers, thus improving the timing of the multiplier output.  The
m00, m02 and m03 multipliers now use their P registers rather than the
M registers, moving the addition they do from the second cycle to the
first.

Also, the XOR that inverts the 32 LSBs is moved before the output
register.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoMerge pull request #326 from antonblanchard/dcache-nc-fix
Paul Mackerras [Sat, 11 Sep 2021 01:57:04 +0000 (11:57 +1000)]
Merge pull request #326 from antonblanchard/dcache-nc-fix

dcache: Loads from non-cacheable PTEs load entire 64 bits

3 years agoMerge pull request #325 from paulusmack/fixes
Anton Blanchard [Fri, 10 Sep 2021 11:04:08 +0000 (21:04 +1000)]
Merge pull request #325 from paulusmack/fixes

decode1: Fix form of isel marked as single-issue

3 years agodcache: Loads from non-cacheable PTEs load entire 64 bits
Anton Blanchard [Fri, 10 Sep 2021 10:51:53 +0000 (20:51 +1000)]
dcache: Loads from non-cacheable PTEs load entire 64 bits

A non-cacheable load should only load the data requested and no more. We
do the right thing for real mode cache inhibited storage instructions,
but when loading through a non-cacheable PTE we load the entire 64 bits
regardless of the size.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agodecode1: Fix form of isel marked as single-issue
Paul Mackerras [Thu, 13 May 2021 22:41:59 +0000 (08:41 +1000)]
decode1: Fix form of isel marked as single-issue

The row in the decode table for isel with BC=0 was inadvertently left
marked as single-issue by commit 813f8340127f ("Add CR hazard
detection", 2019-10-15).  Fix it.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoMerge pull request #323 from paulusmack/fixes
Michael Neuling [Mon, 6 Sep 2021 07:17:37 +0000 (17:17 +1000)]
Merge pull request #323 from paulusmack/fixes

More instruction fixes

3 years agodecode1: Fix maddld and maddhdu to not set CR0
Paul Mackerras [Sat, 4 Sep 2021 09:36:02 +0000 (19:36 +1000)]
decode1: Fix maddld and maddhdu to not set CR0

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agocore: Fix mcrxrx, addpcis and bpermd
Paul Mackerras [Sat, 4 Sep 2021 08:20:54 +0000 (18:20 +1000)]
core: Fix mcrxrx, addpcis and bpermd

- mcrxrx put the bits in the wrong order

- addpcis was setting CR0 if the instruction bit 0 = 1, which it
  shouldn't

- bpermd was producing 0 always and additionally had the wrong bit
  numbering

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoMerge pull request #322 from paulusmack/fixes
Michael Neuling [Fri, 3 Sep 2021 02:07:06 +0000 (12:07 +1000)]
Merge pull request #322 from paulusmack/fixes

Fix bug with load hitting two previous stores

3 years agotests/misc: Add a test for a load that hits two preceding stores
Paul Mackerras [Tue, 31 Aug 2021 01:45:57 +0000 (11:45 +1000)]
tests/misc: Add a test for a load that hits two preceding stores

This checks that the store forwarding machinery in the dcache
correctly combines forwarded stores when they are partial stores
(i.e. only writing part of the doubleword, as for a byte store).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agodcache: Simplify data input to improve timing
Paul Mackerras [Mon, 30 Aug 2021 08:24:49 +0000 (18:24 +1000)]
dcache: Simplify data input to improve timing

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agodcache: Fix bug with forwarding of stores
Paul Mackerras [Tue, 31 Aug 2021 09:47:14 +0000 (19:47 +1000)]
dcache: Fix bug with forwarding of stores

We have two stages of forwarding to cover the two cycles of latency
between when something is written to BRAM and when that new data can
be read from BRAM.  When the writes to BRAM result from store
instructions, the write may write only some bytes of a row (8 bytes)
and not others, so we have a mask to enable only the written bytes to
be forwarded.  However, we only forward written data from either the
first stage of forwarding or the second, not both.  So if we have
two stores in succession that write different bytes of the same row,
and then a load from the row, we will only forward the data from the
second store, and miss the data from the first store; thus the load
will get the wrong value.

To fix this, we make the decision on which forward stage to use for
each byte individually.  This results in a 4-input multiplexer feeding
r1.data_out, with its inputs being the BRAM, the wishbone, the current
write data, and the 2nd-stage forwarding register.  Each byte of the
multiplexer is separately controlled.  The code for this multiplexer
is moved to the dcache_fast_hit process since it is used for cache
hits as well as cache misses.

This also simplifies the BRAM code by ensuring that we can use the
same source for the BRAM address and way selection for writes, whether
we are writing store data or cache line refill data from memory.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agodcache: Move way selection and forwarding earlier
Paul Mackerras [Sat, 28 Aug 2021 10:11:55 +0000 (20:11 +1000)]
dcache: Move way selection and forwarding earlier

This moves the way multiplexer for the data from the BRAM, and the
multiplexers for forwarding data from earlier stores or refills,
before a clock edge rather than after, so that now the data output
from the dcache comes from a clean latch.  To do this we remove the
extra latch on the output of the data BRAM (i.e. ADD_BUF=false) and
rearrange the logic.  The choice whether to forward or not now depends
not on way comparisons but rather on a tag comparisons, for the sake
of timing.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoMerge pull request #319 from antonblanchard/verilator-ci
Michael Neuling [Tue, 17 Aug 2021 02:31:12 +0000 (12:31 +1000)]
Merge pull request #319 from antonblanchard/verilator-ci

Add some Verilator CI tests

3 years agoMerge pull request #318 from paulusmack/pmu
Michael Neuling [Mon, 16 Aug 2021 03:08:24 +0000 (13:08 +1000)]
Merge pull request #318 from paulusmack/pmu

PMU enhancements

3 years agoMerge pull request #320 from antonblanchard/litedram-regenerate
Michael Neuling [Sun, 15 Aug 2021 23:23:27 +0000 (09:23 +1000)]
Merge pull request #320 from antonblanchard/litedram-regenerate

litedram: Regenerate from upstream litex

3 years agolitedram: Regenerate from upstream litex
Anton Blanchard [Sat, 14 Aug 2021 20:20:22 +0000 (06:20 +1000)]
litedram: Regenerate from upstream litex

This adds Joel's sdcard feature reporting to the firmware.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoci: Add verilator tests
Anton Blanchard [Sat, 14 Aug 2021 08:25:15 +0000 (18:25 +1000)]
ci: Add verilator tests

Now we have some verilator tests, add them to the CI.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agomakefile: Check environment for MEMORY_SIZE/RAM_INIT_FILE
Anton Blanchard [Sat, 14 Aug 2021 09:34:12 +0000 (19:34 +1000)]
makefile: Check environment for MEMORY_SIZE/RAM_INIT_FILE

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agomakefile: Add some verilator micropython tests
Anton Blanchard [Sat, 14 Aug 2021 06:59:50 +0000 (16:59 +1000)]
makefile: Add some verilator micropython tests

These are the same micropython tests we use against the ghdl
simulation.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoverilator: Specify top level module
Anton Blanchard [Sat, 14 Aug 2021 05:03:16 +0000 (15:03 +1000)]
verilator: Specify top level module

While verilator finds the correct top level module with the current
setup, if we start adding simulation models it can get confused.

Explicitly specify the top level module.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agomakefile: Simplify microwatt-verilator target, add Docker image
Anton Blanchard [Fri, 13 Aug 2021 05:04:06 +0000 (15:04 +1000)]
makefile: Simplify microwatt-verilator target, add Docker image

Recent versions of verilator support the --build option, allowing
us to remove a step.

Also add a Docker image for verilator.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoPMU: Add several more events
Paul Mackerras [Fri, 13 Aug 2021 09:29:48 +0000 (19:29 +1000)]
PMU: Add several more events

This implements most of the architected PMU events.  The ones missing
are mostly the ones that depend on which level of the cache hierarchy
data is fetched from.  The events implemented here, and their raw
event codes, are:

    Floating-point operation completed (100f4)
    Load completed (100fc)
    Store completed (200f0)
    Icache miss (200fc)
    ITLB miss (100f6)
    ITLB miss resolved (400fc)
    Dcache load miss (400f0)
    Dcache load miss resolved (300f8)
    Dcache store miss (300f0)
    DTLB miss (300fc)
    DTLB miss resolved (200f6)
    No instruction available and none being executed (100f8)
    Instruction dispatched (200f2, 300f2, 400f2)
    Taken branch instruction completed (200fa)
    Branch mispredicted (400f6)
    External interrupt taken (200f8)

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoMerge pull request #316 from antonblanchard/verilator-fix
Paul Mackerras [Sat, 14 Aug 2021 00:18:42 +0000 (10:18 +1000)]
Merge pull request #316 from antonblanchard/verilator-fix

Rename 'do' signal to avoid verilator System Verilog warning

3 years agoMerge pull request #317 from antonblanchard/gpio-fix
Paul Mackerras [Sat, 14 Aug 2021 00:18:12 +0000 (10:18 +1000)]
Merge pull request #317 from antonblanchard/gpio-fix

gpio: Add HAS_GPIO to avoid verilator build errors

3 years agoPMU: Fix PMC5/6 behaviour when MMCR0[PMCC] = 11
Paul Mackerras [Wed, 11 Aug 2021 07:17:25 +0000 (17:17 +1000)]
PMU: Fix PMC5/6 behaviour when MMCR0[PMCC] = 11

The architecture states that when MMCR0[PMCC] = 0b11, PMC5 and PMC6
are not part of the Performance Monitor, meaning that they are not
controlled by bits in MMCRs, and counter negative conditions in PMCs 5
and 6 don't generate Performance Monitor alerts, exceptions or
interrupts.  It doesn't say that PMC5 and PMC6 are frozen in this
case, so presumably they should continue to count run instructions and
run cycles.

This implements that behaviour.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agogpio: Add HAS_GPIO to avoid verilator build errors
Anton Blanchard [Fri, 13 Aug 2021 04:44:04 +0000 (14:44 +1000)]
gpio: Add HAS_GPIO to avoid verilator build errors

The verilator build fails with warnings and errors, because NGPIO
is 0 and we do things like:

        gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);

Set NGPIO to something reasonable (eg 32) and add HAS_GPIO to avoid
building the macro entirely if it isn't in use.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoRename 'do' signal to avoid verilator System Verilog warning
Anton Blanchard [Fri, 13 Aug 2021 03:52:51 +0000 (13:52 +1000)]
Rename 'do' signal to avoid verilator System Verilog warning

Experimenting with using ghdl to do VHDL to Verilog conversion (instead
of ghdl+yosys), verilator complains that a signal is a SystemVerilog
keyword:

%Error: microwatt.v:15013:18: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.

We could probably make this go away by disabling SystemVerilog, but
it's easy to rename the signal in question. Rename di at the same
time.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMerge pull request #315 from paulusmack/pmu
Michael Neuling [Wed, 11 Aug 2021 22:24:05 +0000 (08:24 +1000)]
Merge pull request #315 from paulusmack/pmu

Add basic PMU implementation

3 years agoMerge pull request #314 from antonblanchard/yosys-go-fast-bits
Paul Mackerras [Wed, 11 Aug 2021 06:26:29 +0000 (16:26 +1000)]
Merge pull request #314 from antonblanchard/yosys-go-fast-bits

Reduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut

3 years agoMerge pull request #313 from paulusmack/fixes
Michael Neuling [Wed, 11 Aug 2021 06:25:35 +0000 (16:25 +1000)]
Merge pull request #313 from paulusmack/fixes

Fix bug causing FP unavailable interrupts to be missed

3 years agocore: Add a basic performance monitor unit (PMU) implementation
Paul Mackerras [Mon, 26 Apr 2021 08:09:48 +0000 (18:09 +1000)]
core: Add a basic performance monitor unit (PMU) implementation

This is the start of an implementation of a PMU according to PowerISA
v3.0B.  Things not implemented yet include most architected events,
the BHRB, event-based branches, thresholding, MMCR0[TBCC] field, etc.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoReduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut
Anton Blanchard [Wed, 11 Aug 2021 04:34:41 +0000 (14:34 +1000)]
Reduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut

We've been investigating why the barrel rotator uses an enormous
number of cells on the yosys ECP5 target. Eventually it was narrowed
down to the -abc9 -nowidelut options, which see the cell count go from
4985 cells to 841 cells.

Using the same options on an Orange Crab build reduces the cell count
from 50864 to 36085. The main differences:

     LUT4                        31040 -> 25270
     PFUMX                        6956 ->     0
     L6MUX21                      1746 ->     0
     CCU2C                        2066 ->  1759

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMerge pull request #311 from antonblanchard/litesdcard-nexys-video
Michael Neuling [Tue, 10 Aug 2021 23:48:07 +0000 (09:48 +1000)]
Merge pull request #311 from antonblanchard/litesdcard-nexys-video

Update litesdcard from upstream and add Nexys Video support

3 years agoMerge pull request #312 from shenki/sdcard-soc-features
Michael Neuling [Tue, 10 Aug 2021 23:33:36 +0000 (09:33 +1000)]
Merge pull request #312 from shenki/sdcard-soc-features

litedram: Add sdcard to soc features

3 years agotests/fpu: Test FPU unavailable interrupt following a load
Paul Mackerras [Wed, 26 May 2021 07:44:19 +0000 (17:44 +1000)]
tests/fpu: Test FPU unavailable interrupt following a load

This adds a load before a floating-point load which should generate a
floating-point unavailable interrupt, to test for the bug where
unavailability interrupts can get dropped while loadstore1 is
executing instructions.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agolitedram: Add sdcard to soc features
Joel Stanley [Tue, 10 Aug 2021 09:19:29 +0000 (18:49 +0930)]
litedram: Add sdcard to soc features

Signed-off-by: Joel Stanley <joel@jms.id.au>
3 years agoexecute1: Handle interrupts during sequences of load/store operations
Paul Mackerras [Wed, 26 May 2021 07:34:12 +0000 (17:34 +1000)]
execute1: Handle interrupts during sequences of load/store operations

At present the logic prevents any interrupts from being handled while
there is a load/store instruction (one that has unit=LDST) being
executed.  However, load/store instructions can still get sent to
loadstore1.  Thus an instruction which should generate an interrupt
such as a floating-point unavailable interrupt will instead get
executed.

To fix this, when we detect that an interrupt should be generated but
loadstore1 is still executing a previous instruction, we don't execute
any new instructions, and set a new r.intr_pending flag.  That results
in busy_out being asserted (meaning that no further instructions will
come in from decode2).  When loadstore1 has finished the instructions
it has, the interrupt gets sent to writeback.  If one of the
instructions in loadstore1 generates an interrupt in the meantime, the
l_in.interrupt signal gets asserted and that clears r.intr_pending, so
the interrupt we detected gets discarded.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agolitesdcard: Add Nexys Video support
Anton Blanchard [Mon, 9 Aug 2021 20:41:45 +0000 (06:41 +1000)]
litesdcard: Add Nexys Video support

This board has a reset line that needs to be held low to power up the
SD card hardware.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agolitesdcard: Use vendor not board type
Anton Blanchard [Mon, 9 Aug 2021 20:37:09 +0000 (06:37 +1000)]
litesdcard: Use vendor not board type

litesdcard provides a macro per vendor (eg xilinx, lattice) and not per
board, so modify the fusesoc generator to take a vendor. This will make
it easier to add litesdcard to more boards.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMerge pull request #310 from antonblanchard/liteeth-update-2
Paul Mackerras [Tue, 10 Aug 2021 04:04:55 +0000 (14:04 +1000)]
Merge pull request #310 from antonblanchard/liteeth-update-2

Update liteeth from upstream and add Nexys Video support

3 years agoliteeth: Regenerate from upstream litex
Anton Blanchard [Mon, 9 Aug 2021 03:55:58 +0000 (13:55 +1000)]
liteeth: Regenerate from upstream litex

Unfortunately the CSR layout has shifted on upstream litex, so this
is built with the following litex patch backed out:

aad56a047a33 ("integration/soc: Use CSR automatic allocation.")

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoliteeth: Update yaml config
Anton Blanchard [Mon, 9 Aug 2021 03:49:25 +0000 (13:49 +1000)]
liteeth: Update yaml config

csr_data_width is no longer required. Add ntxslots and nrxslots
parameters but set them to the default value.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoAdd liteeth support to Nexys Video
Anton Blanchard [Wed, 4 Aug 2021 05:59:43 +0000 (15:59 +1000)]
Add liteeth support to Nexys Video

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMerge pull request #307 from antonblanchard/litedram-update
Michael Neuling [Mon, 9 Aug 2021 05:42:05 +0000 (15:42 +1000)]
Merge pull request #307 from antonblanchard/litedram-update

Updating to latest upstream litedram and some cleanups to associated scripts

3 years agoMerge pull request #309 from antonblanchard/clk-cleanup
Michael Neuling [Mon, 9 Aug 2021 05:31:09 +0000 (15:31 +1000)]
Merge pull request #309 from antonblanchard/clk-cleanup

Small cleanups to clock definitions

3 years agoMerge pull request #308 from antonblanchard/small-fixes
Michael Neuling [Mon, 9 Aug 2021 04:25:06 +0000 (14:25 +1000)]
Merge pull request #308 from antonblanchard/small-fixes

Fix some whitespace issues

3 years agoRemove -add from xdc files
Anton Blanchard [Mon, 9 Aug 2021 03:26:32 +0000 (13:26 +1000)]
Remove -add from xdc files

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoRemove -waveform from xdc files
Anton Blanchard [Mon, 9 Aug 2021 03:02:01 +0000 (13:02 +1000)]
Remove -waveform from xdc files

A 50% duty cycle is the default, so no need to use -waveform.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoFix some whitespace issues
Anton Blanchard [Sun, 8 Aug 2021 20:44:43 +0000 (06:44 +1000)]
Fix some whitespace issues

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMerge pull request #305 from mikey/noflatten
Anton Blanchard [Mon, 9 Aug 2021 01:28:49 +0000 (11:28 +1000)]
Merge pull request #305 from mikey/noflatten

ci: Remove noflatten to reduce size of ECP5 builds

3 years agolitedram: Regenerate from upstream litex
Anton Blanchard [Mon, 9 Aug 2021 00:54:35 +0000 (10:54 +1000)]
litedram: Regenerate from upstream litex

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agolitedram: sdrinit() is now sdram_init()
Anton Blanchard [Mon, 9 Aug 2021 00:53:51 +0000 (10:53 +1000)]
litedram: sdrinit() is now sdram_init()

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agolitedram: Fix compiler warning
Anton Blanchard [Mon, 9 Aug 2021 00:29:48 +0000 (10:29 +1000)]
litedram: Fix compiler warning

define MAIN_RAM_BASE and MAIN_RAM_SIZE as unsigned long

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agolitedram: Update yaml files
Anton Blanchard [Mon, 9 Aug 2021 00:26:35 +0000 (10:26 +1000)]
litedram: Update yaml files

Update the litedram yaml files based on latest upstream.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agolitedram: simplify generate.py
Anton Blanchard [Mon, 9 Aug 2021 00:24:38 +0000 (10:24 +1000)]
litedram: simplify generate.py

We can call litedram_gen instead of doing the work ourselves.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agolitedram: Remove variables.mak
Anton Blanchard [Sun, 8 Aug 2021 23:49:03 +0000 (09:49 +1000)]
litedram: Remove variables.mak

Instead of creating variables.mak, just pass the variables in on
the make command line.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoci: Remove noflatten to reduce size of ECP5 builds
Michael Neuling [Wed, 4 Aug 2021 06:33:52 +0000 (16:33 +1000)]
ci: Remove noflatten to reduce size of ECP5 builds

This option was added in the commit but is no longer needed for github
CI to work.

    commit ef0dcf3bc6380cd6c3454cac7ff881a7454a8281
    Author: Michael Neuling <mikey@neuling.org>
    Date:   Thu Jul 2 14:36:14 2020 +1000
    Add SYNTH_ECP5_FLAGS option for building

Removing noflatten has the added advantage that it gets our builds
from 75% down to 59% usage on ECP5 85K.

Signed-off-by: Michael Neuling <mikey@neuling.org>
3 years agoMerge pull request #299 from mikey/vunit-make
Anton Blanchard [Wed, 4 Aug 2021 03:59:22 +0000 (13:59 +1000)]
Merge pull request #299 from mikey/vunit-make

makefile: Add check_vunit

3 years agoMerge pull request #304 from umarcor/ci-backends
Michael Neuling [Tue, 3 Aug 2021 23:57:35 +0000 (09:57 +1000)]
Merge pull request #304 from umarcor/ci-backends

ci: test 'build' with LLVM and GCC backends

3 years agoci: test 'build' with LLVM and GCC backends
umarcor [Wed, 21 Jul 2021 22:02:41 +0000 (00:02 +0200)]
ci: test 'build' with LLVM and GCC backends

Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
3 years agoMerge pull request #301 from umarcor/vunit-cleanup
Michael Neuling [Mon, 2 Aug 2021 04:22:11 +0000 (14:22 +1000)]
Merge pull request #301 from umarcor/vunit-cleanup

VUnit cleanup

3 years agomakefile: Add check_vunit
Michael Neuling [Mon, 21 Jun 2021 01:35:56 +0000 (11:35 +1000)]
makefile: Add check_vunit

Allow newly added vuint run script to be run via make. Also integrate
with DOCKER/PODMAN=1.

Signed-off-by: Michael Neuling <mikey@neuling.org>
3 years agoVUnit: style
umarcor [Wed, 21 Jul 2021 17:54:27 +0000 (19:54 +0200)]
VUnit: style

Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
3 years agoVUnit: use Path.glob instead of glob.glob
umarcor [Wed, 21 Jul 2021 17:52:24 +0000 (19:52 +0200)]
VUnit: use Path.glob instead of glob.glob

Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
3 years agoci: add 'workflow_dispatch'
umarcor [Wed, 21 Jul 2021 16:09:37 +0000 (18:09 +0200)]
ci: add 'workflow_dispatch'

Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
3 years agoci: in job 'VUnit' use a container step instead of a container job
umarcor [Wed, 21 Jul 2021 16:04:15 +0000 (18:04 +0200)]
ci: in job 'VUnit' use a container step instead of a container job

Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
3 years agoReduce the size of icache to help yosys ECP5 builds (#303)
Michael Neuling [Sat, 31 Jul 2021 01:18:39 +0000 (11:18 +1000)]
Reduce the size of icache to help yosys ECP5 builds (#303)

The icache RAM is currently LUT ram not block ram. This massively
bloats the icache size. We think this is due to yosys not inferencing
the RAM correctly but that's yet to be confirmed.

Work around this for now by reducing the default size of the icache
RAM for the ECP5 builds.

On the ECP5 85K builts, this gets us from 95% down to 76% and helps
our CI to pass.

Signed-off-by: Michael Neuling <mikey@neuling.org>
3 years agoMerge pull request #296 from LarsAsplund/logging-checking
Michael Neuling [Mon, 21 Jun 2021 07:58:34 +0000 (17:58 +1000)]
Merge pull request #296 from LarsAsplund/logging-checking

Replaced VHDL assert and report with VUnit checking and logging

3 years agoMerge pull request #298 from paulusmack/master
Michael Neuling [Mon, 21 Jun 2021 01:51:13 +0000 (11:51 +1000)]
Merge pull request #298 from paulusmack/master

MMU: Implement a vestigial partition table

3 years agoMerge pull request #295 from LarsAsplund/master
Michael Neuling [Mon, 21 Jun 2021 01:25:40 +0000 (11:25 +1000)]
Merge pull request #295 from LarsAsplund/master

Run VHDL tests with VUnit

3 years agoMMU: Implement a vestigial partition table
Paul Mackerras [Thu, 17 Jun 2021 10:01:32 +0000 (20:01 +1000)]
MMU: Implement a vestigial partition table

This implements a 1-entry partition table, so that instead of getting
the process table base address from the PRTBL SPR, the MMU now reads
the doubleword pointed to by the PTCR register plus 8 to get the
process table base address.  The partition table entry is cached.

Having the PTCR and the vestigial partition table reduces the amount
of software change required in Linux for Microwatt support.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoReplaced VHDL assert and report with VUnit checking and logging
Lars Asplund [Wed, 9 Jun 2021 21:50:02 +0000 (23:50 +0200)]
Replaced VHDL assert and report with VUnit checking and logging

The VUnit log package is a SW style logging framework in VHDL and the check package is an assertion library doing its error reporting with VUnit logging.
These testbenches don't use, and do not need, very advanced logging/checking features but the following was possible to improve

- Checking equality in VHDL can be quite tedious with a lot of type conversions and long message strings to explain the data received and what was expected.
  VUnit's check_equal procedure allow comparison between same or similar types and automatically create the error message for you.
- The code has report statements used for testbench progress reporting and debugging. These were replaced with the info and debug procedures.
  info logs are visible by default while debug is not. This means that debug logs don't have to be commented, which they are now, when not used.
  Instead there is a show procedure making debug messages visible. The show procedure has been commented to hide the debug messages but a more elegant
  solution is to control visibility from a generic and then set that generic from the command line. I've left this as a TODO but the run script allow you to
  extend the standard CLI of VUnit to add new options and you can also set generics from the run script.
- VUnit log messages are color coded if color codes are supported by the terminal. It makes it quicker to spot messages of different types when there are many log messages.
  Error messages will always be made visible on the terminal but you must use the -v (verbose) to see other logs.
- Some tests have a lot of "metvalue detected" warning messages from the numeric_std package and these clutter the logs when using the -v option. VUnit has a simulator independent
  option allowing you to suppress those messages. That option has been enabled.

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years agoRun VUnit tests in CI
Lars Asplund [Wed, 9 Jun 2021 14:19:24 +0000 (16:19 +0200)]
Run VUnit tests in CI

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years agoOrganized VUnit testbenches into test cases.
Lars Asplund [Tue, 8 Jun 2021 20:32:57 +0000 (22:32 +0200)]
Organized VUnit testbenches into test cases.

Several of the testbenches have stimuli code divided into sections preceded with a header comment explaining
what is being tested. These sections have been made into VUnit test cases. The default behavior of VUnit is
to run each test case in a separate simulation which comes with a number of benefits:

* A failing test case doesn't prevent other test cases to be executed
* Test cases are independent. A test case cannot fail as a side-effect to a problem with another test case
* Test execution can be more parallelized and the overall test execution time reduced

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years agoMake core testbenches recognized by VUnit
Lars Asplund [Mon, 7 Jun 2021 20:34:00 +0000 (22:34 +0200)]
Make core testbenches recognized by VUnit

This commit also removes the dependencies these testbenches have on VHPIDIRECT.
The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using
foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists.
For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions.

The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using
the -p option to the run.py script

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years agoAdded VUnit run script.
Lars Asplund [Mon, 7 Jun 2021 20:05:57 +0000 (22:05 +0200)]
Added VUnit run script.

The VUnit run script will find all VHDL files based on given search patterns, figure out their dependencies, and support incremental compile based on the dependencies.
The same script is used for all VUnit supported simulators. Supporting several simulators simplifies the adoption of this project.

At this point only compilation is performed. Coming commits will enable simulation of VHDL testbenches.

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
3 years agoMerge pull request #277 from paulus/gpio
Michael Neuling [Mon, 17 May 2021 06:19:47 +0000 (16:19 +1000)]
Merge pull request #277 from paulus/gpio

A few cleanups. GPIO IRQ number is now 4 as 3 is now taken by the SD card.

3 years agoMerge pull request #287 from paulusmack/master
Michael Neuling [Thu, 13 May 2021 23:11:41 +0000 (09:11 +1000)]
Merge pull request #287 from paulusmack/master

Add SD card interface

3 years agoMerge pull request #278 from shenki/openocd-v0.11
Paul Mackerras [Tue, 11 May 2021 10:25:29 +0000 (20:25 +1000)]
Merge pull request #278 from shenki/openocd-v0.11

Add files for openocd v0.11

3 years agoopenocd: Fix verify command for v0.10
Joel Stanley [Tue, 11 May 2021 04:47:26 +0000 (14:17 +0930)]
openocd: Fix verify command for v0.10

v0.11 uses verify_image, which is not supported by v0.11. Use the old
verify_bank for v0.10.

Signed-off-by: Joel Stanley <joel@jms.id.au>
3 years agoarty_a7: Add litesdcard interface
Paul Mackerras [Thu, 15 Apr 2021 07:22:31 +0000 (17:22 +1000)]
arty_a7: Add litesdcard interface

This adds litesdcard.v generated from the litex/litesdcard project,
along with logic in top-arty.vhdl to connect it into the system.
There is now a DMA wishbone coming in to soc.vhdl which is narrower
than the other wishbone masters (it has 32-bit data rather than
64-bit) so there is a widening/narrowing adapter between it and the
main wishbone master arbiter.

Also, litesdcard generates a non-pipelined wishbone for its DMA
connection, which needs to be converted to a pipelined wishbone.  We
have a latch on both the incoming and outgoing sides of the wishbone
in order to help make timing (at the cost of two extra cycles of
latency).

litesdcard generates an interrupt signal which is wired up to input 3
of the ICS (IRQ 19).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoicache: Snoop writes to memory by other agents
Paul Mackerras [Tue, 11 May 2021 04:04:08 +0000 (14:04 +1000)]
icache: Snoop writes to memory by other agents

This makes the icache snoop writes to memory in the same way that the
dcache does, thus making DMA cache-coherent for the icache as well as
the dcache.

This also simplifies the logic for the WAIT_ACK state by removing the
stbs_done variable, since is_last_row(r.store_row, r.end_row_ix) can
only be true when stbs_done is true.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agodcache: Simplify logic in RELOAD_WAIT_ACK state
Paul Mackerras [Tue, 11 May 2021 01:29:46 +0000 (11:29 +1000)]
dcache: Simplify logic in RELOAD_WAIT_ACK state

Since the expression is_last_row(r1.store_row, r1.end_row_ix) can only
be true when stbs_done is true, there is no need to include stbs_done
in the expression for the reload being completed, and hence no need to
compute stbs_done in the RELOAD_WAIT_ACK state.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agodcache: Snoop writes to memory by other agents
Paul Mackerras [Tue, 11 May 2021 00:54:57 +0000 (10:54 +1000)]
dcache: Snoop writes to memory by other agents

This adds a path where the wishbone that goes out to memory and I/O
also gets fed back to the dcache, which looks for writes that it
didn't initiate, and invalidates any cache line that gets written to.

This involves a second read port on the cache tag RAM for looking up
the snooped writes, and effectively a second write port on the cache
valid bit array to clear bits corresponding to snoop hits.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoMerge pull request #283 from antonblanchard/whitespace
Paul Mackerras [Wed, 5 May 2021 00:20:46 +0000 (10:20 +1000)]
Merge pull request #283 from antonblanchard/whitespace

Fix a few whitespace issues.  Only changes whitespace and comments.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years agoUpdate documentation. (#280)
Antony Vennard [Wed, 5 May 2021 00:15:26 +0000 (02:15 +0200)]
Update documentation. (#280)

Update documentation to reference fusesoc init for Xilinx boards, for
those like me who have never used fusesoc before. Add a reference to the
board files for Digilent boards and comment on perhaps installing them
for other boards as appropriate.

Signed-off-by: Antony Vennard <antony@vennard.ch>
3 years agoMerge pull request #286 from antonblanchard/Makefile-cleanup-3
Anton Blanchard [Thu, 25 Mar 2021 03:43:45 +0000 (14:43 +1100)]
Merge pull request #286 from antonblanchard/Makefile-cleanup-3

A few more Makefile cleanups

3 years agoRemove unused GHDL_TARGET_GENERICS
Anton Blanchard [Thu, 25 Mar 2021 03:05:00 +0000 (14:05 +1100)]
Remove unused GHDL_TARGET_GENERICS

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMove verilator --trace flag into VERILATOR_FLAGS
Anton Blanchard [Wed, 24 Mar 2021 10:40:26 +0000 (21:40 +1100)]
Move verilator --trace flag into VERILATOR_FLAGS

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMerge pull request #285 from antonblanchard/Makefile-cleanup-2
Anton Blanchard [Wed, 24 Mar 2021 10:31:54 +0000 (21:31 +1100)]
Merge pull request #285 from antonblanchard/Makefile-cleanup-2

A few Makefile cleanups

3 years agoMerge pull request #281 from antonblanchard/cache-tlb-parameters
Anton Blanchard [Wed, 24 Mar 2021 09:44:45 +0000 (20:44 +1100)]
Merge pull request #281 from antonblanchard/cache-tlb-parameters

Pass icache/dcache/tlb parameters down from soc

3 years agoRemove -frelaxed
Anton Blanchard [Wed, 24 Mar 2021 06:08:29 +0000 (17:08 +1100)]
Remove -frelaxed

We don't appear to need this any more, so remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoUse VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator targets
Anton Blanchard [Wed, 24 Mar 2021 06:07:56 +0000 (17:07 +1100)]
Use VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator targets

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoRemove core_files from soc_files and fpga_files
Anton Blanchard [Wed, 24 Mar 2021 04:08:18 +0000 (15:08 +1100)]
Remove core_files from soc_files and fpga_files

We were already including the core_files at the same time as the
soc_files in many targets.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years agoMerge pull request #284 from antonblanchard/boot-clocks
Anton Blanchard [Tue, 23 Mar 2021 09:02:27 +0000 (20:02 +1100)]
Merge pull request #284 from antonblanchard/boot-clocks

Allow SPI BOOT_CLOCKS to be overridden by top level

3 years agoReformat spi_flash_ctrl
Anton Blanchard [Mon, 22 Mar 2021 00:01:10 +0000 (11:01 +1100)]
Reformat spi_flash_ctrl

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>