dri: Allow __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS in driCreateContextAttribs

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

i965: Only enable __DRI2_ROBUSTNESS if kernel support is available

Rather than always advertising the extension but failing to create a
context with reset notifiction, just don't advertise it.  I don't know
why it didn't occur to me to do it this way in the first place.

NOTE: Kristian requested that I provide a follow-up for master that
dynamically generates the list of DRI extensions instead of selected
between two hardcoded lists.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Suggested-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

Revert "i965: Make the driver compile until a proper libdrm can be released."

libdrm 2.4.48 has been released.

This reverts commit bd4596efac2b783b789392a222da909efcd0fd3b.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Bump libdrm requirement

drm_intel_get_reset_stats is only available in libdrm-2.4.48, and
libdrm-2.4.49 contains an important bug fix in that function.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

egl: Kill macro _EGL_DECLARE_MUTEX

Replace all occurences of the macro with its expansion.

It seems that the macro intended to provide cross-platform static mutex
intialization. However, it had the same definition in all pre-processor
paths:
    #define _EGL_DECLARE_MUTEX(m) _EGLMutex m = _EGL_MUTEX_INITIALIZER

Therefore this abstraction obscured rather than helped.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

egl: Enable EGL_EXT_client_extensions

Insert two fields into _egl_global to hold the client extensions and
statically initialize them:
    ClientExtensions // a struct of bools
    ClientExtensionString

Post-patch, Mesa supports exactly one client extension,
EGL_EXT_client_extensions.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

radeon/compute: Unconditionally inline all functions v2

We need to do this until function calls are supported.

v2:
  - Fix loop conditional

https://bugs.freedesktop.org/show_bug.cgi?id=64225

CC: "10.0" <mesa-stable@lists.freedesktop.org>

i965: Use __attribute__((flatten)) on fast tiled teximage code.

The fast tiled texture upload code does not compile with GCC 4.8's -Og
optimization flag.

memcpy() has the always_inline attribute set.  This poses a problem,
since {x,y}tile_copy_faster calls it indirectly via {x,y}tile_copy,
and {x,y}tile_copy normally aren't inlined at -Og.

Using __attribute__((flatten)) tells GCC to inline every function call
inside the function, which I believe was the author's intent.

Fix suggested by Alexander Monakov.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Cc: mesa-stable@lists.freedesktop.org

llvmpipe: support 8bit subpixel precision

8 bit precision is required by d3d10 but unfortunately
requires 64 bit rasterizer. This commit implements
64 bit rasterization with full support for 8bit subpixel
precision. It's a combination of all individual commits
from the llvmpipe-rast-64 branch.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gbm/dri: hide extension loader symbols

They should not be exposed.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>

i965: Enable ARB_draw_indirect (and ARB_multi_draw_indirect) on Gen7+

.. and mark them off on the extensions list as done.

V2: Enable only if pipelined register writes work.
V3: Also update relnotes

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vbo: map indirect buffer and extract params if doing sw primitive restart

V2: Check for mapping failure (thanks Brian)
V3: - Change error on mapping failure to OUT_OF_MEMORY (Brian)
    - Unconst; remove casting away of const.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: pass indirect buffer to sw primitive restart

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: pass indirect buffer to primitive restart check

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: implement indirect drawing for Gen7

Just prior to emitting the 3DPRIMITIVE command, we load each of the
indirect registers. The values loaded are either from offsets into the
current indirect BO, or constant zero if the parameter is not used for
this draw.

Enabling use of the indirect registers is done by turning on a bit in
the first dword of the 3DPRIMITIVE command itself.

V3: - Deduplicate the common part of both indexed and nonindexed indirect
setup.
    - Just refer to the indirect bo out of the context directly.

V4: - Fix bo reference to specify the range we care about.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add new defines for indirect draws

- MMIO registers for draw parameters
- New bit in 3DPRIMITIVE command to enable indirection

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

vbo: Flesh out implementation of indirect draws

Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add indirect_offset, is_indirect to _mesa_prim

V3: Add missing cases
V4: Add indirect_offset here too

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Add validation helpers for new indirect draws

Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series.

V3: - Disallow primcount==0 for DrawMulti*Indirect. The spec is unclear
      on this, but it's silly. We might go back on this later if it
      turns out to be a problem.

    - Make it clear that the caller has dealt with stride==0

V4: - Allow primcount==0 again.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Add binding point for indirect buffer

Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Add extension scaffolding for ARB_draw_indirect

We will reuse the same extension flag for ARB_multi_draw_indirect since
it can always be supported by looping.

Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

glapi: add plumbing for GL_ARB_draw_indirect and GL_ARB_multi_draw_indirect

Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: add indirect drawing buffer parameter to draw functions

Split from patch implementing ARB_draw_indirect.

v2: Const-qualify the struct gl_buffer_object *indirect argument.
v3: Fix up some more draw calls for new argument.
v4: Fix up rebase conflicts in i965.
v5: Undo const-qualification

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

docs/llvmpipe: Add one other good reference.

docs: describe the INTEL_* envvars that do exist

V2: drop description of `fall` and `wm`, which have been removed by the
previous patch; describe `stats`.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

drop old INTEL_DEBUG names for `perf` (fall) and `fs` (wm)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: remove unused DEBUG_IOCTL

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeon: change last instance of DEBUG_IOCTL to use RADEON_IOCTL

DEBUG_IOCTL comes from i965, and is about to be removed. Both defines
have the same value (4).

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

docs: drop INTEL_* envvars which no longer exist

These were removed back in 2012.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

docs: bump supported shading language version

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/mesa: respect higher GLSL levels. (v2)

Limit the max glsl version level to what the state tracker supports.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glsl: Improve error message when attemping assignment to unsized array

V2: Return after error to avoid cascading error messages and
removed redundant "to" from error message

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

intel: enable GL_AMD_vertex_shader_layer extension for gen7+

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

radeonsi: implement MSAA for CIK

There are also some changes to the printfs.

Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: enable 2D tiling on CIK

libdrm does the DRM version check and decides if 2D tiling is used.

Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>

mesa: initialize gl_renderbuffer::Depth in core

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Make the first pre-allocation heuristic be the post heuristic.

I recently made us try two different things that tried to reduce register
pressure so that we would be more likely to allocate successfully.  But
now that we have the logic for trying two, we can make the first thing we
try be the normal, not-prioritizing-register-pressure heuristic.

This means one less scheduling pass in the common case of that heuristic
not producing spills, plus the best schedule we know how to produce, if
that one happens to succeed.  This is important, because our register
allocation produces a lot of possibly avoidable dependencies for the
post-register-allocation schedule, despite ra_set_allocate_round_robin().

GLB2.7: 1.04127% +/- 0.732461% fps improvement (n=31)
nexuiz: No difference (n=5)
lightsmark: 0.838512% +/- 0.300147% fps improvement (n=86)
minecraft apitrace: No difference (n=15)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa: Remove the ralloc canary on release builds.

The canary is basically just to give a better debugging message when you
ralloc_free() something that wasn't rallocated.  Reduces maximum memory
usage of apitrace replay of the dota2 demo by 60MB on my 64-bit system (so
half that on a real 32-bit dota2 environment).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix streamed state dumping/annotation after the blorp-flush change.

I think I was thinking of the batch command packet cache when I pasted
this in, but this counter is only used for dumping out streamed state for
INTEL_DEBUG=batch and for putting annotations in our aub files.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Let driconf clamp_max_samples affect context version

Commit 2f89662 added the driconf option 'clamp_max_samples'.  In that
commit, the option did not alter the context version. The neglect to
alter the context version is a fatal issue for some apps.

For example, consider running Chromium with clamp_max_samples=0.
Pre-patch, Mesa creates a GL 3.0 context but clamps GL_MAX_SAMPLES to
0. This violates the GL 3.0 spec, which requires GL_MAX_SAMPLES >= 4.
The spec violation causes WebGL context creation to fail in many
scenarios because Chromium correctly assumes that a GL 3.0 context
supports at least 4 samples.

Since the driconf option was introduced largely for Chromium, the issue
really needs fixing.

This patch fixes calculation of the context version to respect the
post-clamped value of GL_MAX_SAMPLES. This in turn fixes WebGL on
Chromium when clamp_max_samples=0.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

i965: Share code between intel_quantize_num_samples and clamp_max_samples

clamp_max_samples() and intel_quantize_num_samples() each maintained
their own list of which MSAA modes the hardware supports. This patch
removes the duplication by making intel_quantize_num_samples() use the
same list as clamp_max_samples(), the list maintained in
brw_supported_msaa_modes().

By removing the duplication, we prevent the scenario where someone
updates one list but forgets to update the other.

Move function `brw_context.c:static brw_supported_msaa_modes()` to
`intel_screen.c:(non-static) intel_supported_msaa_modes()` and patch
intel_quantize_num_samples() to use the list returned by that function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

i965: Terminate brw_supported_msaa_modes() list with -1, not 0

This simplifies the loop logic in a subsqequent patch that refactors
intel_quantize_num_samples() to use brw_supported_msaa_modes().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

st/mesa: simplify writemask for emitting fog result

Reviewed-by: José Fonseca <jfonseca@vmware.com>

mesa: fix indentation in ffvertex_prog.c

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

tgsi: Prevent emission of instructions with empty writemask.

These degenerate instructions can often be emitted by state trackers
when the semantics of instructions don't match precisely.

Reviewed-by: Brian Paul <brianp@vmware.com>

tgsi: Rework calls to ureg_emit_insn().

Mere syntactical change.

Reviewed-by: Brian Paul <brianp@vmware.com>

docs: Add a section with recommended reading for llvmpipe development.

Several of links the were contributed by Keith Whitwell and Roland Scheidegger.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe: (trivial) disable new accurate origin calculation

It looks like there's some bugs in it...

meta: Move declaration before code.

Fixes MSVC build.

meta.c(2411) : error C2143: syntax error : missing ';' before 'type'
meta.c(2411) : error C2143: syntax error : missing ')' before 'type'
meta.c(2411) : error C2065: 'layer' : undeclared identifier
meta.c(2411) : error C2059: syntax error : ')'
meta.c(2411) : error C2143: syntax error : missing ';' before '{'
meta.c(2413) : error C2065: 'layer' : undeclared identifier
meta.c(2415) : error C2065: 'layer' : undeclared identifier

Signed-off-by: Vinson Lee <vlee@freedesktop.org>

mesa: Implement GL_FRAMEBUFFER_ATTACHMENT_LAYERED query.

From section 6.1.18 (Renderbuffer Object Queries) of the GL 3.2 spec,
under the heading "If the value of FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE
is TEXTURE, then":

    If pname is FRAMEBUFFER_ATTACHMENT_LAYERED, then params will
    contain TRUE if an entire level of a three-dimesional texture,
    cube map texture, or one-or two-dimensional array texture is
    attached. Otherwise, params will contain FALSE.

Fixes piglit tests:
- spec/!OpenGL 3.2/layered-rendering/framebuffer-layered-attachments
- spec/!OpenGL 3.2/layered-rendering/framebuffertexture-defaults

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
v2: Don't include "EXT" in the error message, since this query only
makes sensen in context versions that have adopted
glGetFramebufferAttachmentParameteriv().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Fix texture target validation for glFramebufferTexture()

Previously we were using the code path for validating
glFramebufferTextureLayer().  But glFramebufferTexture() allows
additional texture types.

Fixes piglit tests:
- spec/!OpenGL 3.2/layered-rendering/gl-layer-cube-map
- spec/!OpenGL 3.2/layered-rendering/framebuffertexture

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
v2: Clarify comment above framebuffer_texture().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Fix fast clear of depth buffers.

From section 4.4.7 (Layered Framebuffers) of the GLSL 3.2 spec:

    When the Clear or ClearBuffer* commands are used to clear a
    layered framebuffer attachment, all layers of the attachment are
    cleared.

This patch fixes the fast depth clear path.

Fixes piglit test "spec/!OpenGL 3.2/layered-rendering/clear-depth".

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Fix blorp clear of layered framebuffers.

From section 4.4.7 (Layered Framebuffers) of the GLSL 3.2 spec:

    When the Clear or ClearBuffer* commands are used to clear a
    layered framebuffer attachment, all layers of the attachment are
    cleared.

This patch fixes the blorp clear path for color buffers.

Fixes piglit test "spec/!OpenGL 3.2/layered-rendering/clear-color".

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: refactor blorp clear code in preparation for layered clears.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

meta: fix meta clear of layered framebuffers

From section 4.4.7 (Layered Framebuffers) of the GLSL 3.2 spec:

    When the Clear or ClearBuffer* commands are used to clear a
    layered framebuffer attachment, all layers of the attachment are
    cleared.

This patch fixes meta clears to properly clear all layers of a layered
framebuffer attachment.  We accomplish this by adding a geometry
shader to the meta clear program which sets gl_Layer to a uniform
value.  When clearing a layered framebuffer, we execute in a loop,
setting the uniform to point to each layer in turn.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa: Track number of layers in layered framebuffers.

In order to properly clear layered framebuffers, we need to know how
many layers they have.  The easiest way to do this is to record it in
the gl_framebuffer struct when we check framebuffer completeness.

This patch replaces the gl_framebuffer::Layered boolean with a
gl_framebuffer::NumLayers integer, which is 0 if the framebuffer is
not layered, and equal to the number of layers otherwise.

v2: Remove gl_framebuffer::Layered and make gl_framebuffer::NumLayers
always have a defined value.  Fix factor of 6 error in the number of
layers in a cube map array.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

nvc0: inform kernel about buffers that screen_create touches

Prevents a GPU page fault if somehow the uniform bo gets evicted
before the screen_create pushbuf has been submitted.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

radeonsi/compute: Fix LDS size calculation

We need to include the number of LDS bytes allocated by the state tracker.

CC: "10.0" <mesa-stable@lists.freedesktop.org>

r600g/compute: Add a work-around for flushing issues on Cayman

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
https://bugs.freedesktop.org/show_bug.cgi?id=69321

CC: "10.0" <mesa-stable@lists.freedesktop.org>

glsl: Fix interstage uniform interface block link error detection.

Previously, we checked for interstage uniform interface block link
errors in validate_interstage_interface_blocks(), which is only called
on pairs of adjacent shader stages.  Therefore, we failed to detect
uniform interface block mismatches between non-adjacent shader stages.

Before the introduction of geometry shaders, this wasn't a problem,
because the only supported shader stages were vertex and fragment
shaders, therefore they were always adjacent.  However, now that we
allow a program to contain vertex, geometry, and fragment shaders,
that is no longer the case.

Fixes piglit test "skip-stage-uniform-block-array-size-mismatch".

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
v2: Rename validate_interstage_interface_blocks() to
validate_interstage_inout_blocks() to reflect the fact that it no
longer validates uniform blocks.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
v3: Make validate_interstage_inout_blocks() skip uniform blocks.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Fix cross-version linking between VS and GS.

Previously, when attempting to link a vertex shader and a geometry
shader that use different GLSL versions, we would sometimes generate a
link error due to the implicit declaration of gl_PerVertex being
different between the two GLSL versions.

This patch fixes that problem by only requiring interface block
definitions to match when they are explicitly declared.

Fixes piglit test "shaders/version-mixing vs-gs".

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
v2: In the interface_block_definition constructor, move the assignment
to explicitly_declared after the existing if block.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Prohibit illegal mixing of redeclarations inside/outside gl_PerVertex.

From section 7.1 (Built-In Language Variables) of the GLSL 4.10
spec:

    Also, if a built-in interface block is redeclared, no member of
    the built-in declaration can be redeclared outside the block
    redeclaration.

We have been regarding this text as a clarification to the behaviour
established for gl_PerVertex by GLSL 1.50, so we apply it regardless
of GLSL version.

This patch enforces the rule by adding an enum to ir_variable to track
how the variable was declared: implicitly, normally, or in an
interface block.

Fixes piglit tests:
- gs-redeclares-pervertex-out-after-global-redeclaration.geom
- vs-redeclares-pervertex-out-after-global-redeclaration.vert
- gs-redeclares-pervertex-out-after-other-global-redeclaration.geom
- vs-redeclares-pervertex-out-after-other-global-redeclaration.vert
- gs-redeclares-pervertex-out-before-global-redeclaration
- vs-redeclares-pervertex-out-before-global-redeclaration

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
v2: Don't set "how_declared" redundantly in builtin_variables.cpp.
Properly clone "how_declared".

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Enable the AMD_performance_monitor extension on Gen5+.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Take "bookend" OA snapshots at the start/end of each batch.

Unfortunately, our hardware only has one set of aggregating performance
counters shared between all 3D programs, and their values are not saved
or restored by hardware contexts.  Also, at least on Sandybridge and
Ivybridge, the counters lose their values if the GPU goes to sleep.

To work around both of these problems, we have to snapshot the
performance counters at the beginning and end of each batch, similar to
how we handle query objects on platforms that don't support hardware
contexts.  I call these "bookend" snapshots.

Since there can be multiple performance monitors active at a time, we
store the bookend snapshots in a global BO, shared by all monitors.

For monitors that span multiple batches, acquiring results involves
adding up three segments:

   BeginPerfMonitor   --> End of Batch 1    ("head")
   Start of Batch 2   --> End of Batch 2
                      ...                   ("middle")
   Start of Batch N-1 --> End of Batch N-1
   Start of Batch N   --> EndPerfMonitor    ("tail")

Monitors that refer to bookend BO snapshots are considered "unresolved".
We delay resolving them (and adding up deltas to obtain the results) as
long as possible to avoid blocking on mapping monitor->oa_bo.

We can also run out of space in the bookend BO, at which point we have
to resolve all unresolved monitors.  Then we can throw away the
snapshots and begin writing at the beginning of the buffer.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Reserve batchbuffer space for a closing MI_REPORT_PERF_COUNT.

In order to use the Observability Architecture effectively, we'll need
to take snapshots of the OA counters via MI_REPORT_PERF_COUNT at the
start and end of each batch.

Experimentation reveals that we need to flush before and after each
MI_REPORT_PERF_COUNT to get working values.  For simplicitly, I chose to
use intel_batchbuffer_emit_mi_flush(), which unfortunately expands to
triple pipe controls on Sandybridge.

We may want to start computing per-generation reserved batch space to
avoid the insanity of Sandybridge's PIPE_CONTROL cost.  That said, much
of this cost existed before I rewrote the query object support to use
hardware contexts, so it's at least not entirely new.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add some plumbing for gathering OA results.

Currently, this only considers the monitor start and end snapshots.
This is woefully insufficient, but allows me to add a bunch of the
infrastructure now and flesh it out later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Start and stop OA counters as necessary.

We need to start OA at the beginning of each batch where monitors are
active.  OACONTROL isn't part of the hardware context, so to avoid
leaving counters enabled for other applications, we turn them off at the
end of the batch too.

We also need to start them at BeginPerfMonitor time (unless they've
already been started).  We stop them when the monitor last ends as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add functions to start and stop the OA counters.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add #defines for the OACONTROL register and fields.

We'll need to write this register to start/stop performance counters.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Take OA counter snapshots at Begin/EndPerfMonitor time.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add a function to emit the MI_REPORT_PERF_COUNT packet.

MI_REPORT_PERF_COUNT writes a snapshot of the Observability Architecture
counters to a buffer.  Exactly how it works varies between generations:
Ironlake requires two packets, Sandybridge has to use GGTT, and Ivybridge
and later use PPGTT.

v2: Assert that we didn't use more space than we reserved (suggested
    by Eric Anholt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Track the number of monitors that need OA counters.

Using the OA counters requires some per-batch work.  When starting and
ending a batch, it's useful to know whether any monitors are actually
interested in OA data.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Enumerate Observability Architecture counters on Gen5+.

In addition to listing the counter names, we include several "remap"
tables.  Confusingly, counters are documented with names like "A23",
are written to some buffer offset other than 23, and exposed by core
Mesa under a counter ID that is different still.

The first is inevitable; MI_REPORT_PERF_COUNT writes certain counters to
fixed locations in the buffer.  The latter could be avoided, but core
Mesa uses the "Counters" array index as the ID for a counter.  We could
do remapping there, but it would just complicate the core Mesa code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Expose pipeline statistics registers via performance monitors.

This is fairly simple:
- At BeginPerfMonitor time, take an opening snapshot.
- At EndPerfMonitor time, take a closing snapshot.
- The first time the application asks for results, subtract the two and
  store that value.  Then free the BO containing the snapshots.
- On subsequent requests for the results, just return the saved value.
- On reset, throw away the results.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Enumerate the pipeline statistics register counters on Gen6+.

For now, we only support these on Gen6+, since that's what currently
uses hardware contexts.  When we add Ironlake hardware context support,
we can add pipeline statistics register support for that as well.

In theory, we could support pipeline statistics counters even without
hardware contexts, but it would be annoyingly painful.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Initialize performance monitor Groups/NumGroups.

Since we don't support any counters, there are zero groups.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add macros for creating performance monitor counters and groups.

The Observability Architecture counters are 32-bit unsigned values, and
the Pipeline Statistics Register counters are 64-bit unsigned values.

These convenience macros make it easy to create those types of counters.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Periodically dump the list of monitors if INTEL_DEBUG=perfmon.

It's useful to see the state of all outstanding monitors; the start
of a new batch seems like a reasonable time to print them out.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add basic driver hooks and plumbing for AMD_performance_monitor.

These stub functions will be filled out in later patches.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add INTEL_DEBUG=perfmon support.

This will enable debugging printfs for the AMD_performance_monitor code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Move brw_emit_query_begin() to the render ring prelude.

Without hardware contexts, the pipeline statistics registers are
free-running and include data from every 3D application running.

In order to find out the contributions of one particular context, we
need to take a snapshot at the start and end of each batch.

Previously, we emitted the PIPE_CONTROL necessary to capture
PS_DEPTH_COUNT when drawing primitives.  Special tracking ensured it
happened only on the first draw of the batch, rather than on every draw.

Moving this to brw_new_batch increases symmetry, since the final
snapshot has always been in brw_finish_batch, which is just a few lines
below.  It should be basically equivalent.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Introduce a "render ring prelude" hook.

The new intel_batchbuffer_emit_render_ring_prelude() hook will be called
when switching from BLT or UNKNOWN_RING to RENDER_RING.  This provides a
place to emit state that should go at the start of each render ring
batch, with minimal overhead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Introduce an UNKNOWN_RING state.

When we first create a batch buffer, it's empty.  We don't actually
know what ring it will be targeted at until the first BEGIN_BATCH or
BEGIN_BATCH_BLT macro.

Previously, one could determine the state of the batch by checking
brw->batch.ring (blit vs. render) and brw->batch.used != 0 (known vs.
unknown).

This should be functionally equivalent, but the tri-state enum is a bit
clearer.

v2: Catch three explicit require_space callers (thanks to Carl and Eric).
v3: Split the boolean -> enum change from the UNKNOWN_RING change.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Convert brw->batch.is_blit to a BLT_RING/RENDER_RING enum.

Passing BLT_RING or RENDER_RING to batchbuffer functions is a lot more
obvious than passing true or false.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

llvmpipe: calculate more accurate interpolation value at origin

Some rounding errors could crop up when calculating a0. Use a more accurate
method (barycentric interpolation essentially) to fix this, though to fix
the REAL problem (which is that our interpolation will give very bad results
with small triangles far away from the origin when they have steep gradients)
this does absolutely nothing (actually makes it worse). (To fix the real
problem, either would need to use a vertex corner (or some other point inside
the tri) as starting point value instead of fb origin and pass that down to
interpolation, or mimic what hw does, use barycentric interpolation (using
the coordinates extracted from the rasterizer edge functions) - maybe another
time.)
Some (silly) tests though really want a high accuracy at fb origin and don't
care much about anything else (Just. Don't. Ask.).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

svga: remove special-case code for texkil w component

Not actually needed.  Fixes piglit ARB_fragment_program/kil-swizzle test.

Reviewed-by: José Fonseca <jfonseca@vmware.com>

gallium: Make TGSI_SEMANTIC_FOG register four-component wide.

D3D9 Shader Model 2 restricted the fog register to one component,
http://msdn.microsoft.com/en-us/library/windows/desktop/bb172945.aspx ,
but that restriction no longer exists in Shader Model 3, and several
WHCK tests enforce that.

So this change:
- lifts the single-component restriction TGSI_SEMANTIC_FOG
  from Gallium interface
- updates the Mesa state tracker to enforce output fog has (f, 0, 0, 1)
- draw module was updated to leave TGSI_SEMANTIC_FOG output registers
  alone

Several gallium drivers that are going out of their way to clear
TGSI_SEMANTIC_FOG components could be simplified in the future.

Thanks to Si Chen and Michal Krol for identifying the problem.

Testing done: piglit fogcoord-*.vpfp tests

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

tgsi_exec: Fix mask calculation for emit_kill_if.

Same as Si Chen's commit e7a5905d8a3960b0981750f8131e3af9acbfcdb8 for
tgsi_exec module.

Not actually tested, because softpipe is failing the test that caught
this bug due to unrelated issues.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: Use IROUND instead of roundf.

roundf is not available on MSVC.

mesa: enable GL_TEXTURE_LOD_BIAS set/get

Earlier comments suggest this was removed from GL core spec but it is
still there. Enabling makes 'texture_lod_bias_getter' Khronos
conformance tests pass, also removes some errors from Metro Last Light
game which is using this API.

v2: leave NOTE comment (Ian)

Cc: "9.0 9.1 9.2 10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>

winsys/radeon: cleanup virtual memory nonsense

The alignment of a virtual memory area must always be at least 4096 bytes.

It only worked because size was aligned to 4096 outside of the function.

Signed-off-by: Christian König <christian.koenig@amd.com>

mesa: Update MESA_INFO to eliminate error

If a user set MESA_INFO and the OpenGL application uses a
3.0 or later context then the MESA_INFO debug output will have
an error when it queries for extensions using the deprecated
enum GL_EXTENSIONS. Passing context argument allows code
to return extension list directly regardless of profile.
Commit title updated as recommended by Kenneth Graunke.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Disable BLORP on Broadwell for now.

BLORP is essential.  However, porting it to Gen8 is a huge amount of
work.  Disabling it for now allows us to proceed with basic hardware
enablement.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Disable HiZ on Broadwell for now.

HiZ is difficult to implement, and while it's essential for performance,
we don't need it right away for purposes of hardware enabling.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Claim OpenGL 3.3 support on Broadwell.

Bugs aside, basically everything ought to work.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add device info structs for Broadwell.

As always, the chipset limits here are placeholders, rather than the
actual values.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Use more portable bash invocation construct.

Fixes 'make check' on distros where bash is not at /bin/bash.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>

gallivm: Ignore unknown file type in non-debug builds.

Fixes "Uninitialized pointer read" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

glx: don't fail out when no configs if we have visuals

GLX 1.2 servers with no SGIX_fbconfigs exist (some citrix thing),
and we fail glxinfo completely in those cases.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/swrast: fix inverted front buffer rendering with old-school swrast

I've no idea when this broke, but we have some people who wanted it fixed,
so here's my attempt.

reproducer, run readpix with swrast hit f, or run trival tri -sb things are
upside down, after this patch they aren't.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62142
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66213

Cc: <mesa-stable@lists.freedesktop.org>"
Signed-off-by: Dave Airlie <airlied@redhat.com>