microwatt.git
4 years agoMerge pull request #201 from mikey/github-actions
Anton Blanchard [Fri, 12 Jun 2020 00:25:09 +0000 (10:25 +1000)]
Merge pull request #201 from mikey/github-actions

Move from travis to github workflows

4 years agoMove from travis to github workflow
Michael Neuling [Tue, 9 Jun 2020 23:57:15 +0000 (09:57 +1000)]
Move from travis to github workflow

Github workflow gives us longer run times and faster startup.

Major kudos for this goes to @eine for the initial version and for
pushing us in this direction.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years agoMerge pull request #194 from ozbenh/misc
Paul Mackerras [Wed, 10 Jun 2020 09:37:01 +0000 (19:37 +1000)]
Merge pull request #194 from ozbenh/misc

Fix syscon registers usage and add "save" function to mw_debug

4 years agogitignore: Add more exlusions
Benjamin Herrenschmidt [Wed, 10 Jun 2020 03:14:00 +0000 (13:14 +1000)]
gitignore: Add more exlusions

litedram build directory used by the generator and the
verilator obj_dir can be taken out

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Fix DRAM init mem using too many address bits
Benjamin Herrenschmidt [Tue, 9 Jun 2020 22:36:44 +0000 (08:36 +1000)]
litedram: Fix DRAM init mem using too many address bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Remove remnants of riscv-inits
Benjamin Herrenschmidt [Fri, 5 Jun 2020 12:28:30 +0000 (22:28 +1000)]
litedram: Remove remnants of riscv-inits

We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agomw_debug: Add "save" function to save memory to a file
Benjamin Herrenschmidt [Thu, 4 Jun 2020 10:25:57 +0000 (20:25 +1000)]
mw_debug: Add "save" function to save memory to a file

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agosw: Properly mask syscon register fields
Benjamin Herrenschmidt [Thu, 4 Jun 2020 01:56:47 +0000 (11:56 +1000)]
sw: Properly mask syscon register fields

Some fields might get extended with extra bits, use the appropriate
masks when reading the values.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoMerge pull request #196 from ozbenh/makefile-lib-fix
Michael Neuling [Tue, 9 Jun 2020 23:54:35 +0000 (09:54 +1000)]
Merge pull request #196 from ozbenh/makefile-lib-fix

Makefile: Improve unisim library generation

4 years agoMerge pull request #195 from shenki/nexys-video
Michael Neuling [Tue, 9 Jun 2020 23:22:50 +0000 (09:22 +1000)]
Merge pull request #195 from shenki/nexys-video

Nexys video

4 years agoMakefile: Improve unisim library generation
Benjamin Herrenschmidt [Tue, 9 Jun 2020 22:31:49 +0000 (08:31 +1000)]
Makefile: Improve unisim library generation

The rewrite of the Makefile to use "ghdl -c" somewhat broke building
the unisim library as ghdl doesn't yet support putting files in
separate libraries from a single command line invocation.

The workaround at the time was to put the entire project in "unisim"
which is ... weird and will break if we try to add another library
such as fmf.

This fixes it by generating the library separately using "ghdl -i"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoflash-arty: Re-add support for running from any path
Joel Stanley [Tue, 9 Jun 2020 01:52:57 +0000 (11:22 +0930)]
flash-arty: Re-add support for running from any path

The changes in d3c274d01ec1 ("flash-arty: Add support for specifying the file type")
added a local jtagspi.cfg, which meant openocd must be run from the root
of the microwatt directory.

This puts the content into the xilinx-xc7.cfg so the script can be used
from any path again.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years agoflash-arty: Support Nexys Video's a200
Joel Stanley [Tue, 9 Jun 2020 00:42:42 +0000 (10:12 +0930)]
flash-arty: Support Nexys Video's a200

Not an Arty but Anton tests on this board.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years agoMerge pull request #193 from paulusmack/master
Michael Neuling [Fri, 5 Jun 2020 10:17:01 +0000 (20:17 +1000)]
Merge pull request #193 from paulusmack/master

Minor improvements and reformatting

4 years agoMerge pull request #182 from mikey/travis
Paul Mackerras [Fri, 5 Jun 2020 08:02:33 +0000 (18:02 +1000)]
Merge pull request #182 from mikey/travis

Travis and testing improvements

4 years agoicache: Fix icbi potentially clobbering the icache (#192)
Benjamin Herrenschmidt [Fri, 5 Jun 2020 06:23:23 +0000 (16:23 +1000)]
icache: Fix icbi potentially clobbering the icache (#192)

icbi currently just resets the icache. This has some nasty side
effects such as also clearing the TLB, but also the wishbone interface.

That means that any ongoing cycle will be dropped.

However, most of our slaves don't handle that well and will continue
sending acks for already issued requests.

Under some circumstances we can thus restart an icache load and get
spurious ack/data from the wishbone left over from the "cancelled"
sequence.

This has broken booting Linux for me.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agodecode2: Reformat to 4-space indentation
Paul Mackerras [Fri, 5 Jun 2020 01:16:56 +0000 (11:16 +1000)]
decode2: Reformat to 4-space indentation

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agodecode1: Reformat to 4-space indentation
Paul Mackerras [Fri, 5 Jun 2020 01:16:07 +0000 (11:16 +1000)]
decode1: Reformat to 4-space indentation

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agodecode1: Make ld/std and lwa not be single-issue
Paul Mackerras [Mon, 1 Jun 2020 06:42:05 +0000 (16:42 +1000)]
decode1: Make ld/std and lwa not be single-issue

These were missed earlier when the single-issue flag was turned off on
the other loads and stores by commit 1a244d34707a ("Remove single-issue
constraint for most loads and stores").

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agoImprove Travis to run as a matrix job
Michael Neuling [Sat, 23 May 2020 07:00:24 +0000 (17:00 +1000)]
Improve Travis to run as a matrix job

Can now run all 999 random tests and unit tests in Travis.

Kudos for this goes to @eine. Based on his input from here:
  https://github.com/antonblanchard/microwatt/pull/182#issuecomment-637926957

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years agoAdd unit tests to check and check_light
Michael Neuling [Sun, 24 May 2020 02:09:11 +0000 (12:09 +1000)]
Add unit tests to check and check_light

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years agoAdd unit tests make target
Michael Neuling [Sun, 24 May 2020 02:08:47 +0000 (12:08 +1000)]
Add unit tests make target

We don't run these but we should.

The SOC tests have bit rotted. We need to fix them but leave them out
for now.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years agoAdd tests_console make target
Michael Neuling [Sat, 23 May 2020 06:59:51 +0000 (16:59 +1000)]
Add tests_console make target

Will use when splitting out Travis tests later

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years agoMerge pull request #191 from ozbenh/litedram
Paul Mackerras [Fri, 5 Jun 2020 03:16:56 +0000 (13:16 +1000)]
Merge pull request #191 from ozbenh/litedram

Litedram updates with L2 cache and sim support

4 years agolitedram: Make the L2 twice as tall
Benjamin Herrenschmidt [Fri, 5 Jun 2020 01:45:00 +0000 (11:45 +1000)]
litedram: Make the L2 twice as tall

This increases the number of L2 lines from 32 to 64. The BRAM usage is the
same as they were only half used. There's an increase in LUTs and registers
due to the extra tags and valid bits, but none of it should be in a
space constrained or critical timing path.

We could make it wider instead (256 bytes lines) which would reduce usage
instead, but this increases the latency by 8 cycles. Something to consider
once the L2 is capable of early response on miss and starting reloads
from any point in a line.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agocore: Do addpcis using the main adder (#189)
Paul Mackerras [Fri, 5 Jun 2020 01:29:31 +0000 (11:29 +1000)]
core: Do addpcis using the main adder (#189)

By adding logic to decode2 to be able to send the instruction address
down the A input, and making CONST_DX_HI (renamed to CONST_DXHI4) add
4 to the immediate value (easy since the bottom 16 bits were zero),
we can do addpcis using the main adder.  This reduces the width of the
result mux and frees up one value in insn_type_t, since we can now use
OP_ADD for addpcis.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agolitedram: Remove old "VexRiscV" based initializations
Benjamin Herrenschmidt [Fri, 5 Jun 2020 01:15:35 +0000 (11:15 +1000)]
litedram: Remove old "VexRiscV" based initializations

Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoMerge pull request #183 from shawnanastasio/addpcis
Paul Mackerras [Fri, 5 Jun 2020 00:54:00 +0000 (10:54 +1000)]
Merge pull request #183 from shawnanastasio/addpcis

Add support for the addpcis instruction

4 years agolitedram: Update to latest LiteX/LiteDRAM version
Benjamin Herrenschmidt [Mon, 1 Jun 2020 13:58:47 +0000 (23:58 +1000)]
litedram: Update to latest LiteX/LiteDRAM version

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Test bench
Benjamin Herrenschmidt [Mon, 1 Jun 2020 22:32:17 +0000 (08:32 +1000)]
litedram: Test bench

The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.

Includes a litedram update to be able to operate the sim model without
inits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Add an L2 cache with store queue
Benjamin Herrenschmidt [Wed, 27 May 2020 01:06:51 +0000 (11:06 +1000)]
litedram: Add an L2 cache with store queue

This adds a cache between the wishbone and litedram with the following
features (at this point, it's still evolving)

  - 128 bytes line width in order to have a reasonable amount of
litedram pipelining on the 128-bit wide data port.

  - Configurable geometry otherwise

  - Stores are acked immediately on wishbone whether hit or miss
(minus a 2 cycles delay if there's a previous load response in the
way) and sent to LiteDRAM via 8 entries (configurable) store queue

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Add support for booting without BRAM
Benjamin Herrenschmidt [Mon, 25 May 2020 10:20:59 +0000 (20:20 +1000)]
litedram: Add support for booting without BRAM

This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Add simulation support
Benjamin Herrenschmidt [Fri, 22 May 2020 08:43:50 +0000 (18:43 +1000)]
litedram: Add simulation support

This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoMerge pull request #185 from ozbenh/misc
Paul Mackerras [Thu, 4 Jun 2020 23:29:24 +0000 (09:29 +1000)]
Merge pull request #185 from ozbenh/misc

Small fixes to mw_debug, bin2hex and improve BRAM generation in dcache

4 years agoMerge pull request #188 from ozbenh/openocd-tweaks
Michael Neuling [Thu, 4 Jun 2020 22:38:18 +0000 (08:38 +1000)]
Merge pull request #188 from ozbenh/openocd-tweaks

Openocd tweaks

4 years agoflash-arty: Add support for specifying the file type
Benjamin Herrenschmidt [Thu, 4 Jun 2020 13:29:29 +0000 (23:29 +1000)]
flash-arty: Add support for specifying the file type

By default openocd tries to "guess" the file type and interpret
it accordingly. For example it will detect an ELF file based on
the presence of an ELF header and will try to load the relevant
segments into the flash.

This may not be what we want. For example, I want to load the raw
ELF file into the flash.

Additionally the ELF parser in most distro's OpenOCD version
only supports ELF32 and will error out.

This adds a "-t" argument to flash-arty to allow us to specify the
file format. For example "-t bin" will treat the file as raw binary.

Unfortunately I had to copy and modify jtagspi.cfg from OpenOCD
to achieve this.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoflash-arty: Support hex values for address
Benjamin Herrenschmidt [Thu, 4 Jun 2020 13:13:45 +0000 (23:13 +1000)]
flash-arty: Support hex values for address

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoMerge pull request #168 from shenki/flash-arty
Paul Mackerras [Wed, 3 Jun 2020 04:20:02 +0000 (14:20 +1000)]
Merge pull request #168 from shenki/flash-arty

Scripts to write data to the Arty's SPI flash

4 years agodcache: Rework RAM wrapper to synthetize better on Xilinx
Benjamin Herrenschmidt [Mon, 25 May 2020 06:48:47 +0000 (16:48 +1000)]
dcache: Rework RAM wrapper to synthetize better on Xilinx

The global wr_en signal is causing Vivado to generate two TDP (True Dual Port)
block RAMs instead of one SDP (Simple Dual Port) for each cache way. Remove
it and instead apply a AND to the individual byte write enables.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agobin2hex: Make sure to generate little endian files
Benjamin Herrenschmidt [Mon, 1 Jun 2020 08:24:15 +0000 (18:24 +1000)]
bin2hex: Make sure to generate little endian files

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agomw_debug: Fix memory overflow with "sim" backend
Benjamin Herrenschmidt [Thu, 28 May 2020 14:04:46 +0000 (00:04 +1000)]
mw_debug: Fix memory overflow with "sim" backend

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoMerge pull request #178 from antonblanchard/intercon
Anton Blanchard [Tue, 2 Jun 2020 01:54:00 +0000 (11:54 +1000)]
Merge pull request #178 from antonblanchard/intercon

Interconnect timing improvements from Ben

4 years agoMerge pull request #184 from antonblanchard/verific
Anton Blanchard [Tue, 2 Jun 2020 00:36:06 +0000 (10:36 +1000)]
Merge pull request #184 from antonblanchard/verific

Delete old verific script

4 years agoDelete bit rotted verific script
Michael Neuling [Tue, 26 May 2020 06:55:20 +0000 (16:55 +1000)]
Delete bit rotted verific script

We can use ghdl-synth and fusesoc now, so verific is a dead path which
has bit rotted.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years agoAdd a new misc test suite with addpcis tests
Shawn Anastasio [Tue, 26 May 2020 01:08:59 +0000 (20:08 -0500)]
Add a new misc test suite with addpcis tests

The two tests obtain NIA with bl+mflr+addi and then compare it
against addpcis with the minimum and maximum immediate operand values.

They were also tested on a real POWER9 system (in userspace) for good
measure.

Signed-off-by: Shawn Anastasio <shawn@anastas.io>
4 years agoImplement the addpcis instruction
Shawn Anastasio [Tue, 26 May 2020 01:03:02 +0000 (20:03 -0500)]
Implement the addpcis instruction

This commit adds support for the addpcis instruction from ISA 3.0.

A new input_reg_b_t type, CONST_DX_HI, was added to support the
shifted immediate value used in DX-Form instructions.

Signed-off-by: Shawn Anastasio <shawn@anastas.io>
4 years agolitedram: Split the init memory from the main wrapper
Benjamin Herrenschmidt [Wed, 20 May 2020 11:00:27 +0000 (21:00 +1000)]
litedram: Split the init memory from the main wrapper

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoirq: Simplify xics->core irq input
Benjamin Herrenschmidt [Sun, 17 May 2020 05:04:23 +0000 (15:04 +1000)]
irq: Simplify xics->core irq input

Use a simple wire. common.vhdl types are better kept for things
local to the core. We can add more wires later if we need to for
HV irqs etc...

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agosoc: Rework interconnect
Benjamin Herrenschmidt [Mon, 11 May 2020 11:22:07 +0000 (21:22 +1000)]
soc: Rework interconnect

This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.

The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.

This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agosw: Add full memory map to .h and use it for litedram .lds
Benjamin Herrenschmidt [Fri, 15 May 2020 07:43:51 +0000 (17:43 +1000)]
sw: Add full memory map to .h and use it for litedram .lds

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoMerge pull request #181 from antonblanchard/Makefile-rework-2
Anton Blanchard [Sat, 23 May 2020 06:50:12 +0000 (16:50 +1000)]
Merge pull request #181 from antonblanchard/Makefile-rework-2

Pass clock frequency to UART sim wrapper

4 years agoPass clock frequency to UART sim wrapper
Anton Blanchard [Sat, 23 May 2020 03:46:43 +0000 (13:46 +1000)]
Pass clock frequency to UART sim wrapper

The UART sim wrapper is currently hard wired to 50 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #180 from antonblanchard/Makefile-rework
Anton Blanchard [Thu, 21 May 2020 02:29:55 +0000 (12:29 +1000)]
Merge pull request #180 from antonblanchard/Makefile-rework

Makefile rework

4 years agoA little less shouting in the Makefile
Anton Blanchard [Wed, 20 May 2020 06:27:06 +0000 (16:27 +1000)]
A little less shouting in the Makefile

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoFix the simulated DMI
Anton Blanchard [Wed, 20 May 2020 06:18:58 +0000 (16:18 +1000)]
Fix the simulated DMI

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoExit cleanly from testbench on success
Anton Blanchard [Wed, 20 May 2020 06:07:13 +0000 (16:07 +1000)]
Exit cleanly from testbench on success

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge Makefile and Makefile.synth
Anton Blanchard [Wed, 20 May 2020 05:37:49 +0000 (15:37 +1000)]
Merge Makefile and Makefile.synth

We still need to a way to our FPGA target on the command line, but this
at least gets us down to a common Makefile.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoAdd Makefile command line variables to enable docker and podman
Anton Blanchard [Wed, 20 May 2020 05:01:42 +0000 (15:01 +1000)]
Add Makefile command line variables to enable docker and podman

Instead of having to edit the Makefile, we can now do:

make DOCKER=1
make PODMAN=1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoRework Makefile
Anton Blanchard [Wed, 20 May 2020 04:29:50 +0000 (14:29 +1000)]
Rework Makefile

Instead of building each file one by one (and having to track all
the dependencies manually), use the ghdl -c command that does
analysis and elaboration in one go.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #179 from antonblanchard/yosys-verilator
Anton Blanchard [Tue, 19 May 2020 05:53:54 +0000 (15:53 +1000)]
Merge pull request #179 from antonblanchard/yosys-verilator

Add yosys/verilator support

4 years agoImprove make clean
Anton Blanchard [Tue, 19 May 2020 05:32:04 +0000 (15:32 +1000)]
Improve make clean

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoAdd yosys/verilator support
Anton Blanchard [Tue, 19 May 2020 05:18:42 +0000 (15:18 +1000)]
Add yosys/verilator support

Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #171 from shenki/mw-debug-features
Anton Blanchard [Tue, 19 May 2020 04:27:42 +0000 (14:27 +1000)]
Merge pull request #171 from shenki/mw-debug-features

mw debug features

4 years agoMerge pull request #173 from Jbalkind/core-vcs-syntax
Anton Blanchard [Tue, 19 May 2020 04:04:19 +0000 (14:04 +1000)]
Merge pull request #173 from Jbalkind/core-vcs-syntax

Changing use of others in core files to satisfy VCS

4 years agomw_debug: Add README
Joel Stanley [Mon, 11 May 2020 04:22:41 +0000 (13:52 +0930)]
mw_debug: Add README

This describes how to build the tool on Fedora, and on Debian which lacks a packaged
liburjtag as of mid 2020.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years agomw_debug: Add usage text
Joel Stanley [Sun, 10 May 2020 04:00:26 +0000 (13:30 +0930)]
mw_debug: Add usage text

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years agomw_debug: Add CFLAGS and fix warnings
Joel Stanley [Mon, 11 May 2020 03:52:00 +0000 (13:22 +0930)]
mw_debug: Add CFLAGS and fix warnings

CFLAGS was defined but not used anywhere. This adds them to the compile
line, and fixes the warnings (and errors!) that result.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years agoMerge pull request #177 from antonblanchard/litedram
Anton Blanchard [Tue, 19 May 2020 03:32:33 +0000 (13:32 +1000)]
Merge pull request #177 from antonblanchard/litedram

LiteDRAM fixes from Ben

4 years agoMerge branch 'master' into litedram
Anton Blanchard [Tue, 19 May 2020 02:28:02 +0000 (12:28 +1000)]
Merge branch 'master' into litedram

4 years agoMerge pull request #176 from antonblanchard/console-improv
Anton Blanchard [Tue, 19 May 2020 01:53:34 +0000 (11:53 +1000)]
Merge pull request #176 from antonblanchard/console-improv

Console improvements from Ben

4 years agoMerge pull request #175 from antonblanchard/yosys-fixes-2
Anton Blanchard [Tue, 19 May 2020 01:38:16 +0000 (11:38 +1000)]
Merge pull request #175 from antonblanchard/yosys-fixes-2

Fix yosys build after MMU merge

4 years agoChanges for compilation with VCS:
Jonathan Balkind [Thu, 14 May 2020 21:17:15 +0000 (17:17 -0400)]
Changes for compilation with VCS:
- Changing use of others in core files to satisfy VCS
- Adding workaround for VCS subtype constraint inconsistencies in common.vhdl

Signed-off-by: Jonathan Balkind <jbalkind@princeton.edu>
4 years agoFix yosys build after MMU merge
Anton Blanchard [Tue, 19 May 2020 01:22:29 +0000 (11:22 +1000)]
Fix yosys build after MMU merge

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #174 from antonblanchard/yosys-fixes
Anton Blanchard [Tue, 19 May 2020 00:44:04 +0000 (10:44 +1000)]
Merge pull request #174 from antonblanchard/yosys-fixes

Some yosys fixes

4 years agoSome yosys fixes
Anton Blanchard [Mon, 18 May 2020 00:15:03 +0000 (10:15 +1000)]
Some yosys fixes

This gets the yosys build further along, but I'm now chasing what looks
like a yosys bug.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years agoMerge pull request #169 from paulusmack/mmu
Anton Blanchard [Mon, 18 May 2020 23:34:41 +0000 (09:34 +1000)]
Merge pull request #169 from paulusmack/mmu

Add radix MMU with dTLB and iTLB

4 years agolitedram: Regenerate
Benjamin Herrenschmidt [Fri, 15 May 2020 03:31:11 +0000 (13:31 +1000)]
litedram: Regenerate

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agosoc/core: Add reset latches
Benjamin Herrenschmidt [Fri, 15 May 2020 03:30:01 +0000 (13:30 +1000)]
soc/core: Add reset latches

This adds one-cycle latches to the various resets out of the soc and
into the various core modules. It *seems* to help vivado P&R a bit
and has shown to avoid timing violations under some circumstances.

Interestingly those resets never seem to appear in the bad timing
path. It looks like those long resets simply impose placement
constraints that Vivado satisfies at the expense of timing elsewhere.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoarty/nexys: Rework reset with litedram
Benjamin Herrenschmidt [Fri, 15 May 2020 03:20:27 +0000 (13:20 +1000)]
arty/nexys: Rework reset with litedram

When using litedram, request a much longer PLL reset. This seems to
help get rid of all the grabled output after config.

Also use the clean system_rst out of litedram as our source of reset
for the rest of the SoC (it is synchronized with system_clk and takes
pll_locked into account already)

4 years agosoc_reset: Use counters, add synchronizers
Benjamin Herrenschmidt [Fri, 15 May 2020 03:15:48 +0000 (13:15 +1000)]
soc_reset: Use counters, add synchronizers

In some cases we need to keep the reset held for much longer,
so use counters rather than shift registers.

Additionally, some signals such as ext_rst and pll_locked
or signals going from the ext_clk domain to the pll_clk
domain need to be treated as async, and testing them without
synchronizers is asking for trouble.

Finally, make the external reset also reset the PLL.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Forward system reset signal
Benjamin Herrenschmidt [Fri, 15 May 2020 03:11:58 +0000 (13:11 +1000)]
litedram: Forward system reset signal

The wrapper wouldn't forward it. Make it do so

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Remove init delays
Benjamin Herrenschmidt [Fri, 15 May 2020 00:14:53 +0000 (10:14 +1000)]
litedram: Remove init delays

The clocks / resets are now stable

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Update to new LiteX/LiteDRAM version
Benjamin Herrenschmidt [Tue, 12 May 2020 10:27:15 +0000 (20:27 +1000)]
litedram: Update to new LiteX/LiteDRAM version

Things have changed a bit in upstream LiteX. LiteDRAM now exposes a
wishbone for the CSRs for example.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agodcache: Fix bug in store hit after dcbz case
Paul Mackerras [Fri, 15 May 2020 12:01:02 +0000 (22:01 +1000)]
dcache: Fix bug in store hit after dcbz case

This fixes a bug where a store that hits in the dcache immediately
following a dcbz has its write to the cache RAM suppressed (but not
its write to memory).  If a load to the same location comes along
before the cache line gets replaced, the load will return incorrect
data.

Fixes: 4db1676ef8b3 ("dcache: Don't assert on dcbz cache hit")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agopp_soc_uart: Fix rx synchronizers and ensure stable tx init state
Benjamin Herrenschmidt [Thu, 14 May 2020 04:26:14 +0000 (14:26 +1000)]
pp_soc_uart: Fix rx synchronizers and ensure stable tx init state

The rx synchronizers were ... non existent. Someone forgot to add
a if rising_edge(clk) to the process.

For tx, ensure that we have a default value so that TX stays high
from TPGA configuration to the reset being sampled on the first clock
cycle.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agopp_fifo: Fix full fifo losing all data on simultaneous push & pop
Benjamin Herrenschmidt [Thu, 14 May 2020 02:30:11 +0000 (12:30 +1000)]
pp_fifo: Fix full fifo losing all data on simultaneous push & pop

The pp_fifo decides whether top = bottom means empty or full based
on whether the previous operation was a push or a pop.

If the fifo performs both in one cycle, it sets the previous op to
pop. That means that a full fifo being added a character and removed
one at the same time becomes empty.

Instead, just leave the previous op alone. If the fifo was empty, it
remains so, if it was full ditto.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoMakefile: Improve clean a bit
Benjamin Herrenschmidt [Thu, 14 May 2020 00:12:44 +0000 (10:12 +1000)]
Makefile: Improve clean a bit

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoconsole: Remove putstr()
Benjamin Herrenschmidt [Thu, 14 May 2020 02:03:39 +0000 (12:03 +1000)]
console: Remove putstr()

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoconsole: Move console files
Benjamin Herrenschmidt [Thu, 14 May 2020 00:08:06 +0000 (10:08 +1000)]
console: Move console files

console.c goes to a new lib/ where we'll store other general utilities
and console.h goes to include/

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoconsole: Replace putstr with puts
Benjamin Herrenschmidt [Thu, 14 May 2020 02:03:01 +0000 (12:03 +1000)]
console: Replace putstr with puts

It makes things a bit more standard and a bit nicer to read
without all those strlen(). Also console.c takes care of adding
the carriage returns before the linefeeds.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoconsole: Improve putchar(), add puts()
Benjamin Herrenschmidt [Thu, 14 May 2020 00:09:36 +0000 (10:09 +1000)]
console: Improve putchar(), add puts()

Make putchar() match a standard prototype and add puts()

Also make puts() add carriage returns before linefeeds so the
users don't have to do it all over the place.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agosoc: Work around compile error with ghdl 0.37-dev
Paul Mackerras [Thu, 14 May 2020 05:43:33 +0000 (15:43 +1000)]
soc: Work around compile error with ghdl 0.37-dev

The ghdl packaged in Fedora 31 doesn't like a port map of the form
"rst => rst or core_reset", so this works around the problem by
doing the OR in a separate statement.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agoMerge branch 'mmu'
Paul Mackerras [Thu, 14 May 2020 05:41:51 +0000 (15:41 +1000)]
Merge branch 'mmu'

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years agoMerge pull request #170 from antonblanchard/litedram
Anton Blanchard [Thu, 14 May 2020 05:08:33 +0000 (15:08 +1000)]
Merge pull request #170 from antonblanchard/litedram

LiteDRAM integration

4 years agoAdd script for writing to flash on arty
Joel Stanley [Wed, 6 May 2020 02:20:17 +0000 (11:50 +0930)]
Add script for writing to flash on arty

You must have openocd 0.10.0 installed.

$ ./openocd/flash-arty ~/microwatt-fusesoc/build/microwatt_0/arty_a7-35-vivado/microwatt_0.bit
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
adapter speed: 25000 kHz
fpga_program
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 25000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
loaded file microwatt/openocd/bscan_spi_xc7a35t.bit to pld device 0 in 0s 136459us
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
Info : Found flash device 'micron n25q128' (ID 0x0018ba20)
flash 'jtagspi' found at 0x00000000
auto erase enabled
Info : Found flash device 'micron n25q128' (ID 0x0018ba20)
Info : Found flash device 'micron n25q128' (ID 0x0018ba20)
Info : Found flash device 'micron n25q128' (ID 0x0018ba20)
Info : sector 0 took 241 ms
Info : sector 1 took 242 ms
Info : sector 2 took 241 ms
Info : sector 3 took 247 ms
Info : sector 4 took 253 ms
Info : sector 5 took 244 ms
Info : sector 6 took 246 ms
Info : sector 7 took 237 ms
Info : sector 8 took 258 ms
Info : sector 9 took 260 ms
Info : sector 10 took 262 ms
Info : sector 11 took 253 ms
Info : sector 12 took 256 ms
Info : sector 13 took 255 ms
wrote 917504 bytes from file microwatt-fusesoc/build/microwatt_0/arty_a7-35-vivado/microwatt_0.bit in 9.642746s (92.920 KiB/s)
Info : Found flash device 'micron n25q128' (ID 0x0018ba20)
read 907483 bytes from file microwatt-fusesoc/build/microwatt_0/arty_a7-35-vivado/microwatt_0.bit and flash bank 0 at offset 0x00000000 in 0.557387s (1589.944 KiB/s)
contents match

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years agolitedram: Use 32-bit CSR bus
Benjamin Herrenschmidt [Sat, 9 May 2020 01:20:59 +0000 (11:20 +1000)]
litedram: Use 32-bit CSR bus

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Add support for Microwatt-initialized controller
Benjamin Herrenschmidt [Fri, 8 May 2020 15:09:26 +0000 (01:09 +1000)]
litedram: Add support for Microwatt-initialized controller

This adds support for initializing the memory controller from microwatt
rather than using a built-in RiscV processor. This might require some
fixes to LiteX and LiteDRAM (they haven't been merged as of this commit
yet).

This is enabled in the shipped generated files and can be changed via
modifying the generator script to pass False to "mw_init"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agohello_world: Use new headers and frequency from syscon
Benjamin Herrenschmidt [Fri, 8 May 2020 00:42:01 +0000 (10:42 +1000)]
hello_world: Use new headers and frequency from syscon

This uses the new header files for register definitions and
extracts the core frequency from syscon rather than hard coding it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agolitedram: Improve sdram init boot messages
Benjamin Herrenschmidt [Tue, 24 Sep 2019 06:19:29 +0000 (16:19 +1000)]
litedram: Improve sdram init boot messages

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years agoAdd microwatt_soc.h and io.h include file
Benjamin Herrenschmidt [Fri, 8 May 2020 00:27:33 +0000 (10:27 +1000)]
Add microwatt_soc.h and io.h include file

This contains C definitions for various Microwatt internal MMIOs
and a set of accessors.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>