openpower-isa.git
3 years agofixedarith: switch maddld to XLEN
Dmitry Selyutin [Tue, 24 Aug 2021 11:49:14 +0000 (11:49 +0000)]
fixedarith: switch maddld to XLEN

3 years agofixedarith: switch maddhdu to XLEN
Dmitry Selyutin [Tue, 24 Aug 2021 11:48:17 +0000 (11:48 +0000)]
fixedarith: switch maddhdu to XLEN

3 years agoadd short mulli random test
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 16:24:56 +0000 (17:24 +0100)]
add short mulli random test

3 years agofixedarith: switch mulli to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 09:06:13 +0000 (09:06 +0000)]
fixedarith: switch mulli to XLEN

3 years agofixedarith: switch mulhdu to XLEN
Dmitry Selyutin [Tue, 24 Aug 2021 11:41:45 +0000 (11:41 +0000)]
fixedarith: switch mulhdu to XLEN

3 years agoadd mulhdu random test
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 16:12:58 +0000 (17:12 +0100)]
add mulhdu random test

3 years agofixedarith: switch mulhd to XLEN
Dmitry Selyutin [Tue, 24 Aug 2021 11:41:02 +0000 (11:41 +0000)]
fixedarith: switch mulhd to XLEN

3 years agofixedarith: switch mulldX to XLEN
Dmitry Selyutin [Mon, 23 Aug 2021 19:51:28 +0000 (19:51 +0000)]
fixedarith: switch mulldX to XLEN

3 years agofixedarith: switch mulhwu to XLEN
Dmitry Selyutin [Mon, 23 Aug 2021 18:56:30 +0000 (18:56 +0000)]
fixedarith: switch mulhwu to XLEN

3 years agofixedarith: switch mullwX to XLEN
Dmitry Selyutin [Mon, 23 Aug 2021 18:55:01 +0000 (18:55 +0000)]
fixedarith: switch mullwX to XLEN

3 years agoquite a big intrusive change in auto-assignment
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 15:03:07 +0000 (16:03 +0100)]
quite a big intrusive change in auto-assignment
variables that do not exist get auto-created based on the bit-width
at which they are first encountered

    prod[0:31]

creates a variable with

    prod = concat(0, repeat=32)

however this needs to be more complicated rather than just assume
it is a pair of constants

expressions can now be

     prod[0:XLEN-1]

which gets an ast.BinOp expression created on the RHS.

therefore allow the assignment "var = concat(...., repeat=xxxx)"
to accept computed expressions by returning an ast.BinOp(UPPER, "-", LOWER)
so that the resultant python code performs the subtract calculation

3 years agoassignment test pattern-matching not adequate, adding quick test
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 14:39:12 +0000 (15:39 +0100)]
assignment test pattern-matching not adequate, adding quick test

3 years agofixedarith: switch mulhw to XLEN
Dmitry Selyutin [Mon, 23 Aug 2021 18:51:30 +0000 (18:51 +0000)]
fixedarith: switch mulhw to XLEN

3 years agofixedlogical: switch bpermd to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 15:10:48 +0000 (15:10 +0000)]
fixedlogical: switch bpermd to XLEN

3 years agofixedlogical: switch cntlzd to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 15:08:31 +0000 (15:08 +0000)]
fixedlogical: switch cntlzd to XLEN

3 years agofixedlogical: switch popcntd to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 15:07:56 +0000 (15:07 +0000)]
fixedlogical: switch popcntd to XLEN

3 years agofixedlogical: switch extsw to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 15:04:38 +0000 (15:04 +0000)]
fixedlogical: switch extsw to XLEN

3 years agofixedlogical: switch prtyw to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 15:03:59 +0000 (15:03 +0000)]
fixedlogical: switch prtyw to XLEN

3 years agofixedlogical: switch prtyd to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 15:02:14 +0000 (15:02 +0000)]
fixedlogical: switch prtyd to XLEN

3 years agofixedlogical: switch popcntb to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 14:51:11 +0000 (14:51 +0000)]
fixedlogical: switch popcntb to XLEN

3 years agofixedlogical: switch cmpb to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 13:05:42 +0000 (13:05 +0000)]
fixedlogical: switch cmpb to XLEN

3 years agofixedlogical: switch cntlzwX to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 13:03:29 +0000 (13:03 +0000)]
fixedlogical: switch cntlzwX to XLEN

3 years agofix RANGE function, reverse direction needed
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 12:50:21 +0000 (13:50 +0100)]
fix RANGE function, reverse direction needed

3 years agofixedlogical: switch xori to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 13:00:03 +0000 (13:00 +0000)]
fixedlogical: switch xori to XLEN

3 years agofixedlogical: switch xoris to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 12:59:42 +0000 (12:59 +0000)]
fixedlogical: switch xoris to XLEN

3 years agofixedlogical: switch oris to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 12:59:01 +0000 (12:59 +0000)]
fixedlogical: switch oris to XLEN

3 years agofixedlogical: switch andis. to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 12:58:37 +0000 (12:58 +0000)]
fixedlogical: switch andis. to XLEN

3 years agofixedlogical: switch ori to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 12:57:41 +0000 (12:57 +0000)]
fixedlogical: switch ori to XLEN

3 years agoalso add pattern-recognition for just
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 12:05:59 +0000 (13:05 +0100)]
also add pattern-recognition for just

     [0] * XLEN

have to keep a close eye on this

3 years agofix pattern-match for an expression such as "XLEN-16" when looking
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 12:03:53 +0000 (13:03 +0100)]
fix pattern-match for an expression such as "XLEN-16" when looking
for concat substitutions

[item] * NUMBER was replaced with
concat(item, repeat=NUMBER)

but [item] * (XLEN-16) was not matching

by adding a HACK which spots ast.Binop then [item]*(XLEN-16) can be
recognised

3 years agomissed data_o/i to i/o_data conversion
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 11:36:29 +0000 (12:36 +0100)]
missed data_o/i to i/o_data conversion

3 years agofixedlogical: switch andi. to XLEN
Dmitry Selyutin [Wed, 25 Aug 2021 12:57:18 +0000 (12:57 +0000)]
fixedlogical: switch andi. to XLEN

3 years agopywriter: support RANGE helper
Dmitry Selyutin [Wed, 25 Aug 2021 14:44:23 +0000 (14:44 +0000)]
pywriter: support RANGE helper

3 years agoparser: support unary minus properly
Dmitry Selyutin [Sun, 22 Aug 2021 19:19:00 +0000 (19:19 +0000)]
parser: support unary minus properly

3 years agolexer: t_NUMBER should not grab minus sign
Dmitry Selyutin [Sun, 22 Aug 2021 18:27:09 +0000 (18:27 +0000)]
lexer: t_NUMBER should not grab minus sign

3 years agoadd another quick test to pseudo parser
Luke Kenneth Casson Leighton [Sun, 22 Aug 2021 19:49:01 +0000 (20:49 +0100)]
add another quick test to pseudo parser

3 years agoset XLEN=64 in ISACaller
Luke Kenneth Casson Leighton [Sat, 21 Aug 2021 11:52:13 +0000 (12:52 +0100)]
set XLEN=64 in ISACaller

3 years agotest_caller_bcd: make bit changes more VHDL-like
Dmitry Selyutin [Thu, 19 Aug 2021 17:50:17 +0000 (17:50 +0000)]
test_caller_bcd: make bit changes more VHDL-like

3 years agotest_caller_bcd: fix and refactor addg6s test loop
Dmitry Selyutin [Thu, 19 Aug 2021 17:30:42 +0000 (17:30 +0000)]
test_caller_bcd: fix and refactor addg6s test loop

3 years agotest_caller_bcd: drop dead code
Dmitry Selyutin [Thu, 19 Aug 2021 16:09:58 +0000 (16:09 +0000)]
test_caller_bcd: drop dead code

3 years agotest_caller_bcd: mention reference implementation
Dmitry Selyutin [Thu, 19 Aug 2021 15:46:06 +0000 (15:46 +0000)]
test_caller_bcd: mention reference implementation

3 years agotest_caller_bcd: refactor addg6s test
Dmitry Selyutin [Thu, 19 Aug 2021 15:40:32 +0000 (15:40 +0000)]
test_caller_bcd: refactor addg6s test

This patch should vastly simplify and speed up the addg6s test. Most
importantly, we drop half adders and full adders, making use of the
fact that Python uses big integers directly. Also, we don't bother
generating all posible products of BCD numbers; instead, we simply
resort to random number generator. Note, however, that we only check
the numbers that are correct from BCD point of view.

3 years agowhitespace, below 80 char limit
Luke Kenneth Casson Leighton [Thu, 19 Aug 2021 16:52:20 +0000 (17:52 +0100)]
whitespace, below 80 char limit

3 years agotest_caller_bcd: mark addg6s test as slowpoke
Dmitry Selyutin [Wed, 18 Aug 2021 20:03:01 +0000 (20:03 +0000)]
test_caller_bcd: mark addg6s test as slowpoke

3 years agotest_caller_bcd: addg6s sketch
Dmitry Selyutin [Wed, 18 Aug 2021 19:57:47 +0000 (19:57 +0000)]
test_caller_bcd: addg6s sketch

3 years agotest_caller_bcd: align tables with spec and cases
Dmitry Selyutin [Tue, 17 Aug 2021 19:04:22 +0000 (19:04 +0000)]
test_caller_bcd: align tables with spec and cases

3 years agotest_caller_bcd: drop temporary code
Dmitry Selyutin [Tue, 17 Aug 2021 19:03:15 +0000 (19:03 +0000)]
test_caller_bcd: drop temporary code

3 years agobring qemu sim size down to 1GB
Luke Kenneth Casson Leighton [Mon, 16 Aug 2021 19:52:56 +0000 (20:52 +0100)]
bring qemu sim size down to 1GB

3 years agoadd subTest back in to bcd tst
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 22:07:28 +0000 (23:07 +0100)]
add subTest back in to bcd tst

3 years agowhitespace (keep below 80 chars)
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 21:59:35 +0000 (22:59 +0100)]
whitespace (keep below 80 chars)

3 years agowhitespace (below 80 chars)
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 21:56:26 +0000 (22:56 +0100)]
whitespace (below 80 chars)

3 years agotake copy of GPR/FPR inputs into ISACaller
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 21:53:52 +0000 (22:53 +0100)]
take copy of GPR/FPR inputs into ISACaller

3 years agoallow constructor of SelectableInt to pass in (and copy)
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 21:52:58 +0000 (22:52 +0100)]
allow constructor of SelectableInt to pass in (and copy)
another SelectableInt

3 years agotest_caller_bcd: basic batch mode support
Dmitry Selyutin [Sun, 15 Aug 2021 18:01:23 +0000 (18:01 +0000)]
test_caller_bcd: basic batch mode support

3 years agono python files to be committed in isafunctions
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 18:14:28 +0000 (19:14 +0100)]
no python files to be committed in isafunctions

3 years agoadd a quick logic test of astor tree-dump
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 17:46:51 +0000 (18:46 +0100)]
add a quick logic test of astor tree-dump

3 years agosv.bc test jumping to wrong location (offset 0xc not 0x8)
Luke Kenneth Casson Leighton [Sun, 15 Aug 2021 16:05:16 +0000 (17:05 +0100)]
sv.bc test jumping to wrong location (offset 0xc not 0x8)
fix sv.bc/all test, and sv.bc pseudocode, to early-exit if one CR test
fails, but also not branch just because *one* test succeeds.

3 years agocreate an end loop condition which tells the sv.bc pseudocode
Luke Kenneth Casson Leighton [Sat, 14 Aug 2021 17:27:03 +0000 (18:27 +0100)]
create an end loop condition which tells the sv.bc pseudocode
that it is on the last src/dststep loop

3 years agoend loop condition in svp64 bc pseudo-code
Luke Kenneth Casson Leighton [Sat, 14 Aug 2021 17:09:35 +0000 (18:09 +0100)]
end loop condition in svp64 bc pseudo-code

3 years agofix test_caller_svp64.py, particularly indexed LD/ST,
Luke Kenneth Casson Leighton [Sat, 14 Aug 2021 10:53:30 +0000 (11:53 +0100)]
fix test_caller_svp64.py, particularly indexed LD/ST,
vector reg numbers have to be aligned to multiple of 4

3 years agomessy resolution of sv.bc testing, early-out detection.
Luke Kenneth Casson Leighton [Sat, 14 Aug 2021 10:43:46 +0000 (11:43 +0100)]
messy resolution of sv.bc testing, early-out detection.

3 years agoadd TODO comments for BCD test speedup
Luke Kenneth Casson Leighton [Thu, 12 Aug 2021 14:20:34 +0000 (15:20 +0100)]
add TODO comments for BCD test speedup

3 years agoadd ctr_ok and cond_ok to namespace to be able
Luke Kenneth Casson Leighton [Thu, 12 Aug 2021 14:20:20 +0000 (15:20 +0100)]
add ctr_ok and cond_ok to namespace to be able
to detect if the branch took place or not

3 years agouse subTest in BCD test
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 19:48:14 +0000 (20:48 +0100)]
use subTest in BCD test

3 years agoget new ISATestCaller set up with correct function params
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 19:44:56 +0000 (20:44 +0100)]
get new ISATestCaller set up with correct function params

3 years agomake only one PowerDecoder2, share it with
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 19:43:54 +0000 (20:43 +0100)]
make only one PowerDecoder2, share it with
multiple tests

3 years agowhoops test for sv.bc* matched accidentally, use explicit test
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 16:28:53 +0000 (17:28 +0100)]
whoops test for sv.bc* matched accidentally, use explicit test
"svremap" and "svstate" instead

3 years agoredirect sv.bc to new svbranch in ISACaller
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 16:15:39 +0000 (17:15 +0100)]
redirect sv.bc to new svbranch in ISACaller
add missing fields needed for sv.bc

3 years agocorrections to SVP64 Branch Conditional
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 16:00:28 +0000 (17:00 +0100)]
corrections to SVP64 Branch Conditional
add special extra fields for sv.bc* in ISACaller namespace

3 years agorename TestRunner class to ISATestRunner
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 09:15:35 +0000 (10:15 +0100)]
rename TestRunner class to ISATestRunner

3 years agoadd (untested) TestRunner based on soc test_runner.py
Luke Kenneth Casson Leighton [Wed, 11 Aug 2021 09:11:31 +0000 (10:11 +0100)]
add (untested) TestRunner based on soc test_runner.py

3 years agotest_caller_bcd: cdtbcd
Dmitry Selyutin [Wed, 11 Aug 2021 07:36:33 +0000 (07:36 +0000)]
test_caller_bcd: cdtbcd

3 years agotest_caller_bcd: cbcdtd test
Dmitry Selyutin [Tue, 10 Aug 2021 20:39:48 +0000 (20:39 +0000)]
test_caller_bcd: cbcdtd test

3 years agopywriter: move BCD/DPD routines to header
Dmitry Selyutin [Tue, 10 Aug 2021 19:15:19 +0000 (19:15 +0000)]
pywriter: move BCD/DPD routines to header

3 years agoadd dct butterfly SVG autogenerator
Luke Kenneth Casson Leighton [Tue, 10 Aug 2021 17:15:26 +0000 (18:15 +0100)]
add dct butterfly SVG autogenerator

3 years agocorrections to SVP64 Branch RM Mode decoding
Luke Kenneth Casson Leighton [Tue, 10 Aug 2021 11:42:41 +0000 (12:42 +0100)]
corrections to SVP64 Branch RM Mode decoding

3 years agowhoops, test of SV.bc in wrong place
Luke Kenneth Casson Leighton [Sun, 8 Aug 2021 21:10:59 +0000 (22:10 +0100)]
whoops, test of SV.bc in wrong place

3 years agoadd start of SVP64ASM encoder for sv.bc and sv.bclr
Luke Kenneth Casson Leighton [Sun, 8 Aug 2021 21:06:45 +0000 (22:06 +0100)]
add start of SVP64ASM encoder for sv.bc and sv.bclr
TODO, sv.bca, sv.bclrl etc.

3 years agoadd bc and bclr to sv_analysis
Luke Kenneth Casson Leighton [Sun, 8 Aug 2021 14:55:50 +0000 (15:55 +0100)]
add bc and bclr to sv_analysis

3 years agoadd SVP64 Branch-Conditional decoding
Luke Kenneth Casson Leighton [Sun, 8 Aug 2021 12:30:14 +0000 (13:30 +0100)]
add SVP64 Branch-Conditional decoding

3 years agoadding some testing of fragment-printing into PowerDecoder
Luke Kenneth Casson Leighton [Sun, 8 Aug 2021 12:29:39 +0000 (13:29 +0100)]
adding some testing of fragment-printing into PowerDecoder

3 years agoremove SVP64 Branch format modifications (achieve a different way)
Luke Kenneth Casson Leighton [Sat, 7 Aug 2021 00:51:09 +0000 (01:51 +0100)]
remove SVP64 Branch format modifications (achieve a different way)

3 years agostart adding Branch-Conditional decoding to SVP64RMModeDecode
Luke Kenneth Casson Leighton [Thu, 5 Aug 2021 10:52:03 +0000 (11:52 +0100)]
start adding Branch-Conditional decoding to SVP64RMModeDecode

3 years agoadd SVP64 Branch-Conditional equivalent of Rc fields
Luke Kenneth Casson Leighton [Thu, 5 Aug 2021 10:37:50 +0000 (11:37 +0100)]
add SVP64 Branch-Conditional equivalent of Rc fields

3 years agoadd inverse DCT in-place unit test with bit-reversed half-swap LD
Luke Kenneth Casson Leighton [Mon, 2 Aug 2021 19:16:57 +0000 (20:16 +0100)]
add inverse DCT in-place unit test with bit-reversed half-swap LD

3 years agobit of a big update, remove all bit-reversed LD operations, replace with
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:37:45 +0000 (18:37 +0100)]
bit of a big update, remove all bit-reversed LD operations, replace with
LD-with-shift, and fix LDST, DCT and FFT unit tests to use new
bitrev-with-half-swap REMAP modes

3 years agoadd BCD operations to SVP64
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:36:49 +0000 (18:36 +0100)]
add BCD operations to SVP64

3 years agorename lw*br to lw*sh
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 15:04:03 +0000 (16:04 +0100)]
rename lw*br to lw*sh

3 years agoadd LD-half-swap for i-DCT which does not work. redesign needed
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 09:30:53 +0000 (10:30 +0100)]
add LD-half-swap for i-DCT which does not work. redesign needed

3 years agopywriter: BCD helpers
Dmitry Selyutin [Sat, 31 Jul 2021 19:14:49 +0000 (19:14 +0000)]
pywriter: BCD helpers

3 years agoisa/bcd: DPD_TO_BCD helper
Dmitry Selyutin [Sat, 31 Jul 2021 18:57:36 +0000 (18:57 +0000)]
isa/bcd: DPD_TO_BCD helper

3 years agoisa/bcd: BCD_TO_DPD helper
Dmitry Selyutin [Sat, 31 Jul 2021 18:56:16 +0000 (18:56 +0000)]
isa/bcd: BCD_TO_DPD helper

3 years agoremove hand-created DOUBLE function, now it is replaced with pseudocode
Luke Kenneth Casson Leighton [Sat, 31 Jul 2021 19:02:28 +0000 (20:02 +0100)]
remove hand-created DOUBLE function, now it is replaced with pseudocode
compiled version

3 years agoreplace DOUBLE function from helpers.py with pseudocode variant
Luke Kenneth Casson Leighton [Sat, 31 Jul 2021 18:48:46 +0000 (19:48 +0100)]
replace DOUBLE function from helpers.py with pseudocode variant

3 years agoadd SINGLE function to double2single, to replace manually-created version
Luke Kenneth Casson Leighton [Sat, 31 Jul 2021 18:38:07 +0000 (19:38 +0100)]
add SINGLE function to double2single, to replace manually-created version

3 years agowhoops, no ability to add comments in between functions in pseudocode
Luke Kenneth Casson Leighton [Sat, 31 Jul 2021 18:37:48 +0000 (19:37 +0100)]
whoops, no ability to add comments in between functions in pseudocode

3 years agoadd outer-inner RADIX2 iDCT unit test.
Luke Kenneth Casson Leighton [Sat, 31 Jul 2021 16:27:20 +0000 (17:27 +0100)]
add outer-inner RADIX2 iDCT unit test.
use FFT twin +/- MUL-ADD-SUB rather than the DCT +/- MUL-ADD-SUB

3 years agoisa/bcd.mdwn: fix incorrect declaration
Dmitry Selyutin [Sat, 31 Jul 2021 13:48:08 +0000 (13:48 +0000)]
isa/bcd.mdwn: fix incorrect declaration

In pseudocode used in our markdown files, dc[16] does not mean that
we declare a variable of 16 bits; it only means that we access bit
16 of variable dc. Details:

https://bugs.libre-soc.org/show_bug.cgi?id=656#c15

3 years agoadd SVP64 i-DCT unit test for inner butterfly, coefficients pre-computed
Luke Kenneth Casson Leighton [Sat, 31 Jul 2021 13:28:25 +0000 (14:28 +0100)]
add SVP64 i-DCT unit test for inner butterfly, coefficients pre-computed
at present

3 years agoadd i-DCT SVP64 unit test for outer butterfly
Luke Kenneth Casson Leighton [Sat, 31 Jul 2021 13:19:46 +0000 (14:19 +0100)]
add i-DCT SVP64 unit test for outer butterfly