gcc.git
6 years ago[AArch64] Implement usadv16qi and ssadv16qi standard names
Kyrylo Tkachov [Mon, 21 May 2018 11:21:07 +0000 (11:21 +0000)]
[AArch64] Implement usadv16qi and ssadv16qi standard names

This patch implements the usadv16qi and ssadv16qi standard names.
See the thread at on gcc@gcc.gnu.org [1] for background.

The V16QImode variant is important to get right as it is the most commonly used pattern:
reducing vectors of bytes into an int.
The midend expects the optab to compute the absolute differences of operands 1 and 2 and
reduce them while widening along the way up to SImode. So the inputs are V16QImode and
the output is V4SImode.

I've tried out a few different strategies for that, the one I settled with is to emit:
UABDL2    tmp.8h, op1.16b, op2.16b
UABAL    tmp.8h, op1.16b, op2.16b
UADALP    op3.4s, tmp.8h

To work through the semantics let's say operands 1 and 2 are:
op1 { a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15 }
op2 { b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15 }
op3 { c0, c1, c2, c3 }

The UABDL2 takes the upper V8QI elements, computes their absolute differences, widens them and stores them into the V8HImode tmp:

tmp { ABS(a[8]-b[8]), ABS(a[9]-b[9]), ABS(a[10]-b[10]), ABS(a[11]-b[11]), ABS(a[12]-b[12]), ABS(a[13]-b[13]), ABS(a[14]-b[14]), ABS(a[15]-b[15]) }

The UABAL after that takes the lower V8QI elements, computes their absolute differences, widens them and accumulates them into the V8HImode tmp from the previous step:

tmp { ABS(a[8]-b[8])+ABS (a[0]-b[0]), ABS(a[9]-b[9])+ABS(a[1]-b[1]), ABS(a[10]-b[10])+ABS(a[2]-b[2]), ABS(a[11]-b[11])+ABS(a[3]-b[3]), ABS(a[12]-b[12])+ABS(a[4]-b[4]), ABS(a[13]-b[13])+ABS(a[5]-b[5]), ABS(a[14]-b[14])+ABS(a[6]-b[6]), ABS(a[15]-b[15])+ABS(a[7]-b[7]) }

Finally the UADALP does a pairwise widening reduction and accumulation into the V4SImode op3:
op3 { c0+ABS(a[8]-b[8])+ABS(a[0]-b[0])+ABS(a[9]-b[9])+ABS(a[1]-b[1]), c1+ABS(a[10]-b[10])+ABS(a[2]-b[2])+ABS(a[11]-b[11])+ABS(a[3]-b[3]), c2+ABS(a[12]-b[12])+ABS(a[4]-b[4])+ABS(a[13]-b[13])+ABS(a[5]-b[5]), c3+ABS(a[14]-b[14])+ABS(a[6]-b[6])+ABS(a[15]-b[15])+ABS(a[7]-b[7]) }

(sorry for the text dump)

Remember, according to [1] the exact reduction sequence doesn't matter (for integer arithmetic at least).
I've considered other sequences as well (thanks Wilco), for example
* UABD + UADDLP + UADALP
* UABLD2 + UABDL + UADALP + UADALP

I ended up settling in the sequence in this patch as it's short (3 instructions) and in the future we can potentially
look to optimise multiple occurrences of these into something even faster (for example accumulating into H registers for longer
before doing a single UADALP in the end to accumulate into the final S register).

If your microarchitecture has some some strong preferences for a particular sequence, please let me know or, even better, propose a patch
to parametrise the generation sequence by code (or the appropriate RTX cost).

This expansion allows the vectoriser to avoid unpacking the bytes in two steps and performing V4SI arithmetic on them.
So, for the code:

unsigned char pix1[N], pix2[N];

int foo (void)
{
  int i_sum = 0;
  int i;

  for (i = 0; i < 16; i++)
    i_sum += __builtin_abs (pix1[i] - pix2[i]);

  return i_sum;
}

we now generate on aarch64:
foo:
        adrp    x1, pix1
        add     x1, x1, :lo12:pix1
        movi    v0.4s, 0
        adrp    x0, pix2
        add     x0, x0, :lo12:pix2
        ldr     q2, [x1]
        ldr     q3, [x0]
        uabdl2  v1.8h, v2.16b, v3.16b
        uabal   v1.8h, v2.8b, v3.8b
        uadalp  v0.4s, v1.8h
        addv    s0, v0.4s
        umov    w0, v0.s[0]
        ret

instead of:
foo:
        adrp    x1, pix1
        adrp    x0, pix2
        add     x1, x1, :lo12:pix1
        add     x0, x0, :lo12:pix2
        ldr     q0, [x1]
        ldr     q4, [x0]
        ushll   v1.8h, v0.8b, 0
        ushll2  v0.8h, v0.16b, 0
        ushll   v2.8h, v4.8b, 0
        ushll2  v4.8h, v4.16b, 0
        usubl   v3.4s, v1.4h, v2.4h
        usubl2  v1.4s, v1.8h, v2.8h
        usubl   v2.4s, v0.4h, v4.4h
        usubl2  v0.4s, v0.8h, v4.8h
        abs     v3.4s, v3.4s
        abs     v1.4s, v1.4s
        abs     v2.4s, v2.4s
        abs     v0.4s, v0.4s
        add     v1.4s, v3.4s, v1.4s
        add     v1.4s, v2.4s, v1.4s
        add     v0.4s, v0.4s, v1.4s
        addv    s0, v0.4s
        umov    w0, v0.s[0]
        ret

So I expect this new expansion to be better than the status quo in any case.
Bootstrapped and tested on aarch64-none-linux-gnu.
This gives about 8% on 525.x264_r from SPEC2017 on a Cortex-A72.

* config/aarch64/aarch64.md ("unspec"): Define UNSPEC_SABAL,
UNSPEC_SABDL2, UNSPEC_SADALP, UNSPEC_UABAL, UNSPEC_UABDL2,
UNSPEC_UADALP values.
* config/aarch64/iterators.md (ABAL): New int iterator.
(ABDL2): Likewise.
(ADALP): Likewise.
(sur): Add mappings for the above.
* config/aarch64/aarch64-simd.md (aarch64_<sur>abdl2<mode>_3):
New define_insn.
(aarch64_<sur>abal<mode>_4): Likewise.
(aarch64_<sur>adalp<mode>_3): Likewise.
(<sur>sadv16qi): New define_expand.

* gcc.c-torture/execute/ssad-run.c: New test.
* gcc.c-torture/execute/usad-run.c: Likewise.
* gcc.target/aarch64/ssadv16qi.c: Likewise.
* gcc.target/aarch64/usadv16qi.c: Likewise.

From-SVN: r260437

6 years agoi386.md (*movsf_internal): AVX falsedep fix.
Alexander Nesterovskiy [Mon, 21 May 2018 11:14:14 +0000 (11:14 +0000)]
i386.md (*movsf_internal): AVX falsedep fix.

2018-05-21  Alexander Nesterovskiy  <alexander.nesterovskiy@intel.com>

gcc/
        * config/i386/i386.md (*movsf_internal): AVX falsedep fix.
        (*movdf_internal): Ditto.
        (*rcpsf2_sse): Ditto.
        (*rsqrtsf2_sse): Ditto.
        (*sqrt<mode>2_sse): Ditto.

From-SVN: r260436

6 years agoAdd missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a
Tamar Christina [Mon, 21 May 2018 10:33:30 +0000 (10:33 +0000)]
Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a

This patch adds the missing neon intrinsics for all 128 bit vector Integer modes for the
three-way XOR and negate and xor instructions for Arm8.2-a to Armv8.4-a.

gcc/
2018-05-21  Tamar Christina  <tamar.christina@arm.com>

* config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to
eor3q<mode>4.
(aarch64_bcaxqv8hi): Change to bcaxq<mode>4.
* config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32,
veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
vbcaxq_s64): New.
* config/aarch64/arm_neon.h: Likewise.
* config/aarch64/iterators.md (VQ_I): New.

gcc/testsuite/
2018-05-21  Tamar Christina  <tamar.christina@arm.com>

* gcc.target/gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32,
veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
vbcaxq_s64): New.
* gcc.target/gcc.target/aarch64/sha3_1.c: Likewise.
* gcc.target/gcc.target/aarch64/sha3_1.c: Likewise.
* gcc.target/gcc.target/aarch64/sha3_1.c: Likewise.

From-SVN: r260435

6 years ago[ARC] Add multilib support for linux targets
Alexey Brodkin [Mon, 21 May 2018 09:56:57 +0000 (09:56 +0000)]
[ARC] Add multilib support for linux targets

We used to build baremetal (AKA Elf32) multilibbed toolchains for years
now but never made that for Linux targets since there were problems with
uClibc n multilib setup. Now with help of Crosstool-NG it is finally
possible to create uClibc-based multilibbed toolchains and so we add
relevant CPUs for multilib in case of configuration for "arc*-*-linux*".

This will be essentially useful for glibc-based multilibbbed toolchains
in the future.

gcc/
2018-05-16  Alexey Brodkin <abrodkin@synopsys.com>

        * config.gcc: Add arc/t-multilib-linux to tmake_file for
        arc*-*-linux*.
        * config/arc/t-multilib-linux: Specify MULTILIB_OPTIONS and
        MULTILIB_DIRNAMES

From-SVN: r260434

6 years agore PR fortran/85841 ([F2018] reject deleted features)
Janus Weil [Mon, 21 May 2018 06:45:55 +0000 (08:45 +0200)]
re PR fortran/85841 ([F2018] reject deleted features)

2018-05-21  Janus Weil  <janus@gcc.gnu.org>

PR fortran/85841
* libgfortran.h: New macros GFC_STD_OPT_*.
* error.c (notify_std_msg): New function.
(gfc_notify_std): Adjust such that it can handle combinations of
GFC_STD_* flags in the 'std' argument, not just a single one.
* match.c (match_arithmetic_if, gfc_match_if): Reject arithmetic if
in Fortran 2018.
(gfc_match_stopcode): Use GFC_STD_OPT_* macros.
* options.c (set_default_std_flags): Warn for F2018 deleted features
by default.
(gfc_handle_option): F2018 deleted features are allowed in earlier
standards.
* symbol.c (gfc_define_st_label, gfc_reference_st_label): Reject
nonblock do constructs in Fortran 2018.

2018-05-21  Janus Weil  <janus@gcc.gnu.org>

PR fortran/85841
* gfortran.dg/g77/19990826-3.f: Add option "-std=legacy".
* gfortran.dg/g77/20020307-1.f: Ditto.
* gfortran.dg/g77/980310-3.f: Ditto.
* gfortran.dg/goacc/loop-1-2.f95: Ditto.
* gfortran.dg/goacc/loop-1.f95: Ditto.
* gfortran.dg/gomp/appendix-a/a.6.1.f90: Ditto.
* gfortran.dg/gomp/appendix-a/a.6.2.f90: Ditto.
* gfortran.dg/gomp/do-1.f90: Ditto.
* gfortran.dg/gomp/omp_do1.f90: Ditto.
* gfortran.dg/pr17229.f: Ditto.
* gfortran.dg/pr37243.f: Ditto.
* gfortran.dg/pr49721-1.f: Ditto.
* gfortran.dg/pr58484.f: Ditto.
* gfortran.dg/pr81175.f: Ditto.
* gfortran.dg/pr81723.f: Ditto.
* gfortran.dg/predcom-2.f: Ditto.
* gfortran.dg/vect/Ofast-pr50414.f90: Ditto.
* gfortran.dg/vect/cost-model-pr34445a.f: Ditto.
* gfortran.dg/vect/fast-math-mgrid-resid.f: Ditto.
* gfortran.dg/vect/pr52580.f: Ditto.

From-SVN: r260433

6 years agoPR libstdc++/85843 - warning in logic_error copy constructor.
Jason Merrill [Mon, 21 May 2018 03:53:00 +0000 (23:53 -0400)]
PR libstdc++/85843 - warning in logic_error copy constructor.

* class.c (type_has_user_nondefault_constructor): Check for a
user-provided ctor, not user-declared.

From-SVN: r260432

6 years agoDaily bump.
GCC Administrator [Mon, 21 May 2018 00:16:44 +0000 (00:16 +0000)]
Daily bump.

From-SVN: r260431

6 years agoPR libstdc++/85843 fix "should be explicitly initialized" warnings
Jonathan Wakely [Sun, 20 May 2018 23:50:08 +0000 (00:50 +0100)]
PR libstdc++/85843 fix "should be explicitly initialized" warnings

PR libstdc++/85843
* src/c++11/cow-stdexcept.cc (logic_error, runtime_error): Explicitly
initialize base class to avoid warnings.

From-SVN: r260427

6 years ago[NDS32] Set call address constraint.
Chung-Ju Wu [Sun, 20 May 2018 16:03:45 +0000 (16:03 +0000)]
[NDS32] Set call address constraint.

gcc/
* config/nds32/constraints.md (S): New constraint.
* config/nds32/nds32.md (call_internal): Use constraint S.
(call_value_internal): Likewise.
(sibcall_internal): Likewise.
(sibcall_value_internal): Likewise.

From-SVN: r260422

6 years agore PR fortran/82275 (gfortran rejects valid & accepts invalid reference to dimension...
Paul Thomas [Sun, 20 May 2018 10:54:24 +0000 (10:54 +0000)]
re PR fortran/82275 (gfortran rejects valid & accepts invalid reference to dimension-remapped type SELECT TYPE selector)

2018-05-20  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/82275
Correcting ChangeLogs
* match.c (gfc_match_type_spec): Go through the array ref and
decrement 'rank' for every dimension that is an element.

2018-05-20  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/82275
Correcting ChangeLogs
* gfortran.dg/select_type_42.f90: New test.

From-SVN: r260416

6 years agore PR fortran/80657 (Loop in character function declaration)
Paul Thomas [Sun, 20 May 2018 10:08:24 +0000 (10:08 +0000)]
re PR fortran/80657 (Loop in character function declaration)

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/80657
* resolve.c (flag_fn_result_spec): Use the 'sym' argument to
test for self refs to the function result in the character len
expression. If a self reference is found, emit an error and
return true.
(resolve_fntype): Use the function symbol in the calls to the
above.

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/80657
* gfortran.dg/char_result_18.f90: New test.

From-SVN: r260415

6 years agore PR fortran/49636 ([F03] ASSOCIATE construct confused with slightly complicated...
Paul Thomas [Sun, 20 May 2018 10:04:46 +0000 (10:04 +0000)]
re PR fortran/49636 ([F03] ASSOCIATE construct confused with slightly complicated case)

2018-05-20  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/49636
* trans-array.c (gfc_get_array_span): Renamed from
'get_array_span'.
(gfc_conv_expr_descriptor): Change references to above.
* trans-array.h : Add prototype for 'gfc_get_array_span'.
* trans-stmt.c (trans_associate_var): If the associate name is
a subref array pointer, use gfc_get_array_span for the span.

2018-05-20  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/49636
* gfortran.dg/associate_38.f90: New test.

From-SVN: r260414

6 years agore PR fortran/82923 (Automatic allocation of deferred length character using function...
Paul Thomas [Sun, 20 May 2018 09:59:54 +0000 (09:59 +0000)]
re PR fortran/82923 (Automatic allocation of deferred length character using function result)

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/82923
PR fortran/66694
PR fortran/82617
* trans-array.c (gfc_alloc_allocatable_for_assignment): Set the
charlen backend_decl of the rhs expr to ss->info->string_length
so that the value in the current scope is used.

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/82923
* gfortran.dg/allocate_assumed_charlen_4.f90: New test. Note
that the patch fixes PR66694 & PR82617, although the testcases
are not explicitly included.

From-SVN: r260413

6 years ago[NDS32] Adjust register move cost for graywolf cpu.
Kito Cheng [Sun, 20 May 2018 07:31:55 +0000 (07:31 +0000)]
[NDS32] Adjust register move cost for graywolf cpu.

gcc/
* config/nds32/nds32.c (nds32_register_move_cost): Take garywolf cpu
into consideration.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>
From-SVN: r260412

6 years ago[NDS32] Rewrite cost model.
Kito Cheng [Sun, 20 May 2018 07:23:39 +0000 (07:23 +0000)]
[NDS32] Rewrite cost model.

gcc/
* config/nds32/nds32-cost.c (rtx_cost_model_t): New structure.
(insn_size_16bit, insn_size_32bit): New variables for cost evaluation.
(nds32_rtx_costs_impl): Simplify.
(nds32_address_cost_impl): Simplify.
(nds32_init_rtx_costs): New function.
(nds32_rtx_costs_speed_prefer): Likewise.
(nds32_rtx_costs_size_prefer): Likewise.
(nds32_address_cost_speed_prefer): Likewise.
(nds32_address_cost_speed_fwprop): Likewise.
(nds32_address_cost_size_prefer): Likewise.
* config/nds32/nds32-protos.h (nds32_init_rtx_costs): Declare.
* config/nds32/nds32.c (nds32_option_override): Use
nds32_init_rtx_costs function.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>
From-SVN: r260411

6 years ago[NDS32] Fix date in gcc/ChangeLog file.
Chung-Ju Wu [Sun, 20 May 2018 07:09:09 +0000 (07:09 +0000)]
[NDS32] Fix date in gcc/ChangeLog file.

From-SVN: r260410

6 years ago[NDS32] Print pipeline model in asm header.
Chung-Ju Wu [Sun, 20 May 2018 05:09:49 +0000 (05:09 +0000)]
[NDS32] Print pipeline model in asm header.

gcc/
* config/nds32/nds32.c (nds32_asm_file_start): Output pipeline model.
* config/nds32/nds32.h (TARGET_PIPELINE_N7): Define.
(TARGET_PIPELINE_N8): Likewise.
(TARGET_PIPELINE_N10): Likewise.
(TARGET_PIPELINE_N13): Likewise.
(TARGET_PIPELINE_GRAYWOLF): Likewise.

From-SVN: r260409

6 years agoDaily bump.
GCC Administrator [Sun, 20 May 2018 00:16:37 +0000 (00:16 +0000)]
Daily bump.

From-SVN: r260408

6 years agoAvoid ICE on unsupported use of __integer_pack.
Jason Merrill [Sat, 19 May 2018 22:57:53 +0000 (18:57 -0400)]
Avoid ICE on unsupported use of __integer_pack.

* pt.c (tsubst_pack_expansion): Sorry rather than abort
on __integer_pack as subexpression of pattern.

From-SVN: r260404

6 years ago[NDS32] Update copyright year in nds32-fpu.md.
Monk Chiang [Sat, 19 May 2018 15:23:45 +0000 (15:23 +0000)]
[NDS32] Update copyright year in nds32-fpu.md.

gcc/
* config/nds32/nds32-fpu.md: Update copyright year.

From-SVN: r260402

6 years ago[NDS32] Adjust ASM spec.
Chung-Ju Wu [Sat, 19 May 2018 15:16:53 +0000 (15:16 +0000)]
[NDS32] Adjust ASM spec.

gcc/
* config/nds32/nds32.h (ASM_SPEC): Adjust spec rule.

From-SVN: r260401

6 years ago[NDS32] New option -minline-asm-r15.
Chung-Ju Wu [Sat, 19 May 2018 15:10:08 +0000 (15:10 +0000)]
[NDS32] New option -minline-asm-r15.

gcc/
* config/nds32/nds32.c
(nds32_md_asm_adjust): Consider flag_inline_asm_r15 variable.
* config/nds32/nds32.opt (minline-asm-r15): New option.

From-SVN: r260400

6 years ago[NDS32] Add abssi2 pattern.
Chung-Ju Wu [Sat, 19 May 2018 14:51:09 +0000 (14:51 +0000)]
[NDS32] Add abssi2 pattern.

gcc/
* common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add
MASK_HW_ABS.
* config/nds32/nds32.md (abssi2): New pattern.

From-SVN: r260398

6 years agoi386.md (rex64namesuffix): New mode attribute.
Uros Bizjak [Sat, 19 May 2018 13:43:06 +0000 (15:43 +0200)]
i386.md (rex64namesuffix): New mode attribute.

* config/i386/i386.md (rex64namesuffix): New mode attribute.
* config/i386/sse.md (sse_cvtsi2ss<rex64namesuffix><round_name>):
Merge insn pattern from sse_cvtsi2ss<round_name> and
sse_cvtsi2ssq<round_name> using SWI48 mode iterator.
(sse_cvtss2si<rex64namesuffix><round_name>): Merge insn pattern
from sse_cvtss2si<round_name> and sse_cvtss2siq<round_name>
using SWI48 mode iterator.
(sse_cvtss2si<rex64namesuffix>_2): Merge insn pattern from
sse_cvtss2si_2 and sse_cvtss2siq_2 using SWI48 mode iterator.
(sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Merge insn
pattern from sse_cvttss2si<round_saeonly_name>
and sse_cvttss2siq<round_saeonly_name> using SWI48 mode iterator.
(avx512f_vcvtss2usi<rex64namesuffix><round_name>): Merge insn pattern
from avx512f_vcvtss2usi<round_name> and avx512f_vcvtss2usiq<round_name>
using SWI48 mode iterator.
(avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>): Merge
insn pattern from avx512f_vcvttss2usi<round_saeonly_name> and
avx512f_vcvttss2usiq<round_saeonly_name> using SWI48 mode iterator.
(avx512f_vcvtsd2usi<rex64namesuffix><round_name>): Merge insn pattern
from avx512f_vcvtsd2usi<round_name> and avx512f_vcvtsd2usiq<round_name>
using SWI48 mode iterator.
(avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>): Merge
insn pattern from avx512f_vcvttsd2usi<round_saeonly_name> and
avx512f_vcvttsd2usiq<round_saeonly_name> using SWI48 mode iterator.
(sse2_cvtsd2si<rex64namesuffix><round_name>): Merge insn pattern from
sse2_cvtsd2si<round_name> and sse2_cvtsd2siq<round_name> using
SWI48 mode iterator.
(sse2_cvtsd2si<rex64namesuffix>_2): Merge insn pattern from
sse2_cvtsd2si_2 and sse2_cvtsd2siq_2 using SWI48 mode iterator.
(sse_cvttsd2si<rex64namesuffix><round_saeonly_name>): Merge insn
pattern from sse_cvttsd2si<round_saeonly_name>
and sse_cvttsd2siq<round_saeonly_name> using SWI48 mode iterator.

From-SVN: r260397

6 years ago[NDS32] Refine functions that deal with lwm and smw operations.
Chung-Ju Wu [Sat, 19 May 2018 12:01:11 +0000 (12:01 +0000)]
[NDS32] Refine functions that deal with lwm and smw operations.

gcc/
* config/nds32/nds32-md-auxiliary.c
(nds32_valid_smw_lwm_base_p): Refine.
(nds32_output_smw_single_word): Refine.
(nds32_output_smw_double_word): New.
* config/nds32/nds32-protos.h (nds32_output_smw_double_word): New.

From-SVN: r260396

6 years ago[NDS32] Refine nds32-md-auxiliary.c.
Chung-Ju Wu [Sat, 19 May 2018 11:31:53 +0000 (11:31 +0000)]
[NDS32] Refine nds32-md-auxiliary.c.

gcc/
* config/nds32/nds32-md-auxiliary.c (nds32_output_stack_push): Refine.
(nds32_output_stack_pop): Refine.
(nds32_expand_unaligned_load): Refine.
(nds32_expand_unaligned_store): Refine.

From-SVN: r260394

6 years ago[NDS32] Support PIC and TLS.
Kuan-Lin Chen [Sat, 19 May 2018 11:03:20 +0000 (11:03 +0000)]
[NDS32] Support PIC and TLS.

gcc/
* config/nds32/constants.md: Add TP_REGNUM constant.
(unspec_element): Add UNSPEC_GOTINIT, UNSPEC_GOT, UNSPEC_GOTOFF,
UNSPEC_PLT, UNSPEC_TLSGD, UNSPEC_TLSLD, UNSPEC_TLSIE, UNSPEC_TLSLE and
UNSPEC_ADD32.
* config/nds32/nds32-doubleword.md: Consider flag_pic.
* config/nds32/nds32-dspext.md (mov<mode>): Expand TLS and PIC cases.
* config/nds32/nds32-predicates.c (nds32_const_unspec_p): New.
* config/nds32/nds32-md-auxiliary.c: Implementation that support TLS
and PIC code generation.
* config/nds32/nds32-protos.h: Declarations that support TLS and PIC
code generation.
* config/nds32/nds32-relax-opt.c: Consider TLS and PIC for relax
optimization.
* config/nds32/nds32.md: Support TLS and PIC.
* config/nds32/nds32.c: Support TLS and PIC.
* config/nds32/nds32.h (nds32_relax_insn_type): New enum type.
* config/nds32/predicates.md (nds32_nonunspec_symbolic_operand): New
predicate.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>
From-SVN: r260393

6 years agore PR fortran/82923 (Automatic allocation of deferred length character using function...
Paul Thomas [Sat, 19 May 2018 10:49:50 +0000 (10:49 +0000)]
re PR fortran/82923 (Automatic allocation of deferred length character using function result)

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/82923
PR fortran/66694
PR fortran/82617
* trans-array.c (gfc_alloc_allocatable_for_assignment): Set the
charlen backend_decl of the rhs expr to ss->info->string_length
so that the value in the current scope is used.

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/82923
* gfortran.dg/allocate_assumed_charlen_4.f90: New test. Note
that the patch fixes PR66694 & PR82617, although the testcases
are not explicitly included.

From-SVN: r260392

6 years ago[NDS32] Use machine mode with E_ prefix.
Chung-Ju Wu [Sat, 19 May 2018 10:18:23 +0000 (10:18 +0000)]
[NDS32] Use machine mode with E_ prefix.

gcc/
* config/nds32/nds32-predicates.c (const_vector_to_hwint): Use machine
mode with E_ prefix.

From-SVN: r260391

6 years ago[NDS32] Implment indirect funciton call attribute.
Kuan-Lin Chen [Sat, 19 May 2018 08:57:57 +0000 (08:57 +0000)]
[NDS32] Implment indirect funciton call attribute.

* config/nds32/constants.md (unspec_element): Add UNSPEC_ICT.
* config/nds32/nds32-md-auxiliary.c
(symbolic_reference_mentioned_p): New.
(nds32_legitimize_ict_address): New.
(nds32_expand_ict_move): New.
(nds32_indirect_call_referenced_p): New.
(nds32_symbol_binds_local_p): Delete.
(nds32_long_call_p): Modify.
* config/nds32/nds32-opts.h (nds32_ict_model_type): New enum type.
* config/nds32/nds32-protos.h
(symbolic_reference_mentioned_p): Declare.
(nds32_legitimize_ict_address): Declare.
(nds32_expand_ict_move): Declare.
(nds32_indirect_call_referenced_p): Declare.
* config/nds32/nds32-relax-opt.c (nds32_ict_const_p): New.
(nds32_relax_group): Use nds32_ict_const_p as condition.
* config/nds32/nds32.c (nds32_attribute_table): Add "indirect_call".
(nds32_asm_file_start): Output ict_model directive in asm code.
(nds32_legitimate_address_p): Consider indirect call.
(nds32_print_operand): Consider indirect call.
(nds32_print_operand_address): Consider indirect call.
(nds32_insert_attributes): Handle "indirect_call" attribute.
(TARGET_LEGITIMATE_ADDRESS_P): Define.
(TARGET_LEGITIMATE_CONSTANT_P): Define.
(TARGET_CANNOT_FORCE_CONST_MEM): Define.
(TARGET_DELEGITIMIZE_ADDRESS): Define.
(TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA): Define.
* config/nds32/nds32.h (SYMBOLIC_CONST_P): Define.
(TARGET_ICT_MODEL_SMALL): Define.
(TARGET_ICT_MODEL_LARGE): Define.
* config/nds32/nds32.md (movsi): Consider ict model.
(call, call_value): Consider ict model.
(sibcall, sibcall_value): Consider ict model.
* config/nds32/nds32.opt (mict-model): New option.
* config/nds32/predicates.md (nds32_symbolic_operand): Consider ict
model.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>
From-SVN: r260390

6 years agoFix std::codecvt_utf8<wchar_t> for Mingw
Jonathan Wakely [Sat, 19 May 2018 02:03:42 +0000 (03:03 +0100)]
Fix std::codecvt_utf8<wchar_t> for Mingw

* src/c++11/codecvt.cc (__codecvt_utf8_base<wchar_t>::do_in)
[__SIZEOF_WCHAR_T__==2 && __BYTE_ORDER__!=__ORDER_BIG_ENDIAN__]: Set
little_endian element in bitmask.
* testsuite/22_locale/codecvt/codecvt_utf8/69703.cc: Run all tests.
* testsuite/22_locale/codecvt/codecvt_utf8/wchar_t/1.cc: New.

From-SVN: r260389

6 years agoDaily bump.
GCC Administrator [Sat, 19 May 2018 00:16:47 +0000 (00:16 +0000)]
Daily bump.

From-SVN: r260388

6 years agoRISC-V: Add RV32E support.
Kito Cheng [Fri, 18 May 2018 22:53:55 +0000 (22:53 +0000)]
RISC-V: Add RV32E support.

Kito Cheng <kito.cheng@gmail.com>
Monk Chiang  <sh.chiang04@gmail.com>

gcc/
* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
Add support to parse rv32e*.  Clear MASK_RVE for rv32i and rv64i.
* config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e.
* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
__riscv_32e when TARGET_RVE.  Handle ABI_ILP32E as soft-float ABI.
* config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E.
* config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE,
compute save_libcall_adjustment properly.
(riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E.
(riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E.
* config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E.
(STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE.
(GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise.
(ABI_SPEC): Handle mabi=ilp32e.
* config/riscv/riscv.opt (abi_type): Add ABI_ILP32E.
(RVE): Add RVE mask.
* doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info.
<-march>: Add rv32e as an example.

gcc/testsuite/
* gcc.dg/stack-usage-1.c: Add support for rv32e.

libgcc/
* config/riscv/save-restore.S: Add support for rv32e.

Co-Authored-By: Jim Wilson <jimw@sifive.com>
Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com>
From-SVN: r260384

6 years agoAliasing 'this' in a C++ constructor
Marc Glisse [Fri, 18 May 2018 22:21:20 +0000 (00:21 +0200)]
Aliasing 'this' in a C++ constructor

2018-05-18  Marc Glisse  <marc.glisse@inria.fr>

PR c++/82899
gcc/
* tree-ssa-structalias.c (create_variable_info_for_1): Extra argument.
(intra_create_variable_infos): Handle C++ constructors.

gcc/testsuite/
* g++.dg/pr82899.C: New testcase.

From-SVN: r260383

6 years ago2018-05-18 François Dumont <fdumont@gcc.gnu.org>
François Dumont [Fri, 18 May 2018 20:49:49 +0000 (20:49 +0000)]
2018-05-18  François Dumont  <fdumont@gcc.gnu.org>

* include/bits/stl_tree.h
(_Rb_tree_impl(_Rb_tree_impl&&, _Node_allocator&&)): New.
(_Rb_tree(_Rb_tree&&, _Node_allocator&&, true_type)): New, use latter.
(_Rb_tree(_Rb_tree&&, _Node_allocator&&, false_type)): New.
(_Rb_tree(_Rb_tree&&, _Node_allocator&&)): Adapt, use latters.
* include/debug/map.h
(map(map&&, const_allocator_type&)): Add noexcept qualitication.
* include/debug/multimap.h
(multimap(multimap&&, const_allocator_type&)): Likewise.
* include/debug/set.h
(set(set&&, const_allocator_type&)): Likewise.
* include/debug/multiset.h
(multiset(multiset&&, const_allocator_type&)): Likewise.
* testsuite/23_containers/map/cons/noexcept_default_construct.cc:
Add checks.
* testsuite/23_containers/map/cons/noexcept_move_construct.cc:
Add checks.
* testsuite/23_containers/multimap/cons/noexcept_default_construct.cc:
Add checks.
* testsuite/23_containers/multimap/cons/noexcept_move_construct.cc:
Add checks.
* testsuite/23_containers/multiset/cons/noexcept_default_construct.cc:
Add checks.
* testsuite/23_containers/multiset/cons/noexcept_move_construct.cc:
Add checks.
* testsuite/23_containers/set/cons/noexcept_default_construct.cc:
Add checks.
* testsuite/23_containers/set/cons/noexcept_move_construct.cc:
Add checks.

From-SVN: r260382

6 years agoPR c++/58407 - deprecated implicit copy ops.
Jason Merrill [Fri, 18 May 2018 20:02:48 +0000 (16:02 -0400)]
PR c++/58407 - deprecated implicit copy ops.

gcc/c-family/
* c.opt (Wdeprecated-copy): New flag.
gcc/cp/
* call.c (build_over_call): Warn about deprecated trivial fns.
* class.c (classtype_has_user_copy_or_dtor): New.
(type_build_ctor_call): Check TREE_DEPRECATED.
(type_build_dtor_call): Likewise.
* decl2.c (cp_warn_deprecated_use): Move from tree.c.
Add checks.  Return bool.  Handle -Wdeprecated-copy.
(mark_used): Use it.
* decl.c (grokdeclarator): Remove redundant checks.
* typeck2.c (build_functional_cast): Likewise.
* method.c (lazily_declare_fn): Mark deprecated copy ops.
* init.c (build_aggr_init): Only set TREE_USED if there are
side-effects.
libitm/
* beginend.cc (save): Disable -Werror=deprecated-copy.

From-SVN: r260381

6 years agoSome libstdc++ fixes for -Wdeprecated-copy.
Jason Merrill [Fri, 18 May 2018 20:02:14 +0000 (16:02 -0400)]
Some libstdc++ fixes for -Wdeprecated-copy.

* include/bits/stl_deque.h (_Deque_iterator): Constrain constructor
for conversion to const_iterator.  Add defaulted copy ops.
* libsupc++/new (bad_alloc): Add defaulted copy ops.
* libsupc++/exception.h (exception): Add defaulted copy ops.
* include/std/system_error (system_error): Add defaulted copy ops.
* include/std/stdexcept (domain_error, invalid_argument)
(length_error, out_of_range, range_error, overflow_error)
(underflow_error): Add defaulted copy ops.
* include/bits/stl_iterator.h (reverse_iterator): Add defaulted
copy assignment.
* include/bits/allocator.h (allocator): Add defaulted copy assignment.
* include/ext/throw_allocator.h (condition_base): Add defaulted
default and copy ctor and copy assignment.

From-SVN: r260380

6 years agoFix typo in test-case.
Martin Liska [Fri, 18 May 2018 19:52:52 +0000 (21:52 +0200)]
Fix typo in test-case.

2018-05-18  Martin Liska  <mliska@suse.cz>

* gcc.dg/pr68766.c: Change pruned output.

From-SVN: r260379

6 years agoRemove redundand pass pass_lower_switch.
Martin Liska [Fri, 18 May 2018 19:52:23 +0000 (21:52 +0200)]
Remove redundand pass pass_lower_switch.

2018-05-18  Martin Liska  <mliska@suse.cz>

* passes.def: Remove a redundant pass.

From-SVN: r260378

6 years agore PR bootstrap/85838 (-Wmaybe-uninitialized warning in sparc.c (sparc_expand_builtin...
Eric Botcazou [Fri, 18 May 2018 18:49:20 +0000 (18:49 +0000)]
re PR bootstrap/85838 (-Wmaybe-uninitialized warning in sparc.c (sparc_expand_builtin) breaks SPARC bootstrap)

PR bootstrap/85838
* config/sparc/sparc.c (sparc_expand_builtin): Always initialize op[0].

From-SVN: r260374

6 years agoPR libstdc++/85098 add missing definitions for static constants
Jonathan Wakely [Fri, 18 May 2018 16:14:04 +0000 (17:14 +0100)]
PR libstdc++/85098 add missing definitions for static constants

In C++11 and C++14 any odr-use of these constants requires a definition
at namespace-scope.  In C++17 they are implicitly inline and so the
namespace-scope redeclarations are redundant (and allowing them is
deprecated).

PR libstdc++/85098
* include/bits/regex.h [__cplusplus < 201703L] (basic_regex::icase)
(basic_regex::nosubs, basic_regex::optimize, basic_regex::collate)
(basic_regex::ECMAScript, basic_regex::basic, basic_regex::extended)
(basic_regex::awk, basic_regex::grep, basic_regex::egrep): Add
definitions.
* include/bits/regex_automaton.h (_NFA::_M_insert_state): Adjust
whitespace.
* include/bits/regex_compiler.tcc (__INSERT_REGEX_MATCHER): Add
braces around body of do-while.
* testsuite/28_regex/basic_regex/85098.cc: New

From-SVN: r260371

6 years agore PR c++/85782 (acc loops with continue statements ICE in c++)
Cesar Philippidis [Fri, 18 May 2018 15:43:09 +0000 (08:43 -0700)]
re PR c++/85782 (acc loops with continue statements ICE in c++)

PR c++/85782

gcc/cp/
* cp-gimplify.c (cp_genericize_r): Call genericize_omp_for_stmt for
OACC_LOOPs.

gcc/testsuite/
* c-c++-common/goacc/pr85782.c: New test.

libgomp/
* testsuite/libgomp.oacc-c-c++-common/pr85782.c: New test.

From-SVN: r260369

6 years ago[AARCH64, SVE] Remove a couple of xfail from slp_5.c
Sudakshina Das [Fri, 18 May 2018 13:19:46 +0000 (13:19 +0000)]
[AARCH64, SVE]  Remove a couple of xfail from slp_5.c

*** gcc/testsuite/ChangeLog ***

2018-05-18  Sudakshina Das  <sudi.das@arm.com>

* gcc.target/aarch64/sve/slp_5.c: Remove xfail for tld1d and tld2d.

From-SVN: r260365

6 years ago[arm][2/2] Remove support for -march=armv3 and older
Kyrylo Tkachov [Fri, 18 May 2018 13:10:36 +0000 (13:10 +0000)]
[arm][2/2] Remove support for -march=armv3 and older

We deprecated architecture versions earlier than Armv4T in GCC 6 [1].
This patch removes support for architectures lower than Armv4.
That is the -march values armv2, armv2a, armv3, armv3m are removed
with this patch.  I did not remove armv4 because it's a bit more
involved code-wise and there has been some pushback on the implications
for -mcpu=strongarm support.

Removing armv3m and earlier though is pretty straightforward.
This allows us to get rid of the armv3m and mode32 feature bits
in arm-cpus.in as they can be assumed to be universally available.

Consequently the mcpu values arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dm are now also removed.

Bootstrapped and tested on arm-none-linux-gnueabihf and on arm-none-eabi
with an aprofile multilib configuration (which builds quite a lot of library
configurations).

[1] https://gcc.gnu.org/gcc-6/changes.html#arm

* config/arm/arm-cpus.in (armv3m, mode32): Delete features.
(ARMv4): Update.
(ARMv2, ARMv3, ARMv3m): Delete fgroups.
(ARMv6m): Update.
(armv2, armv2a, armv3, armv3m): Delete architectures.
(arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620,
arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720,
arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi):
Delete cpus.
* config/arm/arm.md (maddsidi4): Remove check for arm_arch3m.
(*mulsidi3adddi): Likewise.
(mulsidi3): Likewise.
(*mulsidi3_nov6): Likewise.
(umulsidi3): Likewise.
(umulsidi3_nov6): Likewise.
(umaddsidi4): Likewise.
(*umulsidi3adddi): Likewise.
(smulsi3_highpart): Likewise.
(*smulsi3_highpart_nov6): Likewise.
(umulsi3_highpart): Likewise.
(*umulsi3_highpart_nov6): Likewise.
* config/arm/arm.h (arm_arch3m): Delete.
* config/arm/arm.c (arm_arch3m): Delete.
(arm_option_override_internal): Update armv3-related comment.
(arm_configure_build_target): Delete use of isa_bit_mode32.
(arm_option_reconfigure_globals): Delete set of arm_ach3m.
(arm_rtx_costs_internal): Delete check of arm_arch3m.
* config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m.
(mulsa3): Likewise.
(mulusa3): Likewise.
* config/arm/arm-protos.h (arm_arch3m): Delete.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* config/arm/t-arm-elf (all_early_nofp): Delete mentions of
deleted architectures.

* gcc.target/arm/pr62554.c: Delete.
* gcc.target/arm/pr69610-1.c: Likewise.
* gcc.target/arm/pr69610-2.c: Likewise.

From-SVN: r260363

6 years ago[arm][1/2] Remove support for deprecated -march=armv5 and armv5e
Kyrylo Tkachov [Fri, 18 May 2018 13:08:16 +0000 (13:08 +0000)]
[arm][1/2] Remove support for deprecated -march=armv5 and armv5e

The -march=armv5 and armv5e options have been deprecated in GCC 7 [1].
This patch removes support for them.
It's mostly mechanical stuff. The functionality that was previously
gated on arm_arch5 is now gated on arm_arch5t and the functionality
that was gated on arm_arch5e is now gated on arm_arch5te.

A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and
therefore is deleted.

References to armv5 and armv5e are deleted/updated throughout the
source tree and testsuite.

Bootstrapped and tested on arm-none-linux-gnueabihf.
Also built a cc1 for arm-wrs-vxworks as a sanity check.

        * config/arm/arm-cpus.in (armv5, armv5e): Delete features.
        (armv5t, armv5te): New features.
        (ARMv5, ARMv5e): Delete fgroups.
        (ARMv5t, ARMv5te): Adjust for above changes.
        (ARMv6m): Likewise.
        (armv5, armv5e): Delete arches.
        * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of
        arm_arch5.
        (*call_reg_arm): Likewise.
        (*call_value_reg_armv5): Likewise.
        (*call_value_reg_arm): Likewise.
        (*call_symbol): Likewise.
        (*call_value_symbol): Likewise.
        (*sibcall_insn): Likewise.
        (*sibcall_value_insn): Likewise.
        (clzsi2): Likewise.
        (prefetch): Likewise.
        (define_split and define_peephole2 dependent on arm_arch5):
        Likewise.
        * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of
        arm_arch5e.
        (TARGET_ARM_QBIT): Likewise.
        (TARGET_DSP_MULTIPLY): Likewise.
        (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E.
        (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm.c (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t): Declare.
        (arm_option_reconfigure_globals): Update for the above.
        (arm_options_perform_arch_sanity_checks): Update comment, replace
        use of arm_arch5 with arm_arch5t.
        (use_return_insn): Likewise.
        (arm_emit_call_insn): Likewise.
        (output_return_instruction): Likewise.
        (arm_final_prescan_insn): Likewise.
        (arm_coproc_builtin_available): Likewise.
        * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and
        arm_arch5e with arm_arch5t and arm_arch5te.
        * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm-tables.opt: Regenerate.
        * config/arm/t-arm-elf: Remove references to armv5, armv5e.
        * config/arm/t-multilib: Likewise.
        * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t
        instead of arm_arch5.
        (*call_reg_thumb1): Likewise.
        (*call_value_reg_thumb1_v5): Likewise.
        (*call_value_reg_thumb1): Likewise.
        * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now
        unreachable path.
        * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e.

        * gcc.target/arm/pr40887.c: Update comment.
        * lib/target-supports.exp: Don't generate effective target checks
        and related helpers for armv5.  Update comment.
        * gcc.target/arm/armv5_thumb_isa.c: Delete.
        * gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective
        target check and options.

        * config/arm/libunwind.S: Update comment relating to armv5.

From-SVN: r260362

6 years agogcov: add new option -t that prints output to stdout (PR gcov-profile/84846).
Martin Liska [Fri, 18 May 2018 13:06:31 +0000 (15:06 +0200)]
gcov: add new option -t that prints output to stdout (PR gcov-profile/84846).

2018-05-18  Martin Liska  <mliska@suse.cz>

PR gcov-profile/84846
* gcov.c (print_usage): Add new -t option.
(process_args): Handle the option.
(generate_results): Use stdout as output when requested by
the option.
2018-05-18  Martin Liska  <mliska@suse.cz>

PR gcov-profile/84846
* doc/gcov.texi: Document -t option of gcov tool.

From-SVN: r260361

6 years agoPrint working directory to gcov files (PR gcov-profile/84846).
Martin Liska [Fri, 18 May 2018 12:46:32 +0000 (14:46 +0200)]
Print working directory to gcov files (PR gcov-profile/84846).

2018-05-18  Martin Liska  <mliska@suse.cz>

PR gcov-profile/84846
* coverage.c (coverage_init): Write PWD to .gcno file.
* doc/gcov.texi: Document how working directory is printed.
* gcov-dump.c (dump_gcov_file): Print PWD.
* gcov.c (output_intermediate_file): Likewise.
(read_graph_file): Read PWD string.
(output_lines): Print PWD.

From-SVN: r260359

6 years agore PR middle-end/85817 (ICE in expand_call at gcc/calls.c:4291)
Prathamesh Kulkarni [Fri, 18 May 2018 12:31:04 +0000 (12:31 +0000)]
re PR middle-end/85817 (ICE in expand_call at gcc/calls.c:4291)

2018-05-18  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

PR middle-end/85817
* ipa-pure-const.c (malloc_candidate_p): Remove the check integer_zerop
for retval and return false if all args to phi are zero.

testsuite/
* gcc.dg/tree-ssa/pr83648.c: Change scan-tree-dump to
scan-tree-dump-not for h.

From-SVN: r260358

6 years agogimple-ssa-evrp.c (class evrp_folder): Add simplify_stmt_using_ranges method.
Richard Biener [Fri, 18 May 2018 11:54:37 +0000 (11:54 +0000)]
gimple-ssa-evrp.c (class evrp_folder): Add simplify_stmt_using_ranges method.

2018-05-18  Richard Biener  <rguenther@suse.de>

* gimple-ssa-evrp.c (class evrp_folder): Add simplify_stmt_using_ranges
method.
(evrp_dom_walker::before_dom_children): Call it.

* gcc.dg/tree-ssa/pr21559.c: Adjust.
* gcc.dg/tree-ssa/pr45397.c: Likewise.
* gcc.dg/tree-ssa/pr61839_1.c: Likewise.
* gcc.dg/tree-ssa/pr61839_2.c: Likewise.
* gcc.dg/tree-ssa/pr61839_4.c: Likewise.
* gcc.dg/tree-ssa/vrp17.c: Likewise.
* gcc.dg/tree-ssa/vrp18.c: Likewise.
* gcc.dg/tree-ssa/vrp23.c: Likewise.
* gcc.dg/tree-ssa/vrp24.c: Likewise.
* gcc.dg/tree-ssa/vrp58.c: Likewise.
* gcc.dg/vrp-min-max-1.c: Likewise.
* gcc.dg/vrp-min-max-3.c: New testcase.

From-SVN: r260357

6 years agotree-dfa.c (get_ref_base_and_extent): Use range-info to refine results when processin...
Richard Biener [Fri, 18 May 2018 10:12:20 +0000 (10:12 +0000)]
tree-dfa.c (get_ref_base_and_extent): Use range-info to refine results when processing array refs with variable index.

2018-05-18  Richard Biener  <rguenther@suse.de>

* tree-dfa.c (get_ref_base_and_extent): Use range-info to refine
results when processing array refs with variable index.

* gcc.dg/tree-ssa/ssa-dse-35.c: New testcase.
* gcc.dg/graphite/scop-10.c: Adjust to avoid dead code.
* gcc.dg/graphite/scop-6.c: Likewise.
* gcc.dg/graphite/scop-7.c: Likewise.
* gcc.dg/graphite/scop-8.c: Likewise.
* gcc.dg/graphite/scop-9.c: Likewise.

From-SVN: r260354

6 years agoinvoke.texi: Move -floop-unroll-and-jam documentation directly after that of -floop...
Toon Moene [Fri, 18 May 2018 09:07:39 +0000 (09:07 +0000)]
invoke.texi: Move -floop-unroll-and-jam documentation directly after that of -floop-interchange.

2018-05-18  Toon Moene  <toon@moene.org>

* doc/invoke.texi: Move -floop-unroll-and-jam documentation
directly after that of -floop-interchange. Indicate that both
options are enabled by default when specifying -O3.

From-SVN: r260352

6 years ago[AArch64] Unify vec_set patterns, support floating-point vector modes properly
Kyrylo Tkachov [Fri, 18 May 2018 08:52:30 +0000 (08:52 +0000)]
[AArch64] Unify vec_set patterns, support floating-point vector modes properly

We've a deficiency in our vec_set family of patterns.
We don't support directly loading a vector lane using LD1 for V2DImode and all the vector floating-point modes.
We do do it correctly for the other integer vector modes (V4SI, V8HI etc) though.

The alternatives on the relative floating-point patterns only allow a register-to-register INS instruction.
That means if we want to load a value into a vector lane we must first load it into a scalar register and then
perform an INS, which is wasteful.

There is also an explicit V2DI vec_set expander dangling around for no reason that I can see. It seems to do the
exact same things as the other vec_set expanders. This patch removes that.
It now unifies all vec_set expansions into a single "vec_set<mode>" define_expand using the catch-all VALL_F16 iterator.

With this patch we avoid loading values into scalar registers and then doing an explicit INS on them to move them into
the desired vector lanes. For example for:

typedef float v4sf __attribute__ ((vector_size (16)));
typedef long long v2di __attribute__ ((vector_size (16)));

v2di
foo_v2di (long long *a, long long *b)
{
  v2di res = { *a, *b };
  return res;
}

v4sf
foo_v4sf (float *a, float *b, float *c, float *d)
{
  v4sf res = { *a, *b, *c, *d };
  return res;
}

we currently generate:

foo_v2di:
        ldr     d0, [x0]
        ldr     x0, [x1]
        ins     v0.d[1], x0
        ret

foo_v4sf:
        ldr     s0, [x0]
        ldr     s3, [x1]
        ldr     s2, [x2]
        ldr     s1, [x3]
        ins     v0.s[1], v3.s[0]
        ins     v0.s[2], v2.s[0]
        ins     v0.s[3], v1.s[0]
        ret

but with this patch we generate the much cleaner:
foo_v2di:
        ldr     d0, [x0]
        ld1     {v0.d}[1], [x1]
        ret

foo_v4sf:
        ldr     s0, [x0]
        ld1     {v0.s}[1], [x1]
        ld1     {v0.s}[2], [x2]
        ld1     {v0.s}[3], [x3]
        ret

* config/aarch64/aarch64-simd.md (vec_set<mode>): Use VALL_F16 mode
iterator.  Delete separate integer-mode vec_set<mode> expander.
(aarch64_simd_vec_setv2di): Delete.
(vec_setv2di): Delete.
(aarch64_simd_vec_set<mode>): Delete all other patterns with that name.
Use VALL_F16 mode iterator.  Add LD1 alternative and use vwcore for
the "w, r" alternative.

* gcc.target/aarch64/vect-init-ld1.c: New test.

From-SVN: r260351

6 years agoRadically simplify emission of balanced tree for switch statements.
Martin Liska [Fri, 18 May 2018 08:43:19 +0000 (10:43 +0200)]
Radically simplify emission of balanced tree for switch statements.

2018-05-18  Martin Liska  <mliska@suse.cz>

* passes.def: Add pass_lower_switch and pass_lower_switch_O0.
* tree-pass.h (make_pass_lower_switch_O0): New function.
* tree-switch-conversion.c (node_has_low_bound): Remove.
(node_has_high_bound): Likewise.
(node_is_bounded): Likewise.
(class pass_lower_switch): Make it a template type and create
two instances.
(pass_lower_switch::execute): Add template argument.
(make_pass_lower_switch): New function.
(make_pass_lower_switch_O0): New function.
(do_jump_if_equal): Remove.
(emit_case_nodes): Simplify to just handle all 3 cases and leave
all the hard work to tree optimization passes.
2018-05-18  Martin Liska  <mliska@suse.cz>

* gcc.dg/tree-ssa/vrp104.c: Adjust dump file that is scanned.
* gcc.dg/tree-prof/update-loopch.c: Likewise.

From-SVN: r260350

6 years agoSupport lower and upper limit for -fdbg-cnt flag.
Martin Liska [Fri, 18 May 2018 08:42:15 +0000 (10:42 +0200)]
Support lower and upper limit for -fdbg-cnt flag.

2018-05-18  Martin Liska  <mliska@suse.cz>

* dbgcnt.c (limit_low): Renamed from limit.
(limit_high): New variable.
(dbg_cnt_is_enabled): Check for upper limit.
(dbg_cnt): Adjust dumping.
(dbg_cnt_set_limit_by_index): Add new argument for high
value.
(dbg_cnt_set_limit_by_name): Likewise.
(dbg_cnt_process_single_pair): Parse new format.
(dbg_cnt_process_opt): Use strtok.
(dbg_cnt_list_all_counters): Remove 'value' and add
'limit_high'.
* doc/invoke.texi: Document changes.
2018-05-18  Martin Liska  <mliska@suse.cz>

* gcc.dg/ipa/ipa-icf-39.c: New test.
* gcc.dg/pr68766.c: Adjust pruned output.

From-SVN: r260349

6 years agoReplace FMA_EXPR with one internal fn per optab
Richard Sandiford [Fri, 18 May 2018 08:27:58 +0000 (08:27 +0000)]
Replace FMA_EXPR with one internal fn per optab

There are four optabs for various forms of fused multiply-add:
fma, fms, fnma and fnms.  Of these, only fma had a direct gimple
representation.  For the other three we relied on special pattern-
matching during expand, although tree-ssa-math-opts.c did have
some code to try to second-guess what expand would do.

This patch removes the old FMA_EXPR representation of fma and
introduces four new internal functions, one for each optab.
IFN_FMA is tied to BUILT_IN_FMA* while the other three are
independent directly-mapped internal functions.  It's then
possible to do the pattern-matching in match.pd and
tree-ssa-math-opts.c (via folding) can select the exact
FMA-based operation.

The BRIG & HSA parts are a best guess, but seem relatively simple.

2018-05-18  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* doc/sourcebuild.texi (scalar_all_fma): Document.
* tree.def (FMA_EXPR): Delete.
* internal-fn.def (FMA, FMS, FNMA, FNMS): New internal functions.
* internal-fn.c (ternary_direct): New macro.
(expand_ternary_optab_fn): Likewise.
(direct_ternary_optab_supported_p): Likewise.
* Makefile.in (build/genmatch.o): Depend on case-fn-macros.h.
* builtins.c (fold_builtin_fma): Delete.
(fold_builtin_3): Don't call it.
* cfgexpand.c (expand_debug_expr): Remove FMA_EXPR handling.
* expr.c (expand_expr_real_2): Likewise.
* fold-const.c (operand_equal_p): Likewise.
(fold_ternary_loc): Likewise.
* gimple-pretty-print.c (dump_ternary_rhs): Likewise.
* gimple.c (DEFTREECODE): Likewise.
* gimplify.c (gimplify_expr): Likewise.
* optabs-tree.c (optab_for_tree_code): Likewise.
* tree-cfg.c (verify_gimple_assign_ternary): Likewise.
* tree-eh.c (operation_could_trap_p): Likewise.
(stmt_could_throw_1_p): Likewise.
* tree-inline.c (estimate_operator_cost): Likewise.
* tree-pretty-print.c (dump_generic_node): Likewise.
(op_code_prio): Likewise.
* tree-ssa-loop-im.c (stmt_cost): Likewise.
* tree-ssa-operands.c (get_expr_operands): Likewise.
* tree.c (commutative_ternary_tree_code, add_expr): Likewise.
* fold-const-call.h (fold_fma): Delete.
* fold-const-call.c (fold_const_call_ssss): Handle CFN_FMS,
CFN_FNMA and CFN_FNMS.
(fold_fma): Delete.
* genmatch.c (combined_fn): New enum.
(commutative_ternary_tree_code): Remove FMA_EXPR handling.
(commutative_op): New function.
(commutate): Use it.  Handle more than 2 operands.
(dt_operand::gen_gimple_expr): Use commutative_op.
(parser::parse_expr): Allow :c to be used with non-binary
operators if the commutative operand is known.
* gimple-ssa-backprop.c (backprop::process_builtin_call_use): Handle
CFN_FMS, CFN_FNMA and CFN_FNMS.
(backprop::process_assign_use): Remove FMA_EXPR handling.
* hsa-gen.c (gen_hsa_insns_for_operation_assignment): Likewise.
(gen_hsa_fma): New function.
(gen_hsa_insn_for_internal_fn_call): Use it for IFN_FMA, IFN_FMS,
IFN_FNMA and IFN_FNMS.
* match.pd: Add folds for IFN_FMS, IFN_FNMA and IFN_FNMS.
* gimple-fold.h (follow_all_ssa_edges): Declare.
* gimple-fold.c (follow_all_ssa_edges): New function.
* tree-ssa-math-opts.c (convert_mult_to_fma_1): Use the
gimple_build interface and use follow_all_ssa_edges to fold the result.
(convert_mult_to_fma): Use direct_internal_fn_suppoerted_p
instead of checking for optabs directly.
* config/i386/i386.c (ix86_add_stmt_cost): Recognize FMAs as calls
rather than FMA_EXPRs.
* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Create a
call to IFN_FMA instead of an FMA_EXPR.

gcc/brig/
* brigfrontend/brig-function.cc
(brig_function::get_builtin_for_hsa_opcode): Use BUILT_IN_FMA
for BRIG_OPCODE_FMA.
(brig_function::get_tree_code_for_hsa_opcode): Treat BUILT_IN_FMA
as a call.

gcc/c/
* gimple-parser.c (c_parser_gimple_postfix_expression): Remove
__FMA_EXPR handlng.

gcc/cp/
* constexpr.c (cxx_eval_constant_expression): Remove FMA_EXPR handling.
(potential_constant_expression_1): Likewise.

gcc/testsuite/
* lib/target-supports.exp (check_effective_target_scalar_all_fma):
New proc.
* gcc.dg/fma-1.c: New test.
* gcc.dg/fma-2.c: Likewise.
* gcc.dg/fma-3.c: Likewise.
* gcc.dg/fma-4.c: Likewise.
* gcc.dg/fma-5.c: Likewise.
* gcc.dg/fma-6.c: Likewise.
* gcc.dg/fma-7.c: Likewise.
* gcc.dg/gimplefe-26.c: Use .FMA instead of __FMA and require
scalar_all_fma.
* gfortran.dg/reassoc_7.f: Pass -ffp-contract=off.
* gfortran.dg/reassoc_8.f: Likewise.
* gfortran.dg/reassoc_9.f: Likewise.
* gfortran.dg/reassoc_10.f: Likewise.

From-SVN: r260348

6 years agoDaily bump.
GCC Administrator [Fri, 18 May 2018 00:16:37 +0000 (00:16 +0000)]
Daily bump.

From-SVN: r260347

6 years agoline-map.c (linemap_init): Use placement new.
Jason Merrill [Thu, 17 May 2018 23:28:34 +0000 (19:28 -0400)]
line-map.c (linemap_init): Use placement new.

* line-map.c (linemap_init): Use placement new.

* system.h: #include <new>.

From-SVN: r260343

6 years agoRISC-V: Optimize switch with sign-extended index.
Jim Wilson [Thu, 17 May 2018 22:37:38 +0000 (22:37 +0000)]
RISC-V: Optimize switch with sign-extended index.

gcc/
* expr.c (do_tablejump): When converting index to Pmode, if we have a
sign extended promoted subreg, and the range does not have the sign bit
set, then do a sign extend.

* config/riscv/riscv.c (riscv_extend_comparands): In unsigned QImode
test, check for sign extended subreg and/or constant operands, and
do a sign extend in that case.

gcc/testsuite/
* gcc.target/riscv/switch-qi.c: New.
* gcc.target/riscv/switch-si.c: New.

From-SVN: r260340

6 years agothunderx2t99.md (thunderx2t99_ls_both): Delete.
Steve Ellcey [Thu, 17 May 2018 21:05:46 +0000 (21:05 +0000)]
thunderx2t99.md (thunderx2t99_ls_both): Delete.

2018-05-17  Steve Ellcey  <sellcey@cavium.com>

* config/aarch64/thunderx2t99.md (thunderx2t99_ls_both): Delete.
(thunderx2t99_multiple): Delete psuedo-units from used cpus.
Add untyped.
(thunderx2t99_alu_shift): Remove alu_shift_reg, alus_shift_reg.
Change logics_shift_reg to logics_shift_imm.
(thunderx2t99_fp_loadpair_basic): Delete.
(thunderx2t99_fp_storepair_basic): Delete.
(thunderx2t99_asimd_int): Add neon_sub and neon_sub_q types.
(thunderx2t99_asimd_polynomial): Delete.
(thunderx2t99_asimd_fp_simple): Add neon_fp_mul_s_scalar_q
and neon_fp_mul_d_scalar_q.
(thunderx2t99_asimd_fp_conv): Add *int_to_fp* types.
(thunderx2t99_asimd_misc): Delete neon_dup and neon_dup_q.
(thunderx2t99_asimd_recip_step): Add missing *sqrt* types.
(thunderx2t99_asimd_lut): Add missing tbl types.
(thunderx2t99_asimd_ext): Delete.
(thunderx2t99_asimd_load1_1_mult): Delete.
(thunderx2t99_asimd_load1_2_mult): Delete.
(thunderx2t99_asimd_load1_ldp): New.
(thunderx2t99_asimd_load1): New.
(thunderx2t99_asimd_load2): Add missing *load2* types.
(thunderx2t99_asimd_load3): New.
(thunderx2t99_asimd_load4): New.
(thunderx2t99_asimd_store1_1_mult): Delete.
(thunderx2t99_asimd_store1_2_mult): Delete.
(thunderx2t99_asimd_store2_mult): Delete.
(thunderx2t99_asimd_store2_onelane): Delete.
(thunderx2t99_asimd_store_stp): New.
(thunderx2t99_asimd_store1): New.
(thunderx2t99_asimd_store2): New.
(thunderx2t99_asimd_store3): New.
(thunderx2t99_asimd_store4): New.

From-SVN: r260335

6 years agoarm_cmse.h (cmse_nsfptr_create, [...]): Remove #include <stdint.h>.
Jerome Lambourg [Thu, 17 May 2018 16:36:36 +0000 (16:36 +0000)]
arm_cmse.h (cmse_nsfptr_create, [...]): Remove #include <stdint.h>.

2018-05-17  Jerome Lambourg  <lambourg@adacore.com>

gcc/
* config/arm/arm_cmse.h (cmse_nsfptr_create, cmse_is_nsfptr): Remove
#include <stdint.h>.  Replace intptr_t with __INTPTR_TYPE__.

libgcc/
* config/arm/cmse.c (cmse_check_address_range): Replace
UINTPTR_MAX with __UINTPTR_MAX__ and uintptr_t with __UINTPTR_TYPE__.

From-SVN: r260330

6 years agore PR tree-optimization/85698 (CPU2017 525.x264_r fails starting with r257581)
Pat Haugen [Thu, 17 May 2018 16:19:16 +0000 (16:19 +0000)]
re PR tree-optimization/85698 (CPU2017 525.x264_r fails starting with r257581)

PR target/85698
* config/rs6000/rs6000.c (rs6000_output_move_128bit): Check dest operand.

* gcc.target/powerpc/pr85698.c: New test.

Co-Authored-By: Segher Boessenkool <segher@kernel.crashing.org>
From-SVN: r260329

6 years agoPR libstdc++/85818 ensure path::preferred_separator is defined
Jonathan Wakely [Thu, 17 May 2018 15:36:25 +0000 (16:36 +0100)]
PR libstdc++/85818 ensure path::preferred_separator is defined

Because path.cc is compiled with -std=gnu++17 the static constexpr
data member is implicitly 'inline' and so no definition gets emitted
unless it gets used in that translation unit. Other translation units
built as C++11 or C++14 still require a namespace-scope definition of
the variable, so mark the definition as used.

PR libstdc++/85818
* src/filesystem/path.cc (path::preferred_separator): Add used
attribute.
* testsuite/experimental/filesystem/path/preferred_separator.cc: New.

From-SVN: r260326

6 years agoPR libstdc++/85812 fix memory leak in std::make_exception_ptr
Jonathan Wakely [Thu, 17 May 2018 15:03:29 +0000 (16:03 +0100)]
PR libstdc++/85812 fix memory leak in std::make_exception_ptr

PR libstdc++/85812
* libsupc++/cxxabi_init_exception.h (__cxa_free_exception): Declare.
* libsupc++/exception_ptr.h (make_exception_ptr) [__cpp_exceptions]:
Refactor to separate non-throwing and throwing implementations.
[__cpp_rtti && !_GLIBCXX_HAVE_CDTOR_CALLABI]: Deallocate the memory
if constructing the object throws.

From-SVN: r260323

6 years agotree-ssa-dse.c (dse_classify_store): Fix iterator increment for pruning loop and...
Richard Biener [Thu, 17 May 2018 13:42:21 +0000 (13:42 +0000)]
tree-ssa-dse.c (dse_classify_store): Fix iterator increment for pruning loop and prune defs feeding only already...

2018-05-17  Richard Biener  <rguenther@suse.de>

* tree-ssa-dse.c (dse_classify_store): Fix iterator increment
for pruning loop and prune defs feeding only already visited PHIs.

From-SVN: r260322

6 years agotree-ssa-sccvn.c (vn_reference_lookup_3): Improve memset handling.
Richard Biener [Thu, 17 May 2018 12:06:44 +0000 (12:06 +0000)]
tree-ssa-sccvn.c (vn_reference_lookup_3): Improve memset handling.

2018-05-17  Richard Biener  <rguenther@suse.de>

* tree-ssa-sccvn.c (vn_reference_lookup_3): Improve memset handling.

* gcc.dg/tree-ssa/ssa-fre-63.c: New testcase.

From-SVN: r260318

6 years agore PR tree-optimization/85793 ([AARCH64] ICE in verify_gimple during GIMPLE pass...
Bin Cheng [Thu, 17 May 2018 11:25:43 +0000 (11:25 +0000)]
re PR tree-optimization/85793 ([AARCH64] ICE in verify_gimple during GIMPLE pass vect.)

PR tree-optimization/85793
* tree-vect-stmts.c (vectorizable_load): Handle 1 element-wise load
for VMAT_ELEMENTWISE.

gcc/testsuite
* gcc.dg/vect/pr85793.c: New test.

Co-Authored-By: Richard Biener <rguenther@suse.de>
From-SVN: r260317

6 years agoGimple FE support for internal functions
Richard Sandiford [Thu, 17 May 2018 10:52:58 +0000 (10:52 +0000)]
Gimple FE support for internal functions

This patch gets the gimple FE to parse calls to internal functions.
The only non-obvious thing was how the functions should be written
to avoid clashes with real function names.  One option would be to
go the magic number of underscores route, but we already do that for
built-in functions, and it would be good to keep them visually
distinct.  In the end I borrowed the local/internal label convention
from asm and used:

  x = .SQRT (y);

2018-05-17  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* internal-fn.h (lookup_internal_fn): Declare
* internal-fn.c (lookup_internal_fn): New function.
* gimple.c (gimple_build_call_from_tree): Handle calls to
internal functions.
* gimple-pretty-print.c (dump_gimple_call): Print "." before
internal function names.
* tree-pretty-print.c (dump_generic_node): Likewise.
* tree-ssa-scopedtables.c (expr_hash_elt::print): Likewise.

gcc/c/
* gimple-parser.c: Include internal-fn.h.
(c_parser_gimple_statement): Treat a leading CPP_DOT as a call.
(c_parser_gimple_call_internal): New function.
(c_parser_gimple_postfix_expression): Use it to handle CPP_DOT.
Fix typos in comment.

gcc/testsuite/
* gcc.dg/gimplefe-28.c: New test.
* gcc.dg/asan/use-after-scope-9.c: Adjust expected output for
internal function calls.
* gcc.dg/goacc/loop-processing-1.c: Likewise.

From-SVN: r260316

6 years agoAllow gimple_build with internal functions
Richard Sandiford [Thu, 17 May 2018 10:51:42 +0000 (10:51 +0000)]
Allow gimple_build with internal functions

This patch makes the function versions of gimple_build and
gimple_simplify take combined_fns rather than built_in_codes,
so that they work with internal functions too.  The old
gimple_builds were unused, so no existing callers need
to be updated.

2018-05-17  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* gimple-fold.h (gimple_build): Make the function forms take
combined_fn rather than built_in_function.
(gimple_simplify): Likewise.
* gimple-match-head.c (gimple_simplify): Likewise.
* gimple-fold.c (gimple_build): Likewise.
* tree-vect-loop.c (get_initial_def_for_reduction): Use gimple_build
rather than gimple_build_call_internal.
(get_initial_defs_for_reduction): Likewise.
(vect_create_epilog_for_reduction): Likewise.
(vectorizable_live_operation): Likewise.

From-SVN: r260315

6 years agoFix GNU coding style for G_.
Martin Liska [Thu, 17 May 2018 10:44:01 +0000 (12:44 +0200)]
Fix GNU coding style for G_.

2018-05-17  Martin Liska  <mliska@suse.cz>

* gimple-ssa-sprintf.c (format_directive): Do not use
space in between 'G_' and '('.
2018-05-17  Martin Liska  <mliska@suse.cz>

* c-warn.c (overflow_warning): Do not use
space in between 'G_' and '('.
2018-05-17  Martin Liska  <mliska@suse.cz>

* gcc.dg/plugin/ggcplug.c (plugin_init): Do not use
space in between 'G_' and '('.

From-SVN: r260314

6 years agore PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)
Jakub Jelinek [Thu, 17 May 2018 10:07:12 +0000 (12:07 +0200)]
re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)

PR target/85323
* config/i386/i386.c (ix86_fold_builtin): Handle masked shifts
even if the mask is not all ones.

* gcc.target/i386/pr85323-7.c: New test.
* gcc.target/i386/pr85323-8.c: New test.
* gcc.target/i386/pr85323-9.c: New test.

From-SVN: r260313

6 years agore PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)
Jakub Jelinek [Thu, 17 May 2018 10:01:33 +0000 (12:01 +0200)]
re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)

PR target/85323
* config/i386/i386.c (ix86_fold_builtin): Fold shift builtins by
vector.
(ix86_gimple_fold_builtin): Likewise.

* gcc.target/i386/pr85323-4.c: New test.
* gcc.target/i386/pr85323-5.c: New test.
* gcc.target/i386/pr85323-6.c: New test.

From-SVN: r260312

6 years agore PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)
Jakub Jelinek [Thu, 17 May 2018 09:54:36 +0000 (11:54 +0200)]
re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)

PR target/85323
* config/i386/i386.c: Include tree-vector-builder.h.
(ix86_vector_shift_count): New function.
(ix86_fold_builtin): Fold shift builtins by scalar count.
(ix86_gimple_fold_builtin): Likewise.

* gcc.target/i386/pr85323-1.c: New test.
* gcc.target/i386/pr85323-2.c: New test.
* gcc.target/i386/pr85323-3.c: New test.

From-SVN: r260311

6 years agoavx512fintrin.h (_mm512_set_epi16, [...]): New intrinsics.
Jakub Jelinek [Thu, 17 May 2018 09:47:52 +0000 (11:47 +0200)]
avx512fintrin.h (_mm512_set_epi16, [...]): New intrinsics.

* config/i386/avx512fintrin.h (_mm512_set_epi16, _mm512_set_epi8,
_mm512_setzero): New intrinsics.

* gcc.target/i386/avx512f-set-v32hi-1.c: New test.
* gcc.target/i386/avx512f-set-v32hi-2.c: New test.
* gcc.target/i386/avx512f-set-v32hi-3.c: New test.
* gcc.target/i386/avx512f-set-v32hi-4.c: New test.
* gcc.target/i386/avx512f-set-v32hi-5.c: New test.
* gcc.target/i386/avx512f-set-v64qi-1.c: New test.
* gcc.target/i386/avx512f-set-v64qi-2.c: New test.
* gcc.target/i386/avx512f-set-v64qi-3.c: New test.
* gcc.target/i386/avx512f-set-v64qi-4.c: New test.
* gcc.target/i386/avx512f-set-v64qi-5.c: New test.
* gcc.target/i386/avx512f-setzero-1.c: New test.

From-SVN: r260310

6 years ago[patch AArch64] Do not perform a vector splat for vector initialisation if it is...
James Greenhalgh [Thu, 17 May 2018 09:39:02 +0000 (09:39 +0000)]
[patch AArch64] Do not perform a vector splat for vector initialisation if it is not useful

In the testcase in this patch we create an SLP vector with only two
elements. Our current vector initialisation code will first duplicate
the first element to both lanes, then overwrite the top lane with a new
value.

This duplication can be clunky and wasteful.

Better would be to simply use the fact that we will always be
overwriting the remaining bits, and simply move the first element to the corrcet
place (implicitly zeroing all other bits).

This reduces the code generation for this case, and can allow more
efficient addressing modes, and other second order benefits for AArch64
code which has been vectorized to V2DI mode.

Note that the change is generic enough to catch the case for any vector
mode, but is expected to be most useful for 2x64-bit vectorization.

Unfortunately, on its own, this would cause failures in
gcc.target/aarch64/load_v2vec_lanes_1.c and
gcc.target/aarch64/store_v2vec_lanes.c , which expect to see many more
vec_merge and vec_duplicate for their simplifications to apply. To fix
this,
add a special case to the AArch64 code if we are loading from two memory
addresses, and use the load_pair_lanes patterns directly.

We also need a new pattern in simplify-rtx.c:simplify_ternary_operation
to catch:

  (vec_merge:OUTER
     (vec_duplicate:OUTER x:INNER)
     (subreg:OUTER y:INNER 0)
     (const_int N))

And simplify it to:

  (vec_concat:OUTER x:INNER y:INNER) or (vec_concat y x)

This is similar to the existing patterns which are tested in this
function, without requiring the second operand to also be a vec_duplicate.

* config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify
code generation for cases where splatting a value is not useful.
* simplify-rtx.c (simplify_ternary_operation): Simplify
vec_merge across a vec_duplicate and a paradoxical subreg forming a vector
mode to a vec_concat.

* gcc.target/aarch64/vect-slp-dup.c: New.

Co-Authored-By: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
From-SVN: r260309

6 years agore PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)
Paolo Carlini [Thu, 17 May 2018 09:17:56 +0000 (09:17 +0000)]
re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)

2018-05-17  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/85713
* g++.dg/cpp1y/lambda-generic-85713-2.C: New.

From-SVN: r260308

6 years agoconfig.gcc: Support "goldmont-plus".
Olga Makhotina [Thu, 17 May 2018 08:13:23 +0000 (08:13 +0000)]
config.gcc: Support "goldmont-plus".

2018-05-17  Olga Makhotina  <olga.makhotina@intel.com>

gcc/

* config.gcc: Support "goldmont-plus".
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
"goldmont-plus".
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
PROCESSOR_GOLDMONT_PLUS.
* config/i386/i386.c (m_GOLDMONT_PLUS): Define.
(processor_target_table): Add "goldmont-plus".
(PTA_GOLDMONT_PLUS): Define.
(ix86_lea_outperforms): Add TARGET_GOLDMONT_PLUS.
(get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT_PLUS.
(fold_builtin_cpu): Add M_INTEL_GOLDMONT_PLUS.
(fold_builtin_cpu): Add "goldmont-plus".
(ix86_add_stmt_cost): Add TARGET_GOLDMONT_PLUS.
(ix86_option_override_internal): Add "goldmont-plus".
* config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT_PLUS.
(processor_type): Add PROCESSOR_GOLDMONT_PLUS.
* config/i386/x86-tune.def: Add m_GOLDMONT_PLUS.
* doc/invoke.texi: Add goldmont-plus as x86 -march=/-mtune= CPU type.

libgcc/

* config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT_PLUS.
* config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont Plus.

gcc/testsuite/

* gcc.target/i386/builtin_target.c: Test goldmont-plus.
* gcc.target/i386/funcspec-56.inc: Test arch=goldmont-plus.

From-SVN: r260307

6 years agore PR tree-optimization/85757 (tree optimizers fail to fully clean up fixed-size...
Richard Biener [Thu, 17 May 2018 06:57:45 +0000 (06:57 +0000)]
re PR tree-optimization/85757 (tree optimizers fail to fully clean up fixed-size memcpy)

2018-05-17  Richard Biener  <rguenther@suse.de>

PR tree-optimization/85757
* tree-ssa-dse.c (dse_classify_store): Record a PHI def and
remove defs that only feed that PHI from further processing.

* gcc.dg/tree-ssa/ssa-dse-34.c: New testcase.

From-SVN: r260306

6 years agoDaily bump.
GCC Administrator [Thu, 17 May 2018 00:16:17 +0000 (00:16 +0000)]
Daily bump.

From-SVN: r260304

6 years agore PR c++/85363 (Throwing exception from member constructor (brace initializer vs...
Marek Polacek [Wed, 16 May 2018 20:37:45 +0000 (20:37 +0000)]
re PR c++/85363 (Throwing exception from member constructor (brace initializer vs initializer list))

PR c++/85363
* call.c (set_flags_from_callee): Handle AGGR_INIT_EXPRs too.
* tree.c (bot_manip): Call set_flags_from_callee for
AGGR_INIT_EXPRs too.

* g++.dg/cpp0x/initlist-throw1.C: New test.
* g++.dg/cpp0x/initlist-throw2.C: New test.

From-SVN: r260300

6 years agoRISC-V: Minor pattern name cleanup.
Jim Wilson [Wed, 16 May 2018 18:37:52 +0000 (18:37 +0000)]
RISC-V: Minor pattern name cleanup.

gcc/
* config/riscv/riscv.md (<optab>si3_mask, <optab>si3_mask_1): Prepend
asterisk to name.
(<optab>di3_mask, <optab>di3_mask_1): Likewise.

From-SVN: r260299

6 years agoDWARF: Add header for .debug_str_offsets table for dwarf_version 5.
Mark Wielaard [Wed, 16 May 2018 18:20:08 +0000 (18:20 +0000)]
DWARF: Add header for .debug_str_offsets table for dwarf_version 5.

DWARF5 defines a small header for .debug_str_offsets.  Since we only use
it for split dwarf .dwo files we don't need to keep track of the actual
index offset in an attribute.

gcc/ChangeLog

* dwarf2out.c (count_index_strings): New function.
(output_indirect_strings): Call count_index_strings and generate
header for dwarf_version >= 5.

From-SVN: r260298

6 years agoDWARF: Emit DWARF5 forms for indirect addresses and string offsets.
Mark Wielaard [Wed, 16 May 2018 18:02:25 +0000 (18:02 +0000)]
DWARF: Emit DWARF5 forms for indirect addresses and string offsets.

We already emit DWARF5 attributes and tables for indirect addresses
and string offsets, but still use GNU forms. Add a new helper function
dwarf_FORM () for emitting the right form.

Currently we only use the uleb128 forms. But DWARF5 also allows
1, 2, 3 and 4 byte forms (DW_FORM_strx[1234] and DW_FORM_addrx[1234])
which might be more space efficient.

gcc/ChangeLog

* dwarf2out.c (dwarf_FORM): New function.
(set_indirect_string): Use dwarf_FORM.
(reset_indirect_string): Likewise.
(size_of_die): Likewise.
(value_format): Likewise.
(output_die): Likewise.
(add_skeleton_AT_string): Likewise.
(output_macinfo_op): Likewise.
(index_string): Likewise.
(output_index_string_offset): Likewise.
(output_index_string): Likewise.

From-SVN: r260297

6 years agors6000.md (prefetch): Generate ISA 2.06 instructions dcbt and dcbtstt with TH=16...
Carl Love [Wed, 16 May 2018 17:21:04 +0000 (17:21 +0000)]
rs6000.md (prefetch): Generate ISA 2.06 instructions dcbt and dcbtstt with TH=16 if...

gcc/ChangeLog:

2018-05-16  Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000.md (prefetch): Generate ISA 2.06 instructions
dcbt and dcbtstt with TH=16 if operands[2] is 0 and Power 8 or newer.

From-SVN: r260296

6 years agoRemove unused function ipa_free_edge_args_substructures
Martin Jambor [Wed, 16 May 2018 16:22:56 +0000 (18:22 +0200)]
Remove unused function ipa_free_edge_args_substructures

2018-05-16  Martin Jambor  <mjambor@suse.cz>

* ipa-prop.c (ipa_free_all_edge_args): Remove.
* ipa-prop.h (ipa_free_all_edge_args): Likewise.

From-SVN: r260295

6 years agovsx-vector-6-be.c: Remove file.
Carl Love [Wed, 16 May 2018 16:06:08 +0000 (16:06 +0000)]
vsx-vector-6-be.c: Remove file.

gcc/testsuite/ChangeLog:

2018-05-16 Carl Love  <cel@us.ibm.com>
* gcc.target/powerpc/vsx-vector-6-be.c: Remove file.
* gcc.target/powerpc/vsx-vector-6-be.p7.c: New test file.
* gcc.target/powerpc/vsx-vector-6-be.p8.c: New test file.
* gcc.target/powerpc/vsx-vector-6-le.c (dg-final): Update counts for
xvcmpeqdp., xvcmpgtdp., xvcmpgedp., xxlxor, xvrdpi.

From-SVN: r260294

6 years ago[AArch64] Improve register allocation of fma
Wilco Dijkstra [Wed, 16 May 2018 14:33:16 +0000 (14:33 +0000)]
[AArch64] Improve register allocation of fma

This patch improves register allocation of fma by preferring to update the
accumulator register.  This is done by adding fma insns with operand 1 as the
accumulator.  The register allocator considers copy preferences only in operand
order, so if the first operand is dead, it has the highest chance of being
reused as the destination.  As a result code using fma often has a better
register allocation.  Performance of SPECFP2017 improves by over 0.5% on some
implementations, while it had no effect on other implementations.  Fma is more
readable too, in a simple example we now generate:

fmadd s16, s2, s1, s16
fmadd s7, s17, s16, s7
fmadd s6, s16, s7, s6
fmadd s5, s7, s6, s5

instead of:

fmadd s16, s16, s2, s1
fmadd s7, s7, s16, s6
fmadd s6, s6, s7, s5
fmadd s5, s5, s6, s4

    gcc/
* config/aarch64/aarch64.md (fma<mode>4): Change into expand pattern.
(fnma<mode>4): Likewise.
(fms<mode>4): Likewise.
(fnms<mode>4): Likewise.
(aarch64_fma<mode>4): Rename insn, reorder accumulator operand.
(aarch64_fnma<mode>4): Likewise.
(aarch64_fms<mode>4): Likewise.
(aarch64_fnms<mode>4): Likewise.
(aarch64_fnmadd<mode>4): Likewise.

From-SVN: r260292

6 years ago* tree.c (warn_deprecated_use): Return bool. Simplify logic.
Jason Merrill [Wed, 16 May 2018 13:19:56 +0000 (09:19 -0400)]
* tree.c (warn_deprecated_use): Return bool.  Simplify logic.

From-SVN: r260290

6 years agotree-vectorizer.h (struct stmt_info_for_cost): Add where member.
Richard Biener [Wed, 16 May 2018 13:08:04 +0000 (13:08 +0000)]
tree-vectorizer.h (struct stmt_info_for_cost): Add where member.

2018-05-16  Richard Biener  <rguenther@suse.de>

* tree-vectorizer.h (struct stmt_info_for_cost): Add where member.
(dump_stmt_cost): Declare.
(add_stmt_cost): Dump cost we add.
(add_stmt_costs): New function.
(vect_model_simple_cost, vect_model_store_cost, vect_model_load_cost):
No longer exported.
(vect_analyze_stmt): Adjust prototype.
(vectorizable_condition): Likewise.
(vectorizable_live_operation): Likewise.
(vectorizable_reduction): Likewise.
(vectorizable_induction): Likewise.
* tree-vect-loop.c (vect_analyze_loop_operations): Create local
cost vector to pass to vectorizable_ and record afterwards.
(vect_model_reduction_cost): Take cost vector argument and adjust.
(vect_model_induction_cost): Likewise.
(vectorizable_reduction): Likewise.
(vectorizable_induction): Likewise.
(vectorizable_live_operation): Likewise.
* tree-vect-slp.c (vect_create_new_slp_node): Initialize
SLP_TREE_NUMBER_OF_VEC_STMTS.
(vect_analyze_slp_cost_1): Remove.
(vect_analyze_slp_cost): Likewise.
(vect_slp_analyze_node_operations): Take visited args and
a target cost vector.  Avoid processing already visited stmt sets.
(vect_slp_analyze_operations): Use a local cost vector to gather
costs and register those of non-discarded instances.
(vect_bb_vectorization_profitable_p): Use add_stmt_costs.
(vect_schedule_slp_instance): Remove copying of
SLP_TREE_NUMBER_OF_VEC_STMTS.  Instead assert that it is not
zero.
* tree-vect-stmts.c (record_stmt_cost): Remove path directly
adding cost.  Record cost entry location.
(vect_prologue_cost_for_slp_op): Function to compute cost of
a constant or invariant generated for SLP vect in the prologue,
split out from vect_analyze_slp_cost_1.
(vect_model_simple_cost): Make static.  Adjust for SLP costing.
(vect_model_promotion_demotion_cost): Likewise.
(vect_model_store_cost): Likewise, make static.
(vect_model_load_cost): Likewise.
(vectorizable_bswap): Add cost vector arg and adjust.
(vectorizable_call): Likewise.
(vectorizable_simd_clone_call): Likewise.
(vectorizable_conversion): Likewise.
(vectorizable_assignment): Likewise.
(vectorizable_shift): Likewise.
(vectorizable_operation): Likewise.
(vectorizable_store): Likewise.
(vectorizable_load): Likewise.
(vectorizable_condition): Likewise.
(vectorizable_comparison): Likewise.
(can_vectorize_live_stmts): Likewise.
(vect_analyze_stmt): Likewise.
(vect_transform_stmt): Adjust calls to vectorizable_*.
* tree-vectorizer.c: Include gimple-pretty-print.h.
(dump_stmt_cost): New function.

From-SVN: r260289

6 years agoparams.def (PARAM_DSE_MAX_ALIAS_QUERIES_PER_STORE): New param.
Richard Biener [Wed, 16 May 2018 13:02:27 +0000 (13:02 +0000)]
params.def (PARAM_DSE_MAX_ALIAS_QUERIES_PER_STORE): New param.

2018-05-16  Richard Biener  <rguenther@suse.de>

* params.def (PARAM_DSE_MAX_ALIAS_QUERIES_PER_STORE): New param.
* doc/invoke.texi (dse-max-alias-queries-per-store): Document.
* tree-ssa-dse.c: Include tree-ssa-loop.h.
(check_name): New callback.
(dse_classify_store): Track cycles via a visited bitmap of PHI
defs and simplify handling of in-loop and across loop dead stores
and properly fail for loop-variant refs.  Handle byte-tracking with
multiple defs.  Use PARAM_DSE_MAX_ALIAS_QUERIES_PER_STORE for
limiting the walk.

* gcc.dg/tree-ssa/ssa-dse-32.c: New testcase.
* gcc.dg/tree-ssa/ssa-dse-33.c: Likewise.
* gcc.dg/uninit-pr81897-2.c: Use -fno-tree-dse.

From-SVN: r260288

6 years agoHandle vector boolean types when calculating the SLP unroll factor
Richard Sandiford [Wed, 16 May 2018 11:50:44 +0000 (11:50 +0000)]
Handle vector boolean types when calculating the SLP unroll factor

The SLP unrolling factor is calculated by finding the smallest
scalar type for each SLP statement and taking the number of required
lanes from the vector versions of those scalar types.  E.g. for an
int32->int64 conversion, it's the vector of int32s rather than the
vector of int64s that determines the unroll factor.

We rely on tree-vect-patterns.c to replace boolean operations like:

   bool a, b, c;
   a = b & c;

with integer operations of whatever the best size is in context.
E.g. if b and c are fed by comparisons of ints, a, b and c will become
the appropriate size for an int comparison.  For most targets this means
that a, b and c will end up as int-sized themselves, but on targets like
SVE and AVX512 with packed vector booleans, they'll instead become a
small bitfield like :1, padded to a byte for memory purposes.
The SLP code would then take these scalar types and try to calculate
the vector type for them, causing the unroll factor to be much higher
than necessary.

This patch tries to make the SLP code use the same approach as the
loop vectorizer, by splitting out the code that calculates the
statement vector type and the vector type that should be used for
the number of units.

2018-05-16  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vectorizer.h (vect_get_vector_types_for_stmt): Declare.
(vect_get_mask_type_for_stmt): Likewise.
* tree-vect-slp.c (vect_two_operations_perm_ok_p): New function,
split out from...
(vect_build_slp_tree_1): ...here.  Use vect_get_vector_types_for_stmt
to determine the statement's vector type and the vector type that
should be used for calculating nunits.  Deal with cases in which
the type has to be deferred.
(vect_slp_analyze_node_operations): Use vect_get_vector_types_for_stmt
and vect_get_mask_type_for_stmt to calculate STMT_VINFO_VECTYPE.
* tree-vect-loop.c (vect_determine_vf_for_stmt_1)
(vect_determine_vf_for_stmt): New functions, split out from...
(vect_determine_vectorization_factor): ...here.
* tree-vect-stmts.c (vect_get_vector_types_for_stmt)
(vect_get_mask_type_for_stmt): New functions, split out from
vect_determine_vectorization_factor.

gcc/testsuite/
* gcc.target/aarch64/sve/vcond_10.c: New test.
* gcc.target/aarch64/sve/vcond_10_run.c: Likewise.
* gcc.target/aarch64/sve/vcond_11.c: Likewise.
* gcc.target/aarch64/sve/vcond_11_run.c: Likewise.

From-SVN: r260287

6 years agotree-cfg.c (verify_gimple_assign_ternary): Properly verify the [VEC_]COND_EXPR embedd...
Richard Biener [Wed, 16 May 2018 10:22:52 +0000 (10:22 +0000)]
tree-cfg.c (verify_gimple_assign_ternary): Properly verify the [VEC_]COND_EXPR embedded comparison.

2018-05-16  Richard Biener  <rguenther@suse.de>

* tree-cfg.c (verify_gimple_assign_ternary): Properly
verify the [VEC_]COND_EXPR embedded comparison.

From-SVN: r260283

6 years agoPR tree-optimization/85753 - missing -Wrestrict on memcpy into a member array
Martin Sebor [Wed, 16 May 2018 02:30:38 +0000 (02:30 +0000)]
PR tree-optimization/85753 - missing -Wrestrict on memcpy into a member array

gcc/ChangeLog:

PR tree-optimization/85753
* gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref): Handle
RECORD_TYPE in addition to ARRAY_TYPE.

gcc/testsuite/ChangeLog:

PR tree-optimization/85753
* gcc.dg/Wrestrict-10.c: Adjust.
* gcc.dg/Wrestrict-16.c: New test.

From-SVN: r260280

6 years agocp-tree.h (cp_expr): Remove copy constructor.
Jason Merrill [Wed, 16 May 2018 00:57:56 +0000 (20:57 -0400)]
cp-tree.h (cp_expr): Remove copy constructor.

* cp-tree.h (cp_expr): Remove copy constructor.

* mangle.c (struct releasing_vec): Declare copy constructor.

From-SVN: r260279

6 years agoDaily bump.
GCC Administrator [Wed, 16 May 2018 00:16:25 +0000 (00:16 +0000)]
Daily bump.

From-SVN: r260277

6 years ago* constexpr.c (cxx_eval_vec_init_1): Pass tf_none if ctx->quiet.
Jason Merrill [Tue, 15 May 2018 21:56:34 +0000 (17:56 -0400)]
* constexpr.c (cxx_eval_vec_init_1): Pass tf_none if ctx->quiet.

From-SVN: r260273

6 years agoPR c++/64372 - CWG 1560, gratuitous lvalue-rvalue conversion in ?:
Jason Merrill [Tue, 15 May 2018 21:56:29 +0000 (17:56 -0400)]
PR c++/64372 - CWG 1560, gratuitous lvalue-rvalue conversion in ?:

* call.c (build_conditional_expr_1): Don't force_rvalue when one arm
is a throw-expression.

From-SVN: r260272

6 years agoPR middle-end/85643 - attribute nonstring fails to squash -Wstringop-truncation warning
Martin Sebor [Tue, 15 May 2018 21:52:16 +0000 (21:52 +0000)]
PR middle-end/85643 - attribute nonstring fails to squash -Wstringop-truncation warning

gcc/ChangeLog:

PR middle-end/85643
* calls.c (get_attr_nonstring_decl): Handle MEM_REF.

gcc/testsuite/ChangeLog:

PR middle-end/85643
* c-c++-common/attr-nonstring-7.c: New test.

From-SVN: r260271

6 years agore PR lto/85583 (lto1: internal compiler error: in lto_balanced_map, at lto/lto-parti...
Jan Hubicka [Tue, 15 May 2018 16:39:43 +0000 (18:39 +0200)]
re PR lto/85583 (lto1: internal compiler error: in lto_balanced_map, at lto/lto-partition.c:833)

PR lto/85583
* lto-partition.c (account_reference_p): Do not account
references from aliases; do not account refernces from
external initializers.

From-SVN: r260266

6 years agocp-tree.h (DECL_MAYBE_IN_CHARGE_CDTOR_P): New.
Paolo Carlini [Tue, 15 May 2018 16:03:56 +0000 (16:03 +0000)]
cp-tree.h (DECL_MAYBE_IN_CHARGE_CDTOR_P): New.

2018-05-15  Paolo Carlini  <paolo.carlini@oracle.com>

* cp-tree.h (DECL_MAYBE_IN_CHARGE_CDTOR_P): New.
(FOR_EACH_CLONE): Update.
* decl.c (grokdeclarator): Use it.
* decl2.c (vague_linkage_p): Likewise.
* mangle.c (mangle_decl): Likewise.
* method.c (lazily_declare_fn): Likewise.
* optimize.c (can_alias_cdtor, maybe_clone_body): Likewise.
* repo.c (repo_emit_p): Likewise.
* tree.c (decl_linkage): Likewise.

From-SVN: r260264

6 years agoPR libstdc++/85749 constrain seed sequences for random number engines
Jonathan Wakely [Tue, 15 May 2018 15:36:46 +0000 (16:36 +0100)]
PR libstdc++/85749 constrain seed sequences for random number engines

Constrain constructors and member functions of random number engines so
that functions taking seed sequences can only be called with types that
meet the seed sequence requirements.

PR libstdc++/85749
* include/bits/random.h (__detail::__is_seed_seq): New SFINAE helper.
(linear_congruential_engine, mersenne_twister_engine)
(subtract_with_carry_engine, discard_block_engine)
(independent_bits_engine, shuffle_order_engine): Use __is_seed_seq to
constrain function templates taking seed sequences.
* include/bits/random.tcc (linear_congruential_engine::seed(_Sseq&))
(mersenne_twister_engine::seed(_Sseq&))
(subtract_with_carry_engine::seed(_Sseq&)): Change return types to
match declarations.
* include/ext/random (simd_fast_mersenne_twister_engine): Use
__is_seed_seq to constrain function templates taking seed sequences.
* include/ext/random.tcc (simd_fast_mersenne_twister_engine::seed):
Change return type to match declaration.
* testsuite/26_numerics/random/discard_block_engine/cons/seed_seq2.cc:
New.
* testsuite/26_numerics/random/independent_bits_engine/cons/
seed_seq2.cc: New.
* testsuite/26_numerics/random/linear_congruential_engine/cons/
seed_seq2.cc: New.
* testsuite/26_numerics/random/mersenne_twister_engine/cons/
seed_seq2.cc: New.
* testsuite/26_numerics/random/pr60037-neg.cc: Adjust dg-error lineno.
* testsuite/26_numerics/random/shuffle_order_engine/cons/seed_seq2.cc:
New.
* testsuite/26_numerics/random/subtract_with_carry_engine/cons/
seed_seq2.cc: New.
* testsuite/ext/random/simd_fast_mersenne_twister_engine/cons/
seed_seq2.cc: New.

From-SVN: r260263