git.libre-soc.org Git

c/94392 - only enable -ffinite-loops for C++

This does away with enabling -ffinite-loops at -O2+ for all languages
and instead enables it selectively for C++ only.

It also makes -ffinite-loops loop-private at CFG construction time
fixing correctness issues with inlining.

2020-04-02 Richard Biener <rguenther@suse.de>

PR c/94392
* c-opts.c (c_common_post_options): Enable -ffinite-loops
for -O2 and C++11 or newer.

* common.opt (ffinite-loops): Initialize to zero.
* opts.c (default_options_table): Remove OPT_ffinite_loops
entry.
* cfgloop.h (loop::finite_p): New member.
* cfgloopmanip.c (copy_loop_info): Copy finite_p.
* ipa-icf-gimple.c (func_checker::compare_loops): Compare
finite_p.
* lto-streamer-in.c (input_cfg): Stream finite_p.
* lto-streamer-out.c (output_cfg): Likewise.
* tree-cfg.c (replace_loop_annotate): Initialize finite_p
from flag_finite_loops at CFG build time.
* tree-ssa-loop-niter.c (finite_loop_p): Check the loops
finite_p flag instead of flag_finite_loops.
* doc/invoke.texi (ffinite-loops): Adjust documentation of
default setting.

* gcc.dg/torture/pr94392.c: New testcase.

debug/94450 - remove DW_TAG_imported_unit generated in LTRANS units

This removes the DW_TAG_imported_unit we generate for each referenced
early debug unit in LTRANS units. They are more harmful than they
do good and the semantics can be read in a way making it even wrong.

2020-04-02 Richard Biener <rguenther@suse.de>

PR debug/94450
* dwarf2out.c (dwarf2out_early_finish): Remove code emitting
DW_TAG_imported_unit.

doc: RISC-V: Update binutils requirement to 2.30

Complement commit bfe78b08471f ("RISC-V: Using fmv.x.w/fmv.w.x rather
than fmv.x.s/fmv.s.x") and document a binutils 2.30 requirement in the
installation manual, matching the addition of fmv.x.w/fmv.w.x mnemonics
to GAS.

gcc/
* doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
<riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
2.30.

Fix PR94401 by considering reverse overrun

The commit r10-7415 brings scalar type consideration
to eliminate epilogue peeling for gaps, but it exposed
one problem that the current handling doesn't consider
the memory access type VMAT_CONTIGUOUS_REVERSE, for
which the overrun happens on low address side.  This
patch is to make the code take care of it by updating
the offset and construction element order accordingly.

Bootstrapped/regtested on powerpc64le-linux-gnu P8
and aarch64-linux-gnu.

2020-04-02  Kewen Lin  <linkw@gcc.gnu.org>

gcc/ChangeLog

    PR tree-optimization/94401
    * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
    access type when loading halves of vector to avoid peeling for gaps.

Fix up -Wliteral-suffix warning on mti-linux.h

I've noticed while trying to reproduce PR92989 the following warning:
In file included from ./tm.h:42,
                 from ../../gcc/backend.h:28,
                 from ../../gcc/lra-assigns.c:80:
../../gcc/config/mips/mti-linux.h:31:5: warning: invalid suffix on literal; C++11 requires a space between literal and string macro [-Wliteral-suffix]
     "/%{mmicromips:micro}mips%{mel|EL:el}-"MIPS_SYSVERSION_SPEC  \
     ^
This fixes it, string concatenation works just fine even with whitespace
in between.

2020-04-02  Jakub Jelinek  <jakub@redhat.com>

* config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
between a string literal and MIPS_SYSVERSION_SPEC macro.

sra/doc: Document param sra-max-propagations

I forgot to document the new param in invoke.texi, does the text below
look OK?

Tested with make info and make pdf.

Thanks,

Martin

2020-04-02 Martin Jambor <mjambor@suse.cz>

* doc/invoke.texi (Optimize Options): Document sra-max-propagations.

params: Decrease -param=max-find-base-term-values= default [PR92264]

For the PR in question, my proposal would be to also lower
-param=max-find-base-term-values=
default from 2000 to 200 after this, at least in the above 4
bootstraps/regtests there is nothing that would ever result in
find_base_term returning non-NULL with more than 200 VALUEs being processed.

2020-04-02 Jakub Jelinek <jakub@redhat.com>

PR rtl-optimization/92264
* params.opt (-param=max-find-base-term-values=): Decrease default
from 2000 to 200.

cselib: Reuse VALUEs on sp adjustments [PR92264]

As discussed in the PR, if !ACCUMULATE_OUTGOING_ARGS on large functions we
can have hundreds of thousands of stack pointer adjustments and cselib
creates a new VALUE after each sp adjustment, which form extremely deep
VALUE chains, which is very harmful e.g. for find_base_term.
E.g. if we have
sp -= 4
sp -= 4
sp += 4
sp += 4
sp -= 4
sp += 4
that means 7 VALUEs, one for the sp at beginning (val1), than val2 = val1 -
4, then val3 = val2 - 4, then val4 = val3 + 4, then val5 = val4 + 4, then
val6 = val5 - 4, then val7 = val6 + 4.
This patch tweaks cselib, so that it is smarter about sp adjustments.
When cselib_lookup (stack_pointer_rtx, Pmode, 1, VOIDmode) and we know
nothing about sp yet (this happens at the start of the function, for
non-var-tracking also after cselib_reset_table and for var-tracking after
processing fp_setter insn where we forget about former sp values because
that is now hfp related while everything after it is sp related), we
look it up normally, but in addition to what we have been doing before
we mark the VALUE as SP_DERIVED_VALUE_P.  Further lookups of sp + offset
are then special cased, so that it is canonicalized to that
SP_DERIVED_VALUE_P VALUE + CONST_INT (if possible).  So, for the above,
we get val1 with SP_DERIVED_VALUE_P set, then val2 = val1 - 4, val3 = val1 -
8 (note, no longer val2 - 4!), then we get val2 again, val1 again, val2
again, val1 again.
In the find_base_term visited_vals.length () > 100 find_base_term
statistics during combined x86_64-linux and i686-linux bootstrap+regtest
cycle, without the patch I see:
find_base_term > 100
returning NULL returning non-NULL
32-bit compilations 4229178 407
64-bit compilations 217523 0
with largest visited_vals.length () when returning non-NULL being 206.
With the patch the same numbers are:
32-bit compilations 1249588 135
64-bit compilations 3510 0
with largest visited_vals.length () when returning non-NULL being 173.
This shows significant reduction of the deep VALUE chains.
On powerpc64{,le}-linux, these stats didn't change at all, we have
1008 0
for all of -m32, -m64 and little-endian -m64, just the
gcc.dg/pr85180.c and gcc.dg/pr87985.c testcases which are unrelated to sp.

My earlier version of the patch, which contained just the rtl.h and cselib.c
changes, regressed some tests:
gcc.dg/guality/{pr36728-{1,3},pr68860-{1,2}}.c
gcc.target/i386/{pr88416,sse-{13,23,24,25,26}}.c
The problem with the former tests was worse debug info, where with -m32
where arg7 was passed in a stack slot we though a push later on might have
invalidated it, when it couldn't.  This is something I've solved with the
var-tracking.c (vt_initialize) changes.  In those problematic functions, we
create a cfa_base VALUE (argp) and want to record that at the start of
the function the argp VALUE is sp + off and also record that current sp
VALUE is argp's VALUE - off.  The second permanent equivalence didn't make
it after the patch though, because cselib_add_permanent_equiv will
cselib_lookup the value of the expression it wants to add as the equivalence
and if it is the same VALUE as we are calling it on, it doesn't do anything;
and due to the cselib changes for sp based accesses that is exactly what
happened.  By reversing the order of the cselib_add_permanent_equiv calls we
get both equivalences though and thus are able to canonicalize the sp based
accesses in var-tracking to the cfa_base value + offset.
The i386 FAILs were all ICEs, where we had pushf instruction pushing flags
and then pop pseudo reading that value again.  With the cselib changes,
cselib during RTL DSE is able to see through the sp adjustment and wanted
to replace_read what was done pushf, by moving the flags register into a
pseudo and replace the memory read in the pop with that pseudo.  That is
wrong for two reasons: one is that the backend doesn't have an instruction
to move the flags hard register into some other register, but replace_read
has been validating just the mem -> pseudo replacement and not the insns
emitted by copy_to_mode_reg.  And the second issue is that it is obviously
wrong to replace a stack pop which contains stack post-increment by a copy
of pseudo into destination.  dse.c has some code to handle RTX_AUTOINC, but
only uses it when actually removing stores and only when there is REG_INC
note (stack RTX_AUTOINC does not have those), in check_for_inc_dec* where
it emits the reg adjustment(s) before the insn that is going to be deleted.
replace_read doesn't remove the insn, so if it e.g. contained REG_INC note,
it would be kept there and we might have the RTX_AUTOINC not just in *loc,
but other spots.
So, the dse.c changes try to validate the added insns and punt on all
RTX_AUTOINC in *loc.  Furthermore, it seems that with the cselib.c changes
on the gfortran.dg/pr87360.f90 and gcc.target/i386/pr88416.c testcases
check_for_inc_dec{,_1} happily throws stack pointer autoinc on the floor,
which is also wrong.  While we could perhaps do the for_each_inc_dec
call regardless of whether we have REG_INC note or not, we aren't prepared
to handle e.g. REG_ARGS_SIZE distribution and thus could end up with wrong
unwind info or ICEs during dwarf2cfi.c.  So the patch also punts on those,
after all, if we'd in theory managed to try to optimize such pushes before,
we'd create wrong-code.

On x86_64-linux and i686-linux, the patch has some minor debug info coverage
differences, but it doesn't appear very significant to me.
https://github.com/pmachata/dwlocstat tool gives (where before is vanilla
trunk + the rtl.h patch but not {cselib,var-tracking,dse}.c
--enable-checking=yes,rtl,extra bootstrapped, then {cselib,var-tracking,dse}.c
hunks applied and make cc1plus, while after is trunk with the whole patch
applied).

64-bit cc1plus
before
cov% samples cumul
0..10 1232756/48% 1232756/48%
11..20 31089/1% 1263845/49%
21..30 39172/1% 1303017/51%
31..40 38853/1% 1341870/52%
41..50 47473/1% 1389343/54%
51..60 45171/1% 1434514/56%
61..70 69393/2% 1503907/59%
71..80 61988/2% 1565895/61%
81..90 104528/4% 1670423/65%
91..100 875402/34% 2545825/100%
after
cov% samples cumul
0..10 1233238/48% 1233238/48%
11..20 31086/1% 1264324/49%
21..30 39157/1% 1303481/51%
31..40 38819/1% 1342300/52%
41..50 47447/1% 1389747/54%
51..60 45151/1% 1434898/56%
61..70 69379/2% 1504277/59%
71..80 61946/2% 1566223/61%
81..90 104508/4% 1670731/65%
91..100 875094/34% 2545825/100%

32-bit cc1plus
before
cov% samples cumul
0..10 1231221/48% 1231221/48%
11..20 30992/1% 1262213/49%
21..30 36422/1% 1298635/51%
31..40 35793/1% 1334428/52%
41..50 47102/1% 1381530/54%
51..60 41201/1% 1422731/56%
61..70 65467/2% 1488198/58%
71..80 59560/2% 1547758/61%
81..90 104076/4% 1651834/65%
91..100 881879/34% 2533713/100%
after
cov% samples cumul
0..10 1230469/48% 1230469/48%
11..20 30390/1% 1260859/49%
21..30 36362/1% 1297221/51%
31..40 36042/1% 1333263/52%
41..50 47619/1% 1380882/54%
51..60 41674/1% 1422556/56%
61..70 65849/2% 1488405/58%
71..80 59857/2% 1548262/61%
81..90 104178/4% 1652440/65%
91..100 881273/34% 2533713/100%

2020-04-02  Jakub Jelinek  <jakub@redhat.com>

PR rtl-optimization/92264
* rtl.h (struct rtx_def): Mention that call bit is used as
SP_DERIVED_VALUE_P in cselib.c.
* cselib.c (SP_DERIVED_VALUE_P): Define.
(PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
(cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
val_rtx and sp based expression where offsets cancel each other.
(preserve_constants_and_equivs): Formatting fix.
(cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
locs list for cfa_base_preserved_val if needed.  Formatting fix.
(autoinc_split): If the to be returned value is a REG, MEM or
VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
(rtx_equal_for_cselib_1): Call autoinc_split even if both
expressions are PLUS in Pmode with CONST_INT second operands.
Handle SP_DERIVED_VALUE_P cases.
(cselib_hash_plus_const_int): New function.
(cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
second operand, as well as for PRE_DEC etc. that ought to be
hashed the same way.
(cselib_subst_to_values): Substitute PLUS with Pmode and
CONST_INT operand if the first operand is a VALUE which has
SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
SP_DERIVED_VALUE_P + adjusted offset.
(cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
set SP_DERIVED_VALUE_P on it.  Set PRESERVED_VALUE_P when adding
SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
* var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
on the sp value before calling cselib_add_permanent_equiv on the
cfa_base value.
* dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
in the insn without REG_INC note.
(replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
Punt on invalid insns added by copy_to_mode_reg.  Formatting fixes.

aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]

The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits
invalid RTL.
For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits
into that mode) and x being SImode; for non-CONST_INT y it zero extends y
into SImode and compares that against x, for CONST_INT y it zero extends y
into SImode.  The problem is that when the zero extended constant isn't
usable directly, it forces it into a REG, but with y_mode mode, and then
compares against y.  That is wrong, because it should force it into a SImode
REG and compare that way.

2020-04-02  Jakub Jelinek  <jakub@redhat.com>

PR target/94435
* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.

* gcc.target/aarch64/pr94435.c: New test.

[ARM]: Fix for MVE ACLE intrinsics with writeback (PR94317).

Following MVE ACLE intrinsics have an issue with writeback to the base address.

vldrdq_gather_base_wb_s64, vldrdq_gather_base_wb_u64, vldrdq_gather_base_wb_z_s64, vldrdq_gather_base_wb_z_u64, vldrwq_gather_base_wb_s32, vldrwq_gather_base_wb_u32, vldrwq_gather_base_wb_z_s32, vldrwq_gather_base_wb_z_u32, vldrwq_gather_base_wb_f32, vldrwq_gather_base_wb_z_f32.

This patch fixes the bug reported in PR94317 by adding separate builtin calls to update the result and writeback to base address for the above intrinsics.

2020-04-02  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

PR target/94317
* config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
(LDRGBWBXU_Z_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
intrinsic defintion by adding a new builtin call to writeback into base
address.
(__arm_vldrdq_gather_base_wb_u64): Likewise.
(__arm_vldrdq_gather_base_wb_z_s64): Likewise.
(__arm_vldrdq_gather_base_wb_z_u64): Likewise.
(__arm_vldrwq_gather_base_wb_s32): Likewise.
(__arm_vldrwq_gather_base_wb_u32): Likewise.
(__arm_vldrwq_gather_base_wb_z_s32): Likewise.
(__arm_vldrwq_gather_base_wb_z_u32): Likewise.
(__arm_vldrwq_gather_base_wb_f32): Likewise.
(__arm_vldrwq_gather_base_wb_z_f32): Likewise.
* config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
builtin's qualifier.
(vldrdq_gather_base_wb_z_u): Likewise.
(vldrwq_gather_base_wb_u): Likewise.
(vldrdq_gather_base_wb_u): Likewise.
(vldrwq_gather_base_wb_z_s): Likewise.
(vldrwq_gather_base_wb_z_f): Likewise.
(vldrdq_gather_base_wb_z_s): Likewise.
(vldrwq_gather_base_wb_s): Likewise.
(vldrwq_gather_base_wb_f): Likewise.
(vldrdq_gather_base_wb_s): Likewise.
(vldrwq_gather_base_nowb_z_u): Define builtin.
(vldrdq_gather_base_nowb_z_u): Likewise.
(vldrwq_gather_base_nowb_u): Likewise.
(vldrdq_gather_base_nowb_u): Likewise.
(vldrwq_gather_base_nowb_z_s): Likewise.
(vldrwq_gather_base_nowb_z_f): Likewise.
(vldrdq_gather_base_nowb_z_s): Likewise.
(vldrwq_gather_base_nowb_s): Likewise.
(vldrwq_gather_base_nowb_f): Likewise.
(vldrdq_gather_base_nowb_s): Likewise.
* config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
pattern.
(mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
(mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
(mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
(mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
(mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
(mve_vldrdq_gather_base_wb_<supf>v4di):  Modify RTL pattern.
(mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
(mve_vldrdq_gather_base_wb_z_<supf>v4di):  Modify RTL pattern.

gcc/testsuite/ChangeLog:

2020-04-02  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

PR target/94317
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Modify.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.

libstdc++-v3/test: Better skip for "use_service.cc"

2020-04-01 Andrea Corallo <andrea.corallo@arm.com>

* testsuite/experimental/net/execution_context/use_service.cc:
Require pthread and gthreads.

[Fortran] Fix error cleanup of select rank (PR93522)

PR fortran/93522
* match.c (gfc_match_select_rank): Fix error cleanup.

PR fortran/93522
* gfortran.dg/select_rank_4.f90: New.

S/390: Remove superfluous commutative constraint modifiers

For operands with an identical set of alternatives there is no point
in marking them commutative. This patch removes the superfluous
constraint modifiers in vector.md and vx-builtins.md since it might
slow down reload without buying us anything.

There were even two patterns where the constraint modifier was plain
wrong: "sub<VF_HW>3" and "ior_not<VT>3". Fortunately it never had any effect.

gcc/ChangeLog:

2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>

* config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
modifier.
("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
Remove constraints from expander.
* config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.

fortran : ICE in gfc_resolve_findloc PR93498

ICE occurs when findloc is used with character arguments of different
kinds.  If the character kinds are different reject the code.

Original patch provided by Steven G. Kargl  <kargl@gcc.gnu.org>.

gcc/fortran/ChangeLog:

PR fortran/93498
* check.c (gfc_check_findloc):  If the kinds of the arguments
differ goto label "incompat".

gcc/testsuite/ChangeLog:

PR fortran/93498
* gfortran.dg/pr93498_1.f90:  New test.
* gfortran.dg/pr93498_2.f90:  New test.

fortran: ICE equivalence with an element of an array PR94030

Deferred size arrays can not be used in equivalance statements.

gcc/fortran/ChangeLog:

PR fortran/94030
* resolve.c (resolve_equivalence): Correct formatting
around the label "identical_types". Instead of using
gfc_resolve_array_spec use is_non_constants_shape_array
to determine whether the array can be used in a in an
equivalence statement.

gcc/testsuite/ChangeLog:

PR fortran/94030
* gfortran.dg/pr94030_1.f90
* gfortran.dg/pr94030_2.f90

Daily bump.

d: Fix new tests gdc.dg/pr93038.d and gdc.dg/pr93038b.d in r10-7320 fail

The scan-file match is likely too strict to always succeed, so instead
have split it up into a set of smaller matches.

gcc/testsuite/ChangeLog:

PR d/94315
* gdc.dg/pr93038.d: Split dg-final into multiple tests.
* gdc.dg/pr93038b.d: Likewise.

d: Fix gdc.dg/pr92216.d FAILs on 32-bit targets

The symbol being scanned for only matched on 64-bit targets.

gcc/testsuite/ChangeLog:

PR d/94321
* gdc.dg/pr92216.d: Update to work on targets with 16 or 32-bit
pointers.

libstdc++: Move "free books" list from fsf.org to gnu.org

* doc/xml/manual/appendix_free.xml: Move "free books" list from
fsf.org to gnu.org.
* doc/html/manual/appendix_free.html: Regenerate.

analyzer: handle compound assignments [PR94378]

PR analyzer/94378 reports a false -Wanalyzer-malloc-leak
when returning a struct containing a malloc-ed pointer.

The issue is that the assignment code was not handling
compound copies, only copying top-level values from region to region,
and not copying child values.

This patch introduces a region_model::copy_region function, using
it for assignments and when analyzing function return values.
It recursively copies nested values within structs, unions, and
arrays, fixing the bug.

gcc/analyzer/ChangeLog:
PR analyzer/94378
* checker-path.cc: Include "bitmap.h".
* constraint-manager.cc: Likewise.
* diagnostic-manager.cc: Likewise.
* engine.cc: Likewise.
(exploded_node::detect_leaks): Pass null region_id to pop_frame.
* program-point.cc: Include "bitmap.h".
* program-state.cc: Likewise.
* region-model.cc (id_set<region_id>::id_set): Convert to...
(region_id_set::region_id_set): ...this.
(svalue_id_set::svalue_id_set): New ctor.
(region_model::copy_region): New function.
(region_model::copy_struct_region): New function.
(region_model::copy_union_region): New function.
(region_model::copy_array_region): New function.
(stack_region::pop_frame): Drop return value.  Add
"result_dst_rid" param; if it is non-null, use copy_region to copy
the result to it.  Rather than capture and pass a single "known
used" return value to be used by purge_unused_values, instead
gather and pass a set of known used return values.
(root_region::pop_frame): Drop return value.  Add "result_dst_rid"
param.
(region_model::on_assignment): Use copy_region.
(region_model::on_return): Likewise for the result.
(region_model::on_longjmp): Pass null for pop_frame's
result_dst_rid.
(region_model::update_for_return_superedge): Pass the region for the
return value of the call, if any, to pop_frame, rather than setting
the lvalue for the lhs of the result.
(region_model::pop_frame): Drop return value.  Add
"result_dst_rid" param.
(region_model::purge_unused_svalues): Convert third param from an
svalue_id * to an svalue_id_set *, updating the initial populating
of the "used" bitmap accordingly.  Don't remap it when done.
(struct selftest::coord_test): New selftest fixture, extracted from...
(selftest::test_dump_2): ...here.
(selftest::test_compound_assignment): New selftest.
(selftest::test_stack_frames): Pass null to new param of pop_frame.
(selftest::analyzer_region_model_cc_tests): Call the new selftest.
* region-model.h (class id_set): Delete template.
(class region_id_set): Reimplement, using old id_set implementation.
(class svalue_id_set): Likewise.  Convert from auto_sbitmap to
auto_bitmap.
(region::get_active_view): New accessor.
(stack_region::pop_frame): Drop return value.  Add
"result_dst_rid" param.
(root_region::pop_frame): Likewise.
(region_model::pop_frame): Likewise.
(region_model::copy_region): New decl.
(region_model::purge_unused_svalues): Convert third param from an
svalue_id * to an svalue_id_set *.
(region_model::copy_struct_region): New decl.
(region_model::copy_union_region): New decl.
(region_model::copy_array_region): New decl.

gcc/testsuite/ChangeLog:
PR analyzer/94378
* gcc.dg/analyzer/compound-assignment-1.c: New test.
* gcc.dg/analyzer/compound-assignment-2.c: New test.
* gcc.dg/analyzer/compound-assignment-3.c: New test.

subreg: Fix PR94123, SVN r273240 causes gcc.target/powerpc/pr87507.c to fail

Segher's patch that added -fsplit-wide-types-early and enabled by default
for rs6000, caused pr87507.c to FAIL because when running lower-subreg
earlier, we don't see any pseudo-to-pseudo copies of our wide type,
which are created by combine, therefore, we skip decomposing our TImode
accesses. The fix here is just to always run the third pass of lower-subreg
instead of disabling it if we ran the second pass.

2020-04-01 Peter Bergner <bergner@linux.ibm.com>

PR rtl-optimization/94123
* lower-subreg.c (pass_lower_subreg3::gate): Remove test for
flag_split_wide_types_early.

doc: Fix typo

2020-04-01 Joerg Sonnenberger <joerg@bec.de>

* doc/extend.texi (Common Function Attributes): Fix typo.

Whoops, forgot the changelog

doc: Fix a typo in the documentation of the copy attribute

2020-04-01 Zackery Spytz <zspytz@gmail.com>

gcc/
* doc/extend.texi: Fix a typo in the documentation of the
copy function attribute.

rs6000: Make code questionably using r2 not ICE (PR94420)

The example code in the PR uses r2 (the TOC register) directly. In the
RTL generated for that, r2 is copied to some pseudo, and then cprop
propagates that into a "*tocref<mode>" insn, because nothing is
preventing it from doing that.

So, put the same condition in the insn condition for this as we will
later encounter in the constraint anyway, fixing this.

2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>

PR target/94420
* config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
on operands[1].

Add testcase for already fixed PR [PR94436]

2020-04-01 Jakub Jelinek <jakub@redhat.com>

PR middle-end/94436
* gcc.dg/pr94436.c: New test.

fortran : FAIL: gfortran.dg/pr93365.f90 PR94386

Failures of pr93365.f90,  pr93600_1.f90 and pr93600_2.f90.
Changes made by PR94246 delete and changed code from expr.c
introduced by PR93600, the deleted code.  This broke the PR93600
test cases.  Restoring the deleted code and leaving the changed
code alone allows the cases for PR93600 and PR94246 to pass.

gcc/fortran/ChangeLog:

PR fortran/94386
expr.c (simplify_parameter_variable): Restore code deleted
in PR94246.

Clear me from patch ownership.

objsz: Don't call replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI [PR94423]

The following testcase ICEs because the objsz pass calls replace_uses_by
on SSA_NAME_OCCURS_IN_ABNORMAL_PHI SSA_NAME.  The following patch instead
of that calls replace_call_with_value, which will turn it into
  xyz_123(ab) = 234;

2020-04-01  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/94423
* tree-object-size.c (pass_object_sizes::execute): Don't call
replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
call replace_call_with_value.

* gcc.dg/ubsan/pr94423.c: New test.

Fix typo in a macro usage.

PR lto/94249
* plugin-api.h: Fix a typo.

Fix PR94043 by making vect_live_op generate lc-phi

As PR94043 shows, my commit r10-4524 exposed one issue in
vectorizable_live_operation, which inserts one extra BB
before the single exit, leading unexpected operand expansion
and unexpected loop depth assertion.  As Richi suggested,
this patch is to teach vectorizable_live_operation to
generate loop closed phi for vec_lhs, it looks like:
     loop;
     # lhs' = PHI <lhs>
=>
     loop;
     # vec_lhs' = PHI <vec_lhs>
     new_tree = BIT_FIELD_REF <vec_lhs', ...>;
     lhs' = new_tree;

I noticed that there are some SLP cases that have same lhs
and vec_lhs but different offsets, which can make us have
more PHIs for the same vec_lhs there.  But I think it would
be fine since only one of them is actually live, the others
should be eliminated by the following dce.  So the patch
doesn't check whether there is one phi for vec_lhs, just
create one directly instead.

Bootstrapped/regtested on powerpc64le-linux-gnu (LE) P8.

2020-04-01  Kewen Lin  <linkw@gcc.gnu.org>

gcc/ChangeLog

    PR tree-optimization/94043
    * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
    phi for vec_lhs and use it for lane extraction.

gcc/testsuite/ChangeLog

    PR tree-optimization/94043
    * gfortran.dg/graphite/vect-pr94043.f90: New test.

c++: Fix DMI with lambda 'this' capture [PR94205]

We represent 'this' in a default member initializer with a PLACEHOLDER_EXPR.
Normally in constexpr evaluation when we encounter one it refers to
ctx->ctor, but when we're creating a temporary of class type, that replaces
ctx->ctor, so a PLACEHOLDER_EXPR that refers to the type of the member being
initialized needs to be replaced before that happens.

gcc/cp/ChangeLog
2020-03-31 Jason Merrill <jason@redhat.com>

PR c++/94205
* constexpr.c (cxx_eval_constant_expression) [TARGET_EXPR]: Call
replace_placeholders.
* typeck2.c (store_init_value): Fix arguments to
fold_non_dependent_expr.

c++: Adjust formatting.

This patch has no semantic effect; committing it separately makes the change
for 94205 easier to read.

gcc/cp/ChangeLog
2020-03-31 Jason Merrill <jason@redhat.com>

* constexpr.c (cxx_eval_constant_expression) [TARGET_EXPR]: Use
local variables.

Daily bump.

d: Merge UDAs between function prototype and definitions (PR90136)

This change fixes the symbol merging in get_symbol_decl to also consider
prototypes.  This allows the ability to set user defined attributes on
the prototype of a function, which then get applied to the definition,
if found later in the compilation.

The lowering of UDAs to GCC attributes has been commonized into a single
function called apply_user_attributes.

gcc/d/ChangeLog:

PR d/90136
* d-attribs.cc: Include dmd/attrib.h.
(build_attributes): Redeclare as static.
(apply_user_attributes): New function.
* d-tree.h (class UserAttributeDeclaration): Remove.
(build_attributes): Remove.
(apply_user_attributes): Declare.
(finish_aggregate_type): Remove attrs argument.
* decl.cc (get_symbol_decl): Merge declaration prototypes with
definitions.  Use apply_user_attributes.
* modules.cc (layout_moduleinfo_fields): Remove last argument to
finish_aggregate_type.
* typeinfo.cc (layout_classinfo_interfaces): Likewise.
* types.cc (layout_aggregate_members): Likewise.
(finish_aggregate_type): Remove attrs argument.
(TypeVisitor::visit (TypeEnum *)): Use apply_user_attributes.
(TypeVisitor::visit (TypeStruct *)): Remove last argument to
finish_aggregate_type.  Use apply_user_attributes.
(TypeVisitor::visit (TypeClass *)): Likewise.

gcc/testsuite/ChangeLog:

PR d/90136
* gdc.dg/pr90136a.d: New test.
* gdc.dg/pr90136b.d: New test.
* gdc.dg/pr90136c.d: New test.

d: Add always_inline to the internal attribute table.

This attribute is not directly accessible from user code, rather it is
indirectly added from the @forceinline attribute. Even so, a handler
should be present for it to prevent false positive warnings.

Said warnings are not something that could happen currently, but will
become a problem from fixing PR90136 later.

gcc/d/ChangeLog:

* d-attribs.cc (d_langhook_common_attribute_table): Add always_inline.
(handle_always_inline_attribute): New function.

libgccjit: add new version entry point

gcc/jit/ChangeLog
2020-03-31  Andrea Corallo  <andrea.corallo@arm.com>
    David Malcolm  <dmalcolm@redhat.com>

* docs/topics/compatibility.rst (LIBGCCJIT_ABI_13): New ABI tag
plus add version paragraph.
* libgccjit++.h (namespace gccjit::version): Add new namespace.
* libgccjit.c (gcc_jit_version_major, gcc_jit_version_minor)
(gcc_jit_version_patchlevel): New functions.
* libgccjit.h (LIBGCCJIT_HAVE_gcc_jit_version): New macro.
(gcc_jit_version_major, gcc_jit_version_minor)
(gcc_jit_version_patchlevel): New functions.
* libgccjit.map (LIBGCCJIT_ABI_13) New ABI tag.

gcc/testsuite/ChangeLog
2020-03-31  Andrea Corallo  <andrea.corallo@arm.com>

* jit.dg/test-version.c: New testcase.
* jit.dg/all-non-failing-tests.h: Add test-version.c.

libgomp – fix handling of 'target enter data'

* target.c (GOMP_target_enter_exit_data): Handle PSET/MAP_POINTER.
* testsuite/libgomp.fortran/target-enter-data-1.f90: New.

Update cpplib sr.po.

d: Use memset to fill alignment holes with zeroes.

This patch removes the manual insertion of padding for fields in
constructed struct literals, and instead uses memset() on the
declaration being initialized.

When compiling optimized builds, the intent is usually missed, and
alignment holes end up with non-zero values in them anyway.

gcc/d/ChangeLog:

PR d/94424
* d-codegen.cc (build_alignment_field): Remove.
(build_struct_literal): Don't insert alignment padding.
* expr.cc (ExprVisitor::visit (AssignExp *)): Call memset before
assigning struct literals.

gcc/testsuite/ChangeLog:

PR d/94424
* gdc.dg/pr94424.d: New test.

vect: ICE: in vectorizable_load, at tree-vect-stmts.c:9173 [PR94398]

In the testcase for PR94398, we're trying to compute:

  alignment_support_scheme
    = vect_supportable_dr_alignment (first_dr_info, false);
  gcc_assert (alignment_support_scheme);

even for VMAT_GATHER_SCATTER, which always accesses individual elements.
Here we should set alignment_support_scheme to dr_unaligned_supported
the gather/scatter case instead of calling vect_supportable_dr_alignment.

2020-03-31  Felix Yang  <felix.yang@huawei.com>

gcc/
PR tree-optimization/94398
* tree-vect-stmts.c (vectorizable_store): Instead of calling
vect_supportable_dr_alignment, set alignment_support_scheme to
dr_unaligned_supported for gather-scatter accesses.
(vectorizable_load): Likewise.

gcc/testsuite/
PR tree-optimization/94398
* gcc.target/aarch64/pr94398.c: New test.

Library-side tests for parenthesized aggregate init

PR c++/92878
PR c++/92947

* testsuite/20_util/allocator_traits/members/92878_92947.cc: New.
* testsuite/20_util/any/assign/92878_92947.cc: Likewise.
* testsuite/20_util/any/cons/92878_92947.cc: Likewise.
* testsuite/20_util/is_constructible/92878_92947.cc: Likewise.
* testsuite/20_util/optional/assignment/92878_92947.cc: Likewise.
* testsuite/20_util/optional/cons/92878_92947.cc: Likewise.
* testsuite/20_util/pair/cons/92878_92947.cc: Likewise.
* testsuite/20_util/shared_ptr/creation/92878_92947.cc: Likewise.
* testsuite/20_util/specialized_algorithms/construct_at/92878_92947.cc:
Likewise.
* testsuite/20_util/unique_ptr/creation/92878_92947.cc: Likewise.
* testsuite/20_util/uses_allocator/92878_92947.cc: Likewise.
* testsuite/20_util/variant/92878_92947.cc: Likewise.
* testsuite/23_containers/deque/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/forward_list/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/list/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/map/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/multimap/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/multiset/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/priority_queue/92878_92947.cc: Likewise.
* testsuite/23_containers/queue/92878_92947.cc: Likewise.
* testsuite/23_containers/set/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/stack/92878_92947.cc: Likewise.
* testsuite/23_containers/unordered_map/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/unordered_multimap/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/unordered_multiset/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/unordered_set/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/vector/modifiers/emplace/92878_92947.cc:
Likewise.

d: Use d_comdat_linkage on generated internal decl.

This adds weak linkage to internal TypeInfo data on top of the existing
DECL_COMDAT, which helps in the unlikely event that two of the same
TypeInfo data ends up in multiple places.

gcc/d/ChangeLog:

* typeinfo.cc (TypeInfoVisitor::internal_reference): Call
d_comdat_linkage on generated decl.

amdgcn: generalize vector insn modes

Replace all relevant explicit uses of V64 vectors with an iterator (albeit
with only one entry). This is prerequisite to adding extra vector lengths.

The changes are purely mechanical: comparing the mddump files from before
and after shows only white-space differences and the use of GET_MODE_NUNITS.

2020-03-31 Andrew Stubbs <ams@codesourcery.com>

gcc/
* config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
New mode iterators.
(vnsi, VnSI, vndi, VnDI): New mode attributes.
(mov<mode>): Use <VnDI> in place of V64DI.
(mov<mode>_exec): Likewise.
(mov<mode>_sgprbase): Likewise.
(reload_out<mode>): Likewise.
(*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
(gather_load<mode>v64si): Rename to ...
(gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
and <VnDI> in place of V64DI.
(gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
(gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
(gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
(scatter_store<mode>v64si): Rename to ...
(scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
(scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
(scatter<mode>_insn_1offset<exec_scatter>): Likewise.
(scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
(scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
(ds_bpermute<mode>): Use <VnSI>.
(addv64si3_vcc<exec_vcc>): Rename to ...
(add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
(addv64si3_vcc_dup<exec_vcc>): Rename to ...
(add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
(addcv64si3<exec_vcc>): Rename to ...
(addc<mode>3<exec_vcc>): ... this, and use V_SI.
(subv64si3_vcc<exec_vcc>): Rename to ...
(sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
(subcv64si3<exec_vcc>): Rename to ...
(subc<mode>3<exec_vcc>): ... this, and use V_SI.
(addv64di3): Rename to ...
(add<mode>3): ... this, and use V_DI.
(addv64di3_exec): Rename to ...
(add<mode>3_exec): ... this, and use V_DI.
(subv64di3): Rename to ...
(sub<mode>3): ... this, and use V_DI.
(subv64di3_exec): Rename to ...
(sub<mode>3_exec): ... this, and use V_DI.
(addv64di3_zext): Rename to ...
(add<mode>3_zext): ... this, and use V_DI and <VnSI>.
(addv64di3_zext_exec): Rename to ...
(add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
(addv64di3_zext_dup): Rename to ...
(add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
(addv64di3_zext_dup_exec): Rename to ...
(add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
(addv64di3_zext_dup2): Rename to ...
(add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
(addv64di3_zext_dup2_exec): Rename to ...
(add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
(addv64di3_sext_dup2): Rename to ...
(add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
(addv64di3_sext_dup2_exec): Rename to ...
(add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
(<su>mulv64si3_highpart<exec>): Rename to ...
(<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
(mulv64di3): Rename to ...
(mul<mode>3): ... this, and use V_DI and <VnSI>.
(mulv64di3_exec): Rename to ...
(mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
(mulv64di3_zext): Rename to ...
(mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
(mulv64di3_zext_exec): Rename to ...
(mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
(mulv64di3_zext_dup2): Rename to ...
(mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
(mulv64di3_zext_dup2_exec): Rename to ...
(mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
(<expander>v64di3): Rename to ...
(<expander><mode>3): ... this, and use V_DI and <VnSI>.
(<expander>v64di3_exec): Rename to ...
(<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
(<expander>v64si3<exec>): Rename to ...
(<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
(v<expander>v64si3<exec>): Rename to ...
(v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
(<expander>v64si3<exec>): Rename to ...
(<expander><vnsi>3<exec>): ... this, and use V_SI.
(subv64df3<exec>): Rename to ...
(sub<mode>3<exec>): ... this, and use V_DF.
(truncv64di<mode>2): Rename to ...
(trunc<vndi><mode>2): ... this, and use <VnDI>.
(truncv64di<mode>2_exec): Rename to ...
(trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
(<convop><mode>v64di2): Rename to ...
(<convop><mode><vndi>2): ... this, and use <VnDI>.
(<convop><mode>v64di2_exec): Rename to ...
(<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
(vec_cmp<u>v64qidi): Rename to ...
(vec_cmp<u><mode>di): ... this, and use <VnSI>.
(vec_cmp<u>v64qidi_exec): Rename to ...
(vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
(vcond_mask_<mode>di): Use <VnDI>.
(maskload<mode>di): Likewise.
(maskstore<mode>di): Likewise.
(mask_gather_load<mode>v64si): Rename to ...
(mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
(mask_scatter_store<mode>v64si): Rename to ...
(mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
(*<reduc_op>_dpp_shr_v64di): Rename to ...
(*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
(*plus_carry_in_dpp_shr_v64si): Rename to ...
(*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
(*plus_carry_dpp_shr_v64di): Rename to ...
(*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
(vec_seriesv64si): Rename to ...
(vec_series<mode>): ... this, and use V_SI.
(vec_seriesv64di): Rename to ...
(vec_series<mode>): ... this, and use V_DI.

arc: Update operand printing

Use HOST_WIDE_INT_PRINT_DEC macro instead of %ld for format printing.

gcc/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>

* config/arc/arc.c (arc_print_operand): Use
HOST_WIDE_INT_PRINT_DEC macro.

arc: Cleanup compilation warning

gcc/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>

* config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.

[ARM][PATCH]: Add MVE ACLE intrinsics vbicq_n_* polymorphic variant support.

For the following MVE ACLE intrinsics, polymorphic variant support is missing on the trunk.

vbicq_n_s16, vbicq_n_s32, vbicq_n_u16 and vbicq_n_u32.

This patch add the polymorphic variant support for above intrinsics.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

* config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
variant.
(__arm_vbicq): Likewise.

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Modify.
* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.

arc: Allow more ABIs in GLIBC_DYNAMIC_LINKER

Enable big-endian suffixed dynamic linker per glibc multi-abi support.

And to avoid a future churn and version pairingi hassles, also allow
arc700 although glibc for ARC currently doesn't support it.

gcc/
xxxx-xx-xx Vineet Gupta <vgupta@synopsys.com>

* config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700

[ARM][PATCH]: Add support for MVE ACLE intrinsics polymorphic variants for +mve.fp option.

For the following MVE ACLE intrinsics, polymorphic variant supports only +mve option, support for +mve.fp is missing.

vabavq_p_s16, vabavq_p_s32, vabavq_p_s8, vabavq_p_u16, vabavq_p_u32, vabavq_p_u8, vabavq_s16, vabavq_s32, vabavq_s8, vabavq_u16, vabavq_u32, vabavq_u8, vaddlvaq_p_s32, vaddlvaq_p_u32, vaddlvaq_s32, vaddlvaq_u32, vaddlvq_p_s32, vaddlvq_p_u32, vaddlvq_u32, vaddvaq_p_s16, vaddvaq_p_s32, vaddvaq_p_s8, vaddvaq_p_u16, vaddvaq_p_u32, vaddvaq_p_u8, vaddvaq_s16, vaddvaq_s32, vaddvaq_s8, vaddvaq_u16, vaddvaq_u32, vaddvaq_u8, vaddvq_p_s16, vaddvq_p_s32, vaddvq_p_s8, vaddvq_p_u16, vaddvq_p_u32, vaddvq_p_u8, vaddvq_s8, vaddvq_u16, vaddvq_u32, vaddvq_u8, vcmpcsq_m_n_u16, vcmpcsq_m_n_u32, vcmpcsq_m_n_u8, vcmpcsq_m_u16, vcmpcsq_m_u32, vcmpcsq_m_u8, vcmpcsq_n_u16, vcmpcsq_n_u32, vcmpcsq_n_u8, vcmpcsq_u16, vcmpcsq_u32, vcmpcsq_u8, vcmpeqq_n_f16, vcmpeqq_n_f32, vcmpgeq_m_n_s16, vcmpgeq_m_n_s32, vcmpgeq_m_n_s8, vcmpgtq_m_n_f16, vcmpgtq_m_n_f32, vcmpgtq_n_f16, vcmpgtq_n_f32, vcmphiq_m_n_u16, vcmphiq_m_n_u32, vcmphiq_m_n_u8, vcmphiq_m_u16, vcmphiq_m_u32, vcmphiq_m_u8, vcmphiq_n_u16, vcmphiq_n_u32, vcmphiq_n_u8, vcmphiq_u16, vcmphiq_u32, vcmphiq_u8, vcmpleq_m_n_f16, vcmpleq_m_n_f32, vcmpleq_n_f16, vcmpleq_n_f32, vcmpltq_m_n_f16, vcmpltq_m_n_f32, vcmpneq_m_n_f16, vcmpneq_m_n_f32, vcmpneq_n_f16, vcmpneq_n_f32, vmaxavq_p_s16, vmaxavq_p_s32, vmaxavq_p_s8, vmaxavq_s16, vmaxavq_s32, vmaxavq_s8, vmaxq_x_s16, vmaxq_x_s32, vmaxq_x_s8, vmaxq_x_u16, vmaxq_x_u32, vmaxq_x_u8, vmaxvq_p_s16, vmaxvq_p_s32, vmaxvq_p_s8, vmaxvq_p_u16, vmaxvq_p_u32, vmaxvq_p_u8, vmaxvq_s16, vmaxvq_s32, vmaxvq_s8, vmaxvq_u16, vmaxvq_u32, vmaxvq_u8, vminavq_p_s16, vminavq_p_s32, vminavq_p_s8, vminavq_s16, vminavq_s32, vminavq_s8, vminq_x_s16, vminq_x_s32, vminq_x_s8, vminq_x_u16, vminq_x_u32, vminq_x_u8, vminvq_p_s16, vminvq_p_s32, vminvq_p_s8, vminvq_p_u16, vminvq_p_u32, vminvq_p_u8, vminvq_s16, vminvq_s32, vminvq_s8, vminvq_u16, vminvq_u32, vminvq_u8, vmladavaq_p_s16, vmladavaq_p_s32, vmladavaq_p_s8, vmladavaq_p_u16, vmladavaq_p_u32, vmladavaq_p_u8, vmladavaq_s16, vmladavaq_s32, vmladavaq_s8, vmladavaq_u16, vmladavaq_u32, vmladavaq_u8, vmladavaxq_s16, vmladavaxq_s32, vmladavaxq_s8, vmladavq_p_s16, vmladavq_p_s32, vmladavq_p_s8, vmladavq_p_u16, vmladavq_p_u32, vmladavq_p_u8, vmladavq_s16, vmladavq_s32, vmladavq_s8, vmladavq_u16, vmladavq_u32, vmladavq_u8, vmladavxq_p_s16, vmladavxq_p_s32, vmladavxq_p_s8, vmladavxq_s16, vmladavxq_s32, vmladavxq_s8, vmlaldavaq_s16, vmlaldavaq_s32, vmlaldavaq_u16, vmlaldavaq_u32, vmlaldavaxq_s16, vmlaldavaxq_s32, vmlaldavq_p_s16, vmlaldavq_p_s32, vmlaldavq_p_u16, vmlaldavq_p_u32, vmlaldavq_s16, vmlaldavq_s32, vmlaldavq_u16, vmlaldavq_u32, vmlaldavxq_p_s16, vmlaldavxq_p_s32, vmlsdavaq_s16, vmlsdavaq_s32, vmlsdavaq_s8, vmlsdavaxq_s16, vmlsdavaxq_s32, vmlsdavaxq_s8, vmlsdavq_p_s16, vmlsdavq_p_s32, vmlsdavq_p_s8, vmlsdavq_s16, vmlsdavq_s32, vmlsdavq_s8, vmlsdavxq_p_s16, vmlsdavxq_p_s32, vmlsdavxq_p_s8, vmlsdavxq_s16, vmlsdavxq_s32, vmlsdavxq_s8, vmlsldavaq_s16, vmlsldavaq_s32, vmlsldavaxq_s16, vmlsldavaxq_s32, vmlsldavq_p_s16, vmlsldavq_p_s32, vmlsldavq_s16, vmlsldavq_s32, vmlsldavxq_p_s16, vmlsldavxq_p_s32, vmlsldavxq_s16, vmlsldavxq_s32, vmovlbq_x_s16, vmovlbq_x_s8, vmovlbq_x_u16, vmovlbq_x_u8, vmovltq_x_s16, vmovltq_x_s8, vmovltq_x_u16, vmovltq_x_u8, vmulhq_x_s16, vmulhq_x_s32, vmulhq_x_s8, vmulhq_x_u16, vmulhq_x_u32, vmulhq_x_u8, vmullbq_int_x_s16, vmullbq_int_x_s32, vmullbq_int_x_s8, vmullbq_int_x_u16, vmullbq_int_x_u32, vmullbq_int_x_u8, vmullbq_poly_x_p16, vmullbq_poly_x_p8, vmulltq_int_x_s16, vmulltq_int_x_s32, vmulltq_int_x_s8, vmulltq_int_x_u16, vmulltq_int_x_u32, vmulltq_int_x_u8, vmulltq_poly_x_p16, vmulltq_poly_x_p8, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vrmlaldavhaxq_s32, vrmlaldavhq_p_s32, vrmlaldavhq_p_u32, vrmlaldavhq_s32, vrmlaldavhq_u32, vrmlaldavhxq_p_s32, vrmlaldavhxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vrmlsldavhq_p_s32, vrmlsldavhq_s32, vrmlsldavhxq_p_s32, vrmlsldavhxq_s32, vstrbq_p_s16, vstrbq_p_s32, vstrbq_p_s8, vstrbq_p_u16, vstrbq_p_u32, vstrbq_p_u8, vstrbq_s16, vstrbq_s32, vstrbq_s8, vstrbq_scatter_offset_p_s16, vstrbq_scatter_offset_p_s32, vstrbq_scatter_offset_p_s8, vstrbq_scatter_offset_p_u16, vstrbq_scatter_offset_p_u32, vstrbq_scatter_offset_p_u8, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s8, vstrbq_scatter_offset_u16, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u8, vstrbq_u16, vstrbq_u32, vstrbq_u8, vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64,
vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64,
vstrdq_scatter_shifted_offset_u64.

This patch adds the support for MVE ACLE intrinsics polymorphic variants with +mve.fp option.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

* config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
common section of both MVE Integer and MVE Floating Point.
(vaddvq): Likewise.
(vaddlvq_p): Likewise.
(vaddvaq): Likewise.
(vaddvq_p): Likewise.
(vcmpcsq): Likewise.
(vmlsdavxq): Likewise.
(vmlsdavq): Likewise.
(vmladavxq): Likewise.
(vmladavq): Likewise.
(vminvq): Likewise.
(vminavq): Likewise.
(vmaxvq): Likewise.
(vmaxavq): Likewise.
(vmlaldavq): Likewise.
(vcmphiq): Likewise.
(vaddlvaq): Likewise.
(vrmlaldavhq): Likewise.
(vrmlaldavhxq): Likewise.
(vrmlsldavhq): Likewise.
(vrmlsldavhxq): Likewise.
(vmlsldavxq): Likewise.
(vmlsldavq): Likewise.
(vabavq): Likewise.
(vrmlaldavhaq): Likewise.
(vcmpgeq_m_n): Likewise.
(vmlsdavxq_p): Likewise.
(vmlsdavq_p): Likewise.
(vmlsdavaxq): Likewise.
(vmlsdavaq): Likewise.
(vaddvaq_p): Likewise.
(vcmpcsq_m_n): Likewise.
(vcmpcsq_m): Likewise.
(vmladavxq_p): Likewise.
(vmladavq_p): Likewise.
(vmladavaxq): Likewise.
(vmladavaq): Likewise.
(vminvq_p): Likewise.
(vminavq_p): Likewise.
(vmaxvq_p): Likewise.
(vmaxavq_p): Likewise.
(vcmphiq_m): Likewise.
(vaddlvaq_p): Likewise.
(vmlaldavaq): Likewise.
(vmlaldavaxq): Likewise.
(vmlaldavq_p): Likewise.
(vmlaldavxq_p): Likewise.
(vmlsldavaq): Likewise.
(vmlsldavaxq): Likewise.
(vmlsldavq_p): Likewise.
(vmlsldavxq_p): Likewise.
(vrmlaldavhaxq): Likewise.
(vrmlaldavhq_p): Likewise.
(vrmlaldavhxq_p): Likewise.
(vrmlsldavhaq): Likewise.
(vrmlsldavhaxq): Likewise.
(vrmlsldavhq_p): Likewise.
(vrmlsldavhxq_p): Likewise.
(vabavq_p): Likewise.
(vmladavaq_p): Likewise.
(vstrbq_scatter_offset): Likewise.
(vstrbq_p): Likewise.
(vstrbq_scatter_offset_p): Likewise.
(vstrdq_scatter_base_p): Likewise.
(vstrdq_scatter_base): Likewise.
(vstrdq_scatter_offset_p): Likewise.
(vstrdq_scatter_offset): Likewise.
(vstrdq_scatter_shifted_offset_p): Likewise.
(vstrdq_scatter_shifted_offset): Likewise.
(vmaxq_x): Likewise.
(vminq_x): Likewise.
(vmovlbq_x): Likewise.
(vmovltq_x): Likewise.
(vmulhq_x): Likewise.
(vmullbq_int_x): Likewise.
(vmullbq_poly_x): Likewise.
(vmulltq_int_x): Likewise.
(vmulltq_poly_x): Likewise.
(vstrbq): Likewise.

gcc/testsuite/ChangeLog:

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Modify.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.

aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]

The following testcase ICEs in final_scan_insn_1.  The problem is in the
@aarch64_compare_and_swaphi define_insn_and_split, since 9 it uses
aarch64_plushi_operand predicate for the "expected value" operand, which
allows either 0..0xfff constants or 0x1000..0xf000 constants (i.e. HImode
values which when zero extended are either 0..0xfff or (0..0xfff) << 12).
The problem is that RA doesn't care about predicates, it honors just
constraints and the used constraint on the operand is n, which means any
HImode CONST_SCALAR_INT.  In the testcase LRA thus propagates the -1
value into the insn.
This is a define_insn_and_split which requires mandatory split.
But during split2 pass, we check the predicate (and don't check
constraints), which fails and thus we don't split it and during final ICE
because the mandatory splitting didn't happen.

The following patch fixes it by adding a matching constraint to the
predicate and using it.

2020-03-31  Jakub Jelinek  <jakub@redhat.com>

PR target/94368
* config/aarch64/constraints.md (Uph): New constraint.
* config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
(@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
constraint.

* gcc.dg/pr94368.c: New test.

fold-const: Fix division folding with vector operands [PR94412]

The following testcase is miscompiled since 4.9, we treat unsigned
vector types as if they were signed and "optimize" negations across it.

2020-03-31 Marc Glisse <marc.glisse@inria.fr>
Jakub Jelinek <jakub@redhat.com>

PR middle-end/94412
* fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.

* gcc.c-torture/execute/pr94412.c: New test.

Co-authored-by: Marc Glisse <marc.glisse@inria.fr>

store-merging: Allow enums during bswap recognition [PR94403]

The following testcase is optimized with char/unsigned char/signed char,
but not with std::byte. The following patch fixes that. Didn't use
INTEGRAL_TYPE_P because bswapping bools is just too weird.

2020-03-31 Jakub Jelinek <jakub@redhat.com>

PR tree-optimization/94403
* gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
ENUMERAL_TYPE lhs_type.

* g++.dg/tree-ssa/pr94403.C: New test.

forwprop: Pattern recognize more rotates [PR94344]

The following patch adjusts simplify_rotate to recognize more rotates,
basically we allow even some same precision integral -> integral
conversions, with the requirement that the RSHIFT_EXPR operand has to be
done in unsigned type (i.e. logical right shift), so that we compensate for
the combiner no longer being able to simplify those into rotates on some
targets.

2020-03-31 Jakub Jelinek <jakub@redhat.com>

PR rtl-optimization/94344
* tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
conversions, either on both operands of |^+ or just one. Handle
also extra same precision conversion on RSHIFT_EXPR first operand
provided RSHIFT_EXPR is performed in unsigned type.

* gcc.dg/pr94344.c: New test.

lra: set insn_code_data to NULL when freeing

libgccjit's test-threads.c repeatedly compiles and runs numerous tests,
each in a separate thread.

Attempting to add an empty test that generates no code leads to a
double-free ICE within that thread, within lra.c's
finish_insn_code_data_once.

The root cause is that the insn_code_data array is cleared in
init_insn_code_data_once, but this is only called the first time
a cgraph_node is expanded [1], whereas the "loop-over-all-elements
and free them" is unconditionally called in finalize [2].  Hence
if there are no functions:
* the array is not re-initialized for the empty context
* when finish_insn_code_data_once is called for the empty context
it still contains the freed pointers from the previous context
that held the jit mutex, and hence the free is a double-free.

This patch sets the pointers to NULL after freeing them, fixing
the ICE.

[1]
init_insn_code_data_once is called via
  lra_init_once called by
    ira_init_once called by
      initialize_rtl, via:
         if (!rtl_initialized)
           ira_init_once ();
        called by init_function_start
           called by cgraph_node::expand

[2]:
finish_insn_code_data_once is called by:
  lra_finish_once called by
    finalize

gcc/ChangeLog:
* lra.c (finish_insn_code_data_once): Set the array elements
to NULL after freeing them.

gcc/testsuite/ChangeLog:
* jit.dg/all-non-failing-tests.h: Add test-empty.c

Daily bump.

Update gcc sv.po.

* sv.po: Update.

c++: Fix comparison of fn() and ns::fn() [PR90711]

The resolution of CWG issue 1321 clarified that when deciding whether two
expressions involving template parameters are equivalent, two dependent
function calls where the function is named with an unqualified-id are
considered to be equivalent if the name is the same, even if unqualified
lookup finds different sets of functions.  We were wrongly treating
qualified-ids the same way, so that EXISTS and test::EXISTS were considered
to be equivalent even though they are looking up the name in different
scopes.  This also causes a mangling bug, but I don't think it's safe to fix
that for GCC 10; this patch just fixes the comparison.

gcc/cp/ChangeLog
2020-03-30  Jason Merrill  <jason@redhat.com>

PR c++/90711
* tree.c (cp_tree_equal) [CALL_EXPR]: Compare KOENIG_LOOKUP_P.
(called_fns_equal): Check DECL_CONTEXT.

c++: Fix handling of internal fn calls in statement expressions [PR94385]

The following testcase ICEs, because the FE when processing the statement
expression changes the .VEC_CONVERT internal fn CALL_EXPR into .PHI call.
That is because the internal fn call is recorded in the base.u.ifn
field, which overlaps base.u.bits.lang_flag_1 which is used for
STMT_IS_FULL_EXPR_P, so this essentially does ifn |= 2 on little-endian.
STMT_IS_FULL_EXPR_P bit is used in:
cp-gimplify.c-  if (STATEMENT_CODE_P (code))
cp-gimplify.c-    {
cp-gimplify.c-      saved_stmts_are_full_exprs_p = stmts_are_full_exprs_p ();
cp-gimplify.c-      current_stmt_tree ()->stmts_are_full_exprs_p
cp-gimplify.c:        = STMT_IS_FULL_EXPR_P (*expr_p);
cp-gimplify.c-    }
and
pt.c-  if (STATEMENT_CODE_P (TREE_CODE (t)))
pt.c:    current_stmt_tree ()->stmts_are_full_exprs_p = STMT_IS_FULL_EXPR_P (t);
so besides being wrong on some other codes, it actually isn't beneficial at
all to set it on anything else, so the following patch restricts it to
trees with STATEMENT_CODE_P TREE_CODE.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

PR c++/94385
* semantics.c (add_stmt): Only set STMT_IS_FULL_EXPR_P on trees with
STATEMENT_CODE_P code.

* c-c++-common/pr94385.c: New test.

Define TRY_EMPTY_VM_SPACE for riscv64-linux

* config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
Define.

RS6000 Allow builtin initialization regardless of mask

  Disable the code that limits initialization of builtins based
on the rs6000_builtin_mask.  This allows all built-ins to be
properly referenced when building code using #pragma for cpu
targets newer than what was specified by the -mcpu default.
The use of built-ins is still properly limited by logic within
altivec_resolve_overloaded_builtin().

2020-03-30  Will Schmidt  <will_schmidt@vnet.ibm.com>

gcc/
    * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
    to skip defining builtins based on builtin_mask.

gcc/testsuite/
    * gcc.target/powerpc/pragma_power6.c: New.
    * gcc.target/powerpc/pragma_power7.c: New.
    * gcc.target/powerpc/pragma_power8.c: New.
    * gcc.target/powerpc/pragma_power9.c: New.
    * gcc.target/powerpc/pragma_misc9.c: New.
    * gcc.target/powerpc/vsu/vec-all-nez-7.c: Update error message.
    * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Update error message.

Update bswap64-4 test for desired results

Update existing testcase powerpc/bswap64-4.c to
reflect that we generate ldbrx and stdbrx instructions
for newer cpu targets, versus the pair of lwbrx and stwbrx
instructions as seen on previous cpu targets.

2020-03-24 Will Schmidt <will_schmidt@vnet.ibm.com>

gcc/testsuite/
* gcc.target/powerpc/bswap64-4.c: Update scan-assembler
expected results.

i386: Fix up *one_cmplv*2* insn with avx512f [PR94343]

This define_insn has two issues.
One is that with -mavx512f -mno-avx512vl it can emit an AVX512VL-only insn
- 128-bit or 256-bit EVEX encoded vpternlog{d,q}.
Another one is that because there is no vpternlog{b,w}, we emit vpternlogd
instead, but then we shouldn't pretend we support masking of that, because
we don't.
The first one can be fixed by forcing the use of %zmm* registers instead of
%xmm* or %ymm* if AVX512F but not AVX512VL, like we do for a couple of other
insns (although that is primarily done in order to support %xmm16+ regs).
But we need to make sure that in that case the input operand isn't memory,
because while we can read and store the higher bits of registers, we don't
want to read from memory more bytes than what we should read.

A variant to these two if_then_else set attrs, condition in the output and
larger condition would be 4 different define_insns (one with something like
VI48_AVX512VL iterator, masking, no g modifiers and "vm" input constraint,
another one with VI48_AVX iterator, !TARGET_AVX512VL in condition,
no masking, g modifiers and "v" input constraint, one with VI12_AVX512VL
iterator, no masking, no g modifiers and "vm" input constraint and last one with
VI12_AVX2 iterator, !TARGET_AVX512VL in condition, no masking, g modifiers
and "v" input constraint, but I think having one pattern is shorter than
that.

2020-03-30 Jakub Jelinek <jakub@redhat.com>

PR target/94343
* config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
!TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
operand is a register. Don't enable masked variants for V*[QH]Imode.

* gcc.target/i386/avx512f-pr94343.c: New test.
* gcc.target/i386/avx512vl-pr94343.c: New test.

XFAIL pr57193.c test-case.

PR rtl-optimization/87716
* gcc.target/i386/pr57193.c: XFAIL a test-case.

Fix scan pattern of vect-8.f90 dump.

PR testsuite/94402
* gfortran.dg/vect/vect-8.f90: Allow 22 or 23 loops
to be vectorized (based on libmvec presence).

Fix vextract* masked patterns [PR93069]

The AVX512F documentation clearly states that in instructions where the
destination is a memory only merging-masking is possible, not zero-masking,
and the assembler enforces that.

The testcase in this patch fails to assemble because of
Error: unsupported masking for `vextracti32x8'
on
vextracti32x8 $0x0, %zmm1, -64(%rsp){%k1}{z}
For the vector extraction patterns, we apparently have 7 *_maskm patterns
that only accept memory destinations and rtx_equal_p merge-masking source
for it, 7 *<mask_name> corresponding patterns that allow memory destination
only for the non-masked cases (through <store_mask_constraint>), then 2
*<mask_name> patterns (lo ssehalf V16FI and lo ssehalf VI8F_256 ones) which
do allow memory destination even for masked cases and are the cause of the
testsuite failure, because we must not allow C constraint if the destination
is m, and finally one pair of patterns (separate * and *_mask, hi ssehalf
VI4F_256), which has another issue (for which I don't have a testcase
though), where if it would match zero-masking with register destination,
it wouldn't emit the needed {z} into assembly.
The attached patch fixes those 3 issues only, perhaps more suitable for
backporting.

2020-03-30 Jakub Jelinek <jakub@redhat.com>

PR target/93069
* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
<store_mask_constraint> instead of m in output operand constraint.
(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
%{%3%}.

* gcc.target/i386/avx512vl-pr93069.c: New test.
* gcc.dg/vect/pr93069.c: New test.

[RS6000] Put call cookie back in AIX/ELFv2 call patterns

-mlongcall -mno-pltseq is supposed to emit long calls by using
indirect calls.  It differs from -mlongcall -mpltseq in that the
function addresses are not placed in the PLT and thus lazy PLT
resolution is not available, affecting programs that dlopen shared
libraries.

In the case of -mcpu=future -mpcrel -mlongcall -mno-pltseq we see an
indirect call being generated, but combine merrily optimises the
sequence back to a direct call.  call_indirect_pcrel is enough like
call_nonlocal_aix that this can happen.

This patch puts the call cookie back in the call rtl, removed by git
commit f90f960ca8, in order to disable the optimisation for long
calls.  When that is done for call_local_aix the pattern becomes the
same as call_local32/64, so I merged them.  The only difference
besides mode between call_local32 and call_local64, dating back to
1998 commit a260abc996, is that call_local64 has TARGET_64BIT in the
predicate.  That alone doesn't seem reason enough to need separate
patterns; The P mode iterator selects DI on TARGET_64BIT anyway.

* config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
(rs6000_indirect_call_template_1): Adjust to suit.
* config/rs6000/rs6000.md (call_local): Merge call_local32,
call_local64, and call_local_aix.
(call_value_local): Simlarly.
(call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
and disable pattern when CALL_LONG.
(call_indirect_aix, call_value_indirect_aix): Adjust rtl.
(call_indirect_elfv2, call_indirect_pcrel): Likewise.
(call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.

Daily bump.

doc: Update -falign-functions/-falign-loops/-falign-jumps

Change -falign-functions=N to

    Align the start of functions to the next power-of-two greater than
    or equal to N.

Add

    If '-falign-labels' is greater than this value, then its value is
    used instead.

to -falign-loops=N and -falign-jumps=N.

PR driver/94381
* doc/invoke.texi: Update -falign-functions, -falign-loops and
-falign-jumps documentation.

testsuite: Handle more kinds of gdc.test test flags and directives.

This patch adds cases for JSON and D header file generation flags in the
testsuite, and sets up the test accordingly to only compile, then check
that the expected output file exists.

Support has also been added for the DFLAGS test directive, which
disables testing with all default flag permutations.

gcc/testsuite/ChangeLog:

* lib/gdc-utils.exp: (gdc-convert-args): Handle compilation test
arguments -D, -H, -X, and set compilable_output_file_ext.
(gdc-convert-test): Document and add cases DFLAGS and
EXTRA_CPP_SOURCES. Add dg-final entry for output generation tests,
and set compilable_do_what to compile.
(gdc-do-test): Define compilable_do_what, default to assemble.

testsuite: Move C++ tests in gdc.test into own subdirectory.

Tests have been moved into runnable_cxx as part of upstream dmd 3e10e2dd2.

The extra flags required for tests that mix C++ and D are now limited to
only a small subset of tests, rather than applied to all tests across
gdc.dg and gdc.test.

Reviewed-on: https://github.com/dlang/dmd/pull/10980

gcc/testsuite/ChangeLog:

* gdc.test/runnable_cxx/runnable_cxx.exp: New file.
* lib/gdc-utils.exp (gdc-do-test): Add case for runnable_cxx.
* lib/gdc.exp (gdc_include_flags): Only add flags for libstdc++-v3 if
GDC_INCLUDE_CXX_FLAGS is true.
(gdc_link_flags): Likewise.
(gdc_init): Move setting of default gdc test flags to...
(gdc_target_compile): ...here.

Fix typo in a warning related to flatten.

PR ipa/94363
* cgraphunit.c (process_function_and_variable_attributes): Remove
double 'attribute' words.

Delete duplicate .align output.

2020-03-29 John David Anglin <dave.anglin@bell.net>

* gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
.align output.

testsuite: Split up gdc-test.exp into each subdirectory

Use multiple test scripts, one for each subdirectory containing test
files, instead of having one test script to manage them all.

This allows removing some workarounds, such as the need to create
symlinks in the test run directory.

gcc/testsuite/ChangeLog:

* gdc.test/compilable/compilable.exp: New file.
* gdc.test/fail_compilation/fail_compilation.exp: New file.
* gdc.test/gdc-test.exp: Remove.
* gdc.test/runnable/runnable.exp: New file.
* lib/gdc-utils.exp: ...this. Remove load_lib gdc-dg.exp.
(dmd2dg): Rename to...
(gdc-convert-test): ...this.
(gdc-do-test): Add testcases parameter and remove subdir handling.

Daily bump.

libstdc++: Fix two tests that fail in C++20 mode

* testsuite/20_util/is_constructible/value-2.cc: Fix test to account
for changes due to parenthesized aggregate-initialization in C++20.
* testsuite/20_util/time_point/cons/81468.cc: Fix test to not clash
with std::chrono::sys_time in C++20.

libstdc++: Fix std::reverse_iterator relational operators

My recent changes to reverse_iterator's comparisons was not the version
of the code (or tests) that I meant to commit, and broke the relational
operators. This fixes them to reverse the order of the comparisons on
the base() iterators.

This also replaces the SFINAE constraints in the return type of the
reverse_iterator and move_iterator comparisons with a requires-clause.
This ensures the constrained overloads are preferred to unconstrained
ones. This means the non-standard same-type overloads can be omitted for
C++20 because they're not needed to solve the problem with std::rel_ops
or the testsuite's greedy_ops::X type.

* include/bits/stl_iterator.h (reverse_iterator): Use requires-clause
to constrain C++20 versions of comparison operators. Fix backwards
logic of relational operators.
(move_iterator): Use requires-clause to constrain comparison operators
in C++20. Do not declare non-standard same-type overloads for C++20.
* testsuite/24_iterators/move_iterator/rel_ops_c++20.cc: Check result
of comparisons and check using greedy_ops type.
* testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc: Likewise.
* testsuite/24_iterators/move_iterator/greedy_ops.cc: Remove redundant
main function from compile-only test.
* testsuite/24_iterators/reverse_iterator/greedy_ops.cc: Likewise.

testsuite: adjust modulo-sched compare-debug tests

Without this patch tortured tests eventually fail because of another
known issue which I plan to fix later in stage1.

* gcc.dg/torture/pr87197-debug-sms.c: Move to ...
* gcc.dg/sms-compare-debug-1.c: ... this. Add -O2.
* gcc.c-torture/execute/pr70127-debug-sms.c: Move to ...
* gcc.dg/sms-compare-debug-2.c: ... this. Add -O2.

Patch for PR94246

[Fortran] Fix result-variable handling of MODULE PROCEDURE (PR94348)

PR fortran/94348
* decl.c (gfc_match_submod_proc): Add result var to the
proc's namespace.

PR fortran/94348
* gfortran.dg/module_procedure_3.f90: New.

c++: Diagnose when "requires" is used instead of "requires requires" [PR94306]

This adds support to detect and recover from the case where an opening brace
immediately follows the start of a requires-clause. So rather than emitting the
error

error: expected primary-expression before '{' token

followed by a slew of irrevelant errors, we now assume the user had intended to
write "requires requires {" and diagnose and recover accordingly.

gcc/cp/ChangeLog:

PR c++/94306
* parser.c (cp_parser_requires_clause_opt): Diagnose and recover from
"requires {" when "requires requires {" was probably intended.

gcc/testsuite/ChangeLog:

PR c++/94306
* g++.dg/concepts/diagnostic8.C: New test.

c++: requires-expression outside of a template is misevaluated [PR94252]

This PR shows that a REQUIRES_EXPR outside of a template can sometimes be
misevaluated.  This happens because the evaluation routine tsubst_requires_expr
(and diagnose_requires_expr) assumes the REQUIRES_EXPR's subtrees are templated
trees and that therefore it's safe to call tsubst_expr on them.  But this
assumption isn't valid when we've parsed a REQUIRES_EXPR outside of a template
context.  In order to make this assumption valid here, this patch sets
processing_template_decl to non-zero before parsing the body of a REQUIRES_EXPR
so that its subtrees are indeed always templated trees.

gcc/cp/ChangeLog:

PR c++/94252
* constraint.cc (tsubst_compound_requirement): Always suppress errors
from type_deducible_p and expression_convertible_p, as they're not
substitution errors.
(diagnose_atomic_constraint) <case INTEGER_CST>: Remove this case so
that we diagnose INTEGER_CST expressions of non-bool type via the
default case.
* cp-gimplify.c (cp_genericize_r) <case REQUIRES_EXPR>: New case.
* parser.c (cp_parser_requires_expression): Always parse the requirement
body as if we're processing a template, by temporarily incrementing
processing_template_decl.  Afterwards, if we're not actually in a
template context, perform semantic processing to diagnose any invalid
types and expressions.
* pt.c (tsubst_copy_and_build) <case REQUIRES_EXPR>: Remove dead code.
* semantics.c (finish_static_assert): Explain an assertion failure
when the condition is a REQUIRES_EXPR like we do when it is a concept
check.

gcc/testsuite/ChangeLog:

PR c++/94252
* g++.dg/concepts/diagnostic7.C: New test.
* g++.dg/concepts/pr94252.C: New test.
* g++.dg/cpp2a/concepts-requires18.C: Adjust to expect an additional
diagnostic.

c++: Respect current_constraint_diagnosis_depth in diagnose_compound_requirement

The previous patch tries to avoid changing our current default diagnostics. But
for the sake of consistency we arguably should also respect
current_constraint_diagnosis_depth in diagnose_compound_requirement() like we do
in the other error-replaying diagnostic routines. But doing so would be a
change to our default diagnostics behavior, so the change has been split out
into this separate patch for separate consideration.

gcc/cp/ChangeLog:

* constraint.cc (diagnose_compound_requirement): When diagnosing a
compound requirement, maybe replay the satisfaction failure, subject to
the current diagnosis depth.

gcc/testsuite/ChangeLog:

* g++.dg/concepts/diagnostic1.C: Pass -fconcepts-diagnostics-depth=2.
* g++.dg/concepts/diagnostic5.C: Adjust expected diagnostics.
* g++.dg/cpp2a/concepts-iconv1.C: Pass -fconcepts-diagnostics-depth=2.
* g++.dg/cpp2a/concepts-requires5.C: Likewise.

c++: Replay errors during diagnosis of constraint satisfaction failures

This patch adds a new flag -fconcepts-diagnostics-depth to the C++ frontend
which controls how deeply we replay errors when diagnosing a constraint
satisfaction failure.  The default is -fconcepts-diagnostics-depth=1 which
diagnoses only the topmost constraint satisfaction failure and is consistent
with our behavior before this patch.  By increasing this flag's value, the user
can control how deeply they want the compiler to explain a constraint
satisfaction error.

For example, if the unsatisfied constraint is a disjunction, then the default
behavior is to just say "no branch in the disjunction is satisfied", but with
-fconcepts-diagnostics-depth=2 we will additionally replay and diagnose the
error in each branch of the disjunction.  And if the unsatisfied constraint is a
requires expression, then we will replay the error in the requires expression,
etc.  This proceeds recursively until there is nothing more to replay or we
exceeded the maximum depth specified by the flag.

Implementation wise, this patch essentially just uncomments the existing
commented-out code that performs the error-replaying, and along the way adds
logic to keep track of and limit the current replay depth.  Besides that, there
is a new routine collect_operands_of_disjunction which flattens a disjunction
and collects all of its operands into a vector.

The extra diagnostics enabled by this flag are at times longer than they need to
be (e.g.  "the operand is_array_v<...> is unsatisfied because \n the expression
is_array_v<...> [with ...] evaluated to false") and not immediately easy to
follow (especially when there are nested disjunctions), but the transparency
provided by these optional diagnostics seems to be pretty helpful in practice.

gcc/c-family/ChangeLog:

* c.opt: Add -fconcepts-diagnostics-depth.

gcc/cp/ChangeLog:

* constraint.cc (finish_constraint_binary_op): Set the location of EXPR
as well as its range, because build_x_binary_op doesn't always do so.
(current_constraint_diagnosis_depth): New.
(concepts_diagnostics_max_depth_exceeded_p): New.
(collect_operands_of_disjunction): New.
(satisfy_disjunction): When diagnosing a satisfaction failure, maybe
replay each branch of the disjunction, subject to the current diagnosis
depth.
(diagnose_valid_expression): When diagnosing a satisfaction failure,
maybe replay the substitution error, subject to the current diagnosis
recursion.
(diagnose_valid_type): Likewise.
(diagnose_nested_requiremnet): Likewise.
(diagnosing_failed_constraint::diagnosing_failed_constraint): Increment
current_constraint_diagnosis_depth when diagnosing.
(diagnosing_failed_constraint::~diagnosing_failed_constraint): Decrement
current_constraint_diagnosis_depth when diagnosing.
(diagnosing_failed_constraint::replay_errors_p): New static member
function.
(diagnose_constraints): Don't diagnose if concepts_diagnostics_max_depth
is 0.  Emit a one-off note to increase -fconcepts-diagnostics-depth if
the limit was exceeded.
* cp-tree.h (diagnosing_failed_constraint::replay_errors_p): Declare.

gcc/testsuite/ChangeLog:

* g++.dg/concepts/diagnostic2.C: Expect "no operand" instead of
"neither operand".
* g++.dg/concepts/diagnostic5.C: New test.

c: After issuing errors about array size, for error-recovery don't make the array VLA [PR93573]

After we report various errors about array size, we set for error-recovery
the size to be 1, but because size_int_const is false, it still means we
pretend the array is a VLA, can emit a second diagnostics in that case etc.
E.g.
$ ./cc1.unpatched -quiet a.c
a.c:1:5: error: size of array ‘f’ has non-integer type
    1 | int f[100.0];
      |     ^
a.c:1:1: warning: variably modified ‘f’ at file scope
    1 | int f[100.0];
      | ^~~
$ ./cc1 -quiet a.c
a.c:1:5: error: size of array ‘f’ has non-integer type
    1 | int f[100.0];
      |     ^

2020-03-28  Jakub Jelinek  <jakub@redhat.com>

PR c/93573
* c-decl.c (grokdeclarator): After issuing errors, set size_int_const
to true after setting size to integer_one_node.

* gcc.dg/pr93573-1.c: New test.
* gcc.dg/pr93573-2.c: New test.

reassoc: Fix -fcompare-debug bug in reassociate_bb [PR94329]

The following testcase FAILs with -fcompare-debug, because reassociate_bb
mishandles the case when the last stmt in a bb has zero uses.  In that case
reassoc_remove_stmt (like gsi_remove) moves the iterator to the next stmt,
i.e. gsi_end_p is true, which means the code sets the iterator back to
gsi_last_bb.  The problem is that the for loop does gsi_prev on that before
handling the next statement, which means the former penultimate stmt, now
last one, is not processed by reassociate_bb.
Now, with -g, if there is at least one debug stmt at the end of the bb,
reassoc_remove_stmt moves the iterator to that following debug stmt and we
just do gsi_prev and continue with the former penultimate non-debug stmt,
now last non-debug stmt.

The following patch fixes that by not doing the gsi_prev in this case; there
are too many continue; cases, so I didn't want to copy over the gsi_prev to
all of them, so this patch uses a bool for that instead.  The second
gsi_end_p check isn't needed anymore, because when we don't do the
undesirable gsi_prev after gsi = gsi_last_bb, the loop !gsi_end_p (gsi)
condition will catch the removal of the very last stmt from a bb.

2020-03-28  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/94329
* tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
on the last stmt in a bb, make sure gsi_prev isn't done immediately
after gsi_last_bb.

* gfortran.dg/pr94329.f90: New test.

Daily bump.

libstdc++: Define __cpp_lib_ranges macro for C++20

Define the feature test macro now that ranges support is complete.

This also changes the preprocessor checks for the __cpp_concepts macro
so that library components depending on concepts are only enabled when
C++20 concepts are supported, and not just for the Concepts TS (which
uses different syntax in places).

* include/bits/range_cmp.h (__cpp_lib_ranges): Define.
* include/bits/stl_iterator.h: Check value of __cpp_concepts so that
C++20 concepts are required.
* include/bits/stl_iterator_base_types.h: Likewise.
* include/std/concepts: Likewise.
* include/std/version: Likewise.
* testsuite/std/ranges/headers/ranges/synopsis.cc: Check feature test
macro.

libstdc++: Add remaining C++20 changes to iterator adaptors

This adds the missing parts of P0896R4 to reverse_iterator and
move_iterator, so that they meet the C++20 requirements. This should be
the last piece of P0896R4, meaning ranges support is now complete.

The PR 94354 bug with reverse_iterator's comparisons is fixed for C++20
only, but that change should be extended to C++11, C++14 and C++17 modes
in stage 1.

* include/bits/stl_iterator.h (reverse_iterator::iterator_concept)
(reverse_iterator::iterator_category): Define for C++20.
(reverse_iterator): Define comparison operators correctly for C++20.
(__normal_iterator): Add constraints to comparison operators for C++20.
(move_iterator::operator++(int)) [__cpp_lib_concepts]: Define new
overload for input iterators.
(move_iterator): Add constraints to comparison operators for C++20.
Define operator<=> for C++20.
* testsuite/24_iterators/move_iterator/input_iterator.cc: New test.
* testsuite/24_iterators/move_iterator/move_only.cc: New test.
* testsuite/24_iterators/move_iterator/rel_ops_c++20.cc: New test.
* testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc: New test.

libstdc++: Implement C++20 changes to insert iterators

std::insert_iterator and std::inserter need to be adjusted for C++20, so
that they use ranges::iterator_t. That alias template requires
ranges::begin to be defined. Rather than moving the whole of
ranges::begin (and related details like ranges::enable_borrowed_range)
into <iterator>, this defines a new, simpler version of ranges::begin
that is sufficient for ranges::iterator_t to be defined. This works
because ranges::iterator_t uses an lvalue reference type, so the logic
in ranges::begin for non-lvalue ranges (i.e. borrowed ranges) isn't
needed.

This also adds the missing constexpr specifiers to the other insert
iterators.

* include/bits/iterator_concepts.h (__detail::__decay_copy)
(__detail::__member_begin, __detail::__adl_begin): Move here from
<bits/range_access.h>.
(__detail::__ranges_begin, __detail::__range_iter_t): Define.
* bits/range_access.h (__cust_access::__decay_copy)
(__cust_access::__member_begin, __cust_access::__adl_begin): Move to
<bits/iterator_concepts.h>.
(ranges::iterator_t): Use __detail::__range_iter_t.
* include/bits/stl_iterator.h (back_insert_iterator): Simplify
conditional compilation. Add _GLIBCXX20_CONSTEXPR to all members.
(front_insert_iterator): Likewise.
(insert_iterator): Implement changes from P0896R4 for C++20.
* testsuite/24_iterators/back_insert_iterator/constexpr.cc: New test.
* testsuite/24_iterators/front_insert_iterator/constexpr.cc: New test.
* testsuite/24_iterators/headers/iterator/synopsis_c++17.cc: Adjust
for inclusion in synopsis_c++20.cc which expects different signatures
for some function templates.
* testsuite/24_iterators/insert_iterator/constexpr.cc: New test.

libstdc++: Move definition earlier in file

This moves __is_array_convertible so it's not between
__is_nothrow_convertible and its helper, since it isn't related to
those.

* include/std/type_traits (__is_array_convertible): Move definition
to immediately after is_convertible.

Update gcc de.po.

[RS6000] PR94145, make PLT loads volatile

The PLT is volatile.  On PowerPC it is a bss style section which the
dynamic loader initialises to point at resolver stubs (called glink on
PowerPC64) to support lazy resolution of function addresses.  The
first call to a given function goes via the dynamic loader symbol
resolver, which updates the PLT entry for that function and calls the
function.  The second call, if there is one and we don't have a
multi-threaded race, will use the updated PLT entry and thus avoid
the relatively slow symbol resolver path.

Calls via the PLT are like calls via a function pointer, except that
no initialised function pointer is volatile like the PLT.  All
initialised function pointers are resolved at program startup to point
at the function or are left as NULL.  There is no support for lazy
resolution of any user visible function pointer.

So why does any of this matter to gcc?  Well, normally the PLT call
mechanism happens entirely behind gcc's back, but since we implemented
inline PLT calls (effectively putting the PLT code stub that loads the
PLT entry inline and making that code sequence scheduled), the load of
the PLT entry is visible to gcc.  That load then is subject to gcc
optimization, for example in

/* -S -mcpu=future -mpcrel -mlongcall -O2.  */
int foo (int);
void bar (void)
{
  while (foo(0))
    foo (99);
}

we see the PLT load for foo being hoisted out of the loop and stashed
in a call-saved register.  If that happens to be the first call to
foo, then the stashed value is that for the resolver stub, and every
call to foo in the loop will then go via the slow resolver path.  Not
a good idea.  Also, if foo turns out to be a local function and the
linker replaces the PLT calls with direct calls to foo then gcc has
just wasted a call-saved register.

This patch teaches gcc that the PLT loads are volatile.  The change
doesn't affect other loads of function pointers and thus has no effect
on normal indirect function calls.  Note that because the
"optimization" this patch prevents can only occur over function calls,
the only place gcc can stash PLT loads is in call-saved registers or
in other memory.  I'm reasonably confident that this change will be
neutral or positive for the "ld -z now" case where the PLT is not
volatile, in code where there is any register pressure.  Even if gcc
could be taught to recognise cases where the PLT is resolved, you'd
need to discount use of registers to cache PLT loads by some factor
involving the chance that those calls would be converted to direct
calls.

PR target/94145
* config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
for PLT16_LO and PLT_PCREL.
* config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
(UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
(pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.

c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339]

With the PR94346 fix in, we can revert the attr-copy-2.C workaround.

2020-03-27 Jakub Jelinek <jakub@redhat.com>

PR c++/94339
* g++.dg/ext/attr-copy-2.C: Revert the last changes.

PR c++/94346 - [9/10 Regression] ICE due to handle_copy_attribute since r9-3982

gcc/c-family/ChangeLog:

PR c++/94346
* c-attribs.c (handle_copy_attribute): Avoid passing expressions
to decl_attributes. Make handling of different kinds of entities
more robust.

gcc/c-c++-common/ChangeLog:

PR c++/94346
* c-c++-common/attr-copy.c: New test.

[pr84733] Fix ICE popping local scope

PR c++/84733
* name-lookup.c (do_pushdecl): Look through cleanp levels.

PR c++/94098 - ICE on attribute access redeclaration

gcc/c-family/ChangeLog:

PR c++/94098
* c-attribs.c (handle_access_attribute): Avoid setting TYPE_ATTRIBUTES
here.

gcc/ChangeLog:

PR c++/94098
* calls.c (init_attr_rdwr_indices): Iterate over all access attributes.

gcc/testsuite/ChangeLog:

PR c++/94098
* g++.dg/ext/attr-access-2.C: New test.

amdgcn: refactor mode iterators

The iterative addition of 8 and 16 bit vectors has left the mode iterators in a
bit of a mess.  Also, the original names were rather verbose leading to
formatting difficulties.

This patch renames all the vector modes such that they are shorter and tidier.
It does not change the output machine description at all.

2020-03-27  Andrew Stubbs  <ams@codesourcery.com>

gcc/
* config/gcn/gcn-valu.md:
(VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
(VEC_1REG_MODE): Delete.
(VEC_1REG_ALT): Delete.
(VEC_ALL1REG_MODE): Rename to V_1REG throughout.
(VEC_1REG_INT_MODE): Delete.
(VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
(VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
(VEC_2REG_MODE): Rename to V_2REG throughout.
(VEC_REG_MODE): Rename to V_noHI throughout.
(VEC_ALLREG_MODE): Rename to V_ALL throughout.
(VEC_ALLREG_ALT):  Rename to V_ALL_ALT throughout.
(VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
(VEC_INT_MODE): Delete.
(VEC_FP_MODE): Rename to V_FP throughout and move to top.
(VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
(FP_MODE): Delete and replace with FP throughout.
(FP_1REG_MODE): Delete and replace with FP_1REG throughout.
(VCMP_MODE): Rename to V_noQI throughout and move to top.
(VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
* config/gcn/gcn.md (FP): New mode iterator.
(FP_1REG): New mode iterator.

c++: avoid -Wredundant-tags on a first declaration in use [PR 93824]

-Wredundant-tags doesn't consider type declarations that are also
the first uses of the type, such as in 'void f (struct S);' and
issues false positives for those.  According to the reported that's
making it harder to use the warning to clean up LibreOffice.

The attached patch extends -Wredundant-tags to avoid these false
positives by relying on the same class_decl_loc_t::class2loc mapping
as -Wmismatched-tags.  The patch also improves the detection
of both issues in template declarations.

gcc/cp/ChangeLog
2020-03-27  Martin Sebor  <msebor@redhat.com>

PR c++/94078
PR c++/93824
PR c++/93810
* cp-tree.h (most_specialized_partial_spec): Declare.
* parser.c (cp_parser_elaborated_type_specifier): Distinguish alias
from declarations.
(specialization_of): New function.
(cp_parser_check_class_key): Move code...
(class_decl_loc_t::add): ...to here.  Add parameters.  Avoid issuing
-Wredundant-tags on first-time declarations in other declarators.
Correct handling of template specializations.
(class_decl_loc_t::diag_mismatched_tags): Also expect to be called
when -Wredundant-tags is enabled.  Use primary template or partial
specialization as the guide for uses of implicit instantiations.
* pt.c (most_specialized_partial_spec): Declare extern.

gcc/testsuite/ChangeLog
2020-03-27  Martin Sebor  <msebor@redhat.com>

PR c++/94078
PR c++/93824
PR c++/93810
* g++.dg/warn/Wmismatched-tags-3.C: New test.
* g++.dg/warn/Wmismatched-tags-4.C: New test.
* g++.dg/warn/Wmismatched-tags-5.C: New test.
* g++.dg/warn/Wmismatched-tags-6.C: New test.
* g++.dg/warn/Wredundant-tags-3.C: Remove xfails.
* g++.dg/warn/Wredundant-tags-6.C: New test.
* g++.dg/warn/Wredundant-tags-7.C: New test.

c++: Fix ICE after ambiguous inline namespace reopen [PR94257]

Following DR2061, 'namespace F', looks for 'F's inside inline namespaces.
That can result in ambiguous lookups that we failed to diagnose early enough,
leading us to push a new namespace and ICE later. Diagnose the ambiguity
earlier, and then pick one.

PR c++/94257
* name-lookup.c (push_namespace): Triage ambiguous lookups that
contain namespaces.