gallivm: Use MCInstrInfo in the disassembler for querying instruction info

This fixes the build since llvm r232885 and also simplifies the code.

clover: use get_device_vendor instead of get_vendor

The pipe's get_vendor method returns something more akin to a driver
vendor string in most cases, instead of the actual device vendor. Use
get_device_vendor instead, which was introduced specifically for this
purpose.

Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

gallium: implement get_device_vendor() for existing drivers

The only hackish ones are llvmpipe and softpipe, which currently return
the same string as for get_vendor(), while ideally they should return
the CPU vendor.

Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

gallium: introduce get_device_vendor() entrypoint for pipes

This will be needed by Clover to return the correct information
to CL_DEVICE_VENDOR info queries.

Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium: remove trailing whitespace in p_screen.h

Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

clover: The unit for CL_DEVICE_MEM_BASE_ADDR_ALIGN is bits not bytes

Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

clover: Add all the mandatory 1.1 extensions to the extension string

Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

clover: Add a space at the end of CL_DEVICE_OPENCL_C_VERSION

This is required by the spec.

Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/vec4: Fix handling of multiple register reads and writes in dead_code_eliminate().

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Calculate live intervals with subregister granularity.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Define helpers to calculate the common live interval of a range of variables.

These will be especially useful when we start keeping track of
liveness information for each subregister.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Define helper functions to convert a register to a variable index.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Don't lose the force_writemask_all flag during CSE.

And set it in the MOV instructions that copy the temporary to the
original destination if the generator instruction had it set.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix handling of multiple register reads and writes in opt_cse().

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix handling of multiple register reads and writes during copy propagation.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix handling of multiple register reads and writes in split_virtual_grfs().

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix handling of multiple register reads and writes in opt_register_coalesce().

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Define method to check whether a backend_reg is inside a given range.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Remove dependency of vec4_live_variables on the visitor.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Trivial copy propagate clean-up.

Fix typo and punctuation in a comment, break long line and add space
before curly bracket.

Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/vec4: Add argument index and type checks to SEL saturate propagation.

SEL saturate propagation already implicitly relies on these
assumptions.

Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/vec4: Fix broken saturate mask check in copy propagation.

try_copy_propagate() was checking the bit of the saturate mask for the
arg-th component of the source to decide whether the whole source
should be saturated (WTF?).  We need to swizzle the original saturate
mask and check that for all enabled channels the saturate flag is
either set or unset, as we cannot saturate a subset of destination
components only.

Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/vec4: Don't lose copy propagation saturate bits for not written components.

Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

Revert "i965/vec4: Don't lose the saturate modifier in copy propagation."

This reverts commit 0dfec59a2785cf7a87ee5128889ecebe810b611b.  The
change prevented propagation of copies with the saturate flag set,
making the whole saturate mask tracking completely useless.  A proper
fix follows.

Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

i965/vec4: Remove unused method definition.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Some more trivial swizzle clean-up.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Improve src_reg/dst_reg conversion constructors.

This simplifies the src_reg/dst_reg conversion constructors using the
swizzle utils introduced in a previous patch.  It also makes them more
useful by changing their semantics slightly: dst_reg(src_reg) used to
set the writemask to XYZW if the src_reg swizzle was anything other
than XXXX, which was almost certainly not what the caller intended if
the swizzle was non-trivial.  After this patch the same components
that are present in the swizzle will be enabled in the resulting
writemask.

src_reg(dst_reg) used to set the first components of the swizzle to
the enabled components of the writemask and then replicate the last
enabled component to fill the swizzle, which, in cases where the
writemask didn't have exactly the first n components set, would in
general not be compatible with the original dst_reg.  E.g.:

| ADD(tmp, src_reg(tmp), src_reg(1));

would *not* do what one would expect (add one to each of the enabled
components of tmp) if tmp didn't have a writemask of the described
form (e.g. YZ, YW, XZW would all fail).  This pattern actually occurs
in many different places in the VEC4 back-end, it's a wonder that it
hasn't caused piglit failures until now.  After this patch
src_reg(dst_reg) will construct a swizzle with each enabled component
at its natural position (e.g. Y at the second position, Z at the
third, and so on).  The resulting swizzle will behave like the
identity when used in any instruction with the original writemask.

I've manually verified that *none* of the callers of both conversion
constructors were relying on the previous broken semantics.  There are
no piglit regressions on any generation.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Pass argument by reference to src_reg/dst_reg conversion constructors.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Remove swizzle_for_size() in favour of brw_swizzle_for_size().

It could be objected that swizzle_for_size() is "faster" than
brw_swizzle_for_size().  It's not measurably better in any reasonable
CPU-bound benchmark on VLV according to the Finnish benchmarking
system (including the SynMark2 DrvShComp shader compilation
benchmark).

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Remove broken vector size deduction in setup_builtin_uniform_values().

This seemed to be trying to deduce the number of uniform vector
components from the parameter swizzle, but the algorithm would always
give 4 as result.  Instead grab the correct number of components from
the GLSL type.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Simplify visitor handling of swizzles using the swizzle utils.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Simplify opt_register_coalesce() using the swizzle utils.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Simplify reswizzle() using the swizzle utils.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Simplify opt_reduce_swizzle() using the swizzle utils.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Fix signedness of backend_reg::reg_offset.

And make it 16-bit so it packs nicely with the previous field.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix signedness of dst_reg::writemask.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Don't use GL types in the IR data structures.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/vec4: Fix signedness of brw_is_single_value_swizzle() argument.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Define some useful swizzle helper functions.

This defines helper functions implementing some common swizzle
transformations that are usually open-coded in the compiler back-end,
causing a lot of clutter.  Some optimization passes will become almost
trivial implemented in terms of these functions (e.g.
vec4_visitor::opt_reduce_swizzle()).

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: fix names in lower_constant_arrays_to_uniforms

Patch changes lowering pass to use unique name for each uniform
so that arrays from different stages cannot end up having same
name.

v2: instead of global counter, use pointer to achieve
    unique name (Kenneth Graunke)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89590
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: 10.5 10.4 <mesa-stable@lists.freedesktop.org>

i965/nir: Use signed integer type for booleans

FS instructions with NIR on i965:
total instructions in shared programs: 2663561 -> 2619051 (-1.67%)
instructions in affected programs:     1612965 -> 1568455 (-2.76%)
helped:                                5455
HURT:                                  12

FS instructions with NIR on g4x:
total instructions in shared programs: 2352633 -> 2307908 (-1.90%)
instructions in affected programs:     1441842 -> 1397117 (-3.10%)
helped:                                5463
HURT:                                  11

FS instructions with NIR on ilk:
total instructions in shared programs: 3997305 -> 3934278 (-1.58%)
instructions in affected programs:     2189409 -> 2126382 (-2.88%)
helped:                                8969
HURT:                                  22

FS instructions with NIR on hsw (snb and ivb were similar):
total instructions in shared programs: 4109389 -> 4109242 (-0.00%)
instructions in affected programs:     109869 -> 109722 (-0.13%)
helped:                                339
HURT:                                  190

No SIMD16 programs were gained or lost on any platform

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/nir: Do boolean resolves on GEN <= 5

v2: A couple comment clean-ups from Matt

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Add a NIR analysis pass for determining when a boolean resolve is needed

v2: Fix the spelling of analyze and re-arrange code for better readability
    as per Connor's comments.
v3: Make the naming of things more consistent and add a pile of comments
v4: Stop trying to avoid vectors

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

i965/nir: Properly set the predicate on the SEL used in min/max

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/nir: Use NIR lowering for ffma for gen < 6

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/nir: Use emit_lrp for emitting flrp

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Make emit_lrp return an fs_inst

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: define I915_PARAM_REVISION

we are broken against the libdrm 2.4.60 minimum specified,
so fix it for now.

Signed-off-by: Dave Airlie <airlied@redhat.com>

gallivm: Silence unused variable warnings on release builds.

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Silence conversion from 'size_t' to 'type', possible loss of data on MSVC.

Most cases seem harmless, though that might not always be the case.  Maybe
one day we can get gcc to complain about these and fix them throughout
the code, but until then let's silence them.

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Ensure inttypes.h is always pre-included on MSVC.

It's a bit hackish couldn't find another solution.  See code comment
for details.   The warning is useful, so universally disabling doesn't
sound a good idea.

Fixes

   warning C4005: 'xxx' : macro redefinition

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Silence MSVC C4351 warning.

It warns about change in MSVC behavior -- array initialisation used to
be non-standard, but is standard now, assuming I understand correctly
http://en.cppreference.com/w/cpp/language/zero_initialization .

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Match some of LLVM warning options.

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Cleanup flex/bison settings specification.

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Prefer winflexbison, and use --wincompat when available.

This avoids MSVC the warning

  warning C4013: 'isatty' undefined; assuming extern returning int

with certain versions of flex.

Reviewed-by: Brian Paul <brianp@vmware.com>
v2: Add win flex-bison link to docs/install.html.

scons: Define YY_USE_CONST on MSVC.

This prevents the MSVC from

  warning C4090: 'function' : different 'const' qualifiers

when compiling flex generated lexers.

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Tell MSVC STL library to not use exceptions.

MSVC defaults to no exceptions unless /EH option is passed (which we don't), while
MSVC's STL defaults to use exceptions unless _HAS_EXCEPTIONS=0 is defined,
which we didn't.

This fixes

  warning C4530: C++ exception handler used, but unwind semantics are not enabled. Specify /EHsc

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Ensure git_sha1.h's directory exists.

Reviewed-by: Brian Paul <brianp@vmware.com>

configure: Bail out with MinGW targets.

We only support native Windows builds with SCons.

Tested with:

  ./configure --host=i686-w64-mingw32

Reviewed-by: Brian Paul <brianp@vmware.com>

include: Ensure float.h is included for DBL_MAX.

I didn't actually hit the issue in practice, but just happen to notice
while looking at the code.

Reviewed-by: Brian Paul <brianp@vmware.com>

st/vdpau: Avoid constness cast warnings.

Fixes MSVC

  warning C4090: '=' : different 'const' qualifiers

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

glsl: Disable MSVC switch warning on a per-file basis.

This addresses

  ...\glsl_parser.cpp(...) : warning C4065: switch statement contains 'default' but no 'case' labels

This is on code generated by bison, which we have little control.

It seems useful to have this warning otherwise enabled.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Avoid GLboolean vs bool arithmetic MSVC warnings.

Note that GLboolean is an alias for unsigned char, which lacks the
implicit true/false semantics that C++/C99 bool have.

Reviewed-by: Brian Paul <brianp@vmware.com>
v2: Change gl_shader::IsES and gl_shader_program::IsES to be bool as
recommended by Ian Romanick.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

galahad: actually remove the driver

Should have been part of 429a4355259(galahad: remove driver). Seems like
I've erroneously committed the trimmed patch.

Reported-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

egl: cut down static storage size for {Version,ClientAPI}String

Both seems to be excessively long, namely:

ClientAPIString can get up-to 47 based on current code, while the name
of the driver can dictate the length of the VersionString, currently it
is around 11. Let's pad each to 100, rather than the current 1000.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

docs: note the removal of gbm_gallium, galahad and identity

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

galahad: remove driver

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium/docs: remove information about identity driver

Removed from tree.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

docs: update the egl_platforms list

Add the missing wayland, null, android and haiku platforms.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

egl/main: drop platform fbdev specific code

st/egl was the only one which had support for this platform.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

winsys/sw/fbdev: remove unused software winsys

st/egl was its only user.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

winsys/sw/wayland: remove unused winsys

st/egl was its only user.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

st/gbm: remove state-tracker

st/egl was its only user.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>

llvmpipe: use global llvm context for PIPE_SUBSYSTEM_EMBEDDED

There's 2 reasons why we'd want to use the global context:
1) There still seems to be one memory "leak" left when using multiple llvm
contexts (it is not a true leak as the memory disappears into some still
addressable pool but nevertheless the memory consumption grows). See
http://cgit.freedesktop.org/~jrfonseca/llvm-jitstress/
2) These contexts get kinda big - even when disposing modules etc. after
compiling a shader the LLVMContext can easily be over 100kB. So when there's
lots of llvm contexts arounds it adds up.

The downside is that at least right now this is absolutely not thread safe,
so this only works safely in environments where multiple pipe contexts are not
used concurrently.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

docs: add news item and link release notes for mesa 10.4.7

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: Add sha256 sums for the 10.4.7 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit cb154bb22116910c462f7a83f4401bd01e15c34d)

Add release notes for the 10.4.7 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit d26f3c1f860e267964d2bd74a86235ae702af3f4)

mesa: reorder gl_light_attrib

reduces from 2664->2656.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_framebuffer

this reduces it from 1088 -> 1080 bytes

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: fix hole in vertex_array_object

this just removes 4 bytes from this object.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: repack gl_texture_attrib.

This removes a hole, and puts the large allocation at the end,

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reduce gl_colorbuffer_attrib and gl_fog_attrib

These 392->388 and 72->68.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_image_unit

reduces 40->32
but reduces use in context from 7680->6144.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_program, gl_shader, gl_shader_program

gl_program : 1344->1336
gl_shader: 488->472
gl_shader_program: 352->344.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_transform_feedback_object

Reduces size from 184 to 176 bytes.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder prog_instruction

reduces size from 64 to 56 bytes.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_array_attrib

drops 80 bytes to 72.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_client_array

drops from 56 to 48 bytes,
drops gl_vertex_array_object from 4584 to 4320 bytes

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_texture_unit

drops size from 520 -> 512 bytes,
which then makes gl_texture_attrib go from 99984 to 98440.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_point_attrib

this drops the size from 52 bytes to 48 bytes.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: reorder gl_multisample_attrib

drops size from 28 bytes to 20.

Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965/fs: Use correct null destination register in cmod tests

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89670
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Vinson Lee <vlee@freedesktop.org>

i965/fs: bail on move-to-flag in sel peephole

Fixes a piglit regression
(shaders/glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined) with
my series for GVN.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>

i965: Mask out unused Align16 components in brw_untyped_atomic.

This is currently not a problem because the vec4 visitor happens to
mask out unused components from the destination, but it might become
an issue when we start using atomics without writeback message.  In
any case it seems sensible to set it again here because the
consequences of setting the wrong writemask (random graphics memory
corruption) are difficult to debug and can easily go unnoticed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Pass number of components explicitly to brw_untyped_atomic and _surface_read.

And calculate the message response size based on the number of
components rather than the other way around.  This simplifies their
interface somewhat and allows the caller to request a writeback
message with more than one vector component in SIMD4x2 mode.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Don't disable exec masking for sampler message sends.

This was telling the sampler to do texture fetches for *all* channels
in the non-constant surface index case, what could have reduced
throughput unnecessarily when some of the channels were disabled by
control flow.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Factor out logic to build a send message instruction with indirect descriptor.

This is going to be useful because the Gen7+ uniform and varying pull
constant, texturing, typed and untyped surface read, write, and atomic
generation code on the vec4 and fs back-end all require the same logic
to handle conditionally indirect surface indices.  In pseudocode:

|   if (surface.file == BRW_IMMEDIATE_VALUE) {
|      inst = brw_SEND(p, dst, payload);
|      set_descriptor_control_bits(inst, surface, ...);
|   } else {
|      inst = brw_OR(p, addr, surface, 0);
|      set_descriptor_control_bits(inst, ...);
|      inst = brw_SEND(p, dst, payload);
|      set_indirect_send_descriptor(inst, addr);
|   }

This patch abstracts out this frequently recurring pattern so we can
now write:

| inst = brw_send_indirect_message(p, sfid, dst, payload, surface)
| set_descriptor_control_bits(inst, ...);

without worrying about handling the immediate and indirect surface
index cases explicitly.

v2: Rebase.  Improve documentatation and commit message. (Topi)
    Preserve UW destination type cargo-cult. (Topi, Ken, Matt)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Set nr_params to the number of uniform components in the VS/GS path.

Both do_vs_prog and do_gs_prog initialize brw_stage_prog_data::nr_params to
the number of uniform *vectors* required by the shader rather than the number
of uniform components, contradicting the comment.  This is inconsistent with
what the state upload code and scalar path expect but it happens to work until
Gen8 because vec4_visitor interprets it as a number of vectors on construction
and later on overwrites its original value with the number of uniform
components referenced by the shader.

Also there's no need to add the number of samplers, they're not actually
passed in as uniforms.

Fixes a memory corruption issue on BDW with SIMD8 VS.

Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/skl: Break down SIMD16 3-source instructions when required.

Several steppings of Skylake fail when using SIMD16 with 3-source
instructions (such as MAD).

This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit
tests.

Based on a patch by Neil Roberts.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

i965: Refactor SIMD16-to-2xSIMD8 checks.

The places that were checking whether 3-source instructions are
supported have now been combined into a small helper function. This
will be used in the next patch to add an additonal restriction.

Based on a patch by Kenneth Graunke.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>