Eddie Hung [Fri, 19 Apr 2019 22:47:36 +0000 (15:47 -0700)]
Fixes for simple_abc9 tests
Eddie Hung [Fri, 19 Apr 2019 15:44:53 +0000 (08:44 -0700)]
Do not assume inst_module is always present
Eddie Hung [Fri, 19 Apr 2019 15:37:10 +0000 (08:37 -0700)]
ignore_boxes -> holes_mode
Eddie Hung [Fri, 19 Apr 2019 15:36:38 +0000 (08:36 -0700)]
Make SB_DFF whitebox
Eddie Hung [Fri, 19 Apr 2019 06:07:16 +0000 (23:07 -0700)]
Fix SB_DFF comb model
Eddie Hung [Fri, 19 Apr 2019 00:50:11 +0000 (17:50 -0700)]
Missing close bracket
Eddie Hung [Fri, 19 Apr 2019 00:46:53 +0000 (17:46 -0700)]
Annotate SB_DFF* with abc_flop and abc_box_id
Eddie Hung [Fri, 19 Apr 2019 00:46:32 +0000 (17:46 -0700)]
Add SB_DFF* to boxes
Eddie Hung [Fri, 19 Apr 2019 00:43:13 +0000 (17:43 -0700)]
Add flop support for write_xaiger
Eddie Hung [Fri, 19 Apr 2019 00:39:36 +0000 (17:39 -0700)]
read_aiger to parse 'r' extension
Eddie Hung [Fri, 19 Apr 2019 00:35:16 +0000 (17:35 -0700)]
Spelling
Eddie Hung [Thu, 18 Apr 2019 17:32:41 +0000 (10:32 -0700)]
Use new -wb flag for ABC flow
Eddie Hung [Thu, 18 Apr 2019 17:30:45 +0000 (10:30 -0700)]
write_json to not write contents (cells/wires) of whiteboxes
Eddie Hung [Thu, 18 Apr 2019 17:19:45 +0000 (10:19 -0700)]
Ignore 'whitebox' attr in flatten with "-wb" option
Eddie Hung [Thu, 18 Apr 2019 16:58:34 +0000 (09:58 -0700)]
Also update Makefile.inc
Eddie Hung [Thu, 18 Apr 2019 16:05:22 +0000 (09:05 -0700)]
Make SB_LUT4 a blackbox
Eddie Hung [Thu, 18 Apr 2019 16:04:34 +0000 (09:04 -0700)]
Fix rename
Eddie Hung [Thu, 18 Apr 2019 16:02:58 +0000 (09:02 -0700)]
Rename to abc_*.{box,lut}
Eddie Hung [Thu, 18 Apr 2019 16:00:06 +0000 (09:00 -0700)]
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
Clifford Wolf [Thu, 18 Apr 2019 15:42:12 +0000 (17:42 +0200)]
Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 17 Apr 2019 23:36:03 +0000 (16:36 -0700)]
Skip if abc_box_id earlier
Eddie Hung [Wed, 17 Apr 2019 23:35:27 +0000 (16:35 -0700)]
Remove use of abc_box_id in stat
Eddie Hung [Wed, 17 Apr 2019 23:03:29 +0000 (16:03 -0700)]
Fix $anyseq warning and cleanup
Eddie Hung [Wed, 17 Apr 2019 22:19:48 +0000 (15:19 -0700)]
Update Makefile.inc too
Eddie Hung [Wed, 17 Apr 2019 22:19:02 +0000 (15:19 -0700)]
Reduce to three devices: hx, lp, u
Eddie Hung [Wed, 17 Apr 2019 22:11:14 +0000 (15:11 -0700)]
Do not print slack histogram
Eddie Hung [Wed, 17 Apr 2019 22:10:39 +0000 (15:10 -0700)]
Add up5k timings
Eddie Hung [Wed, 17 Apr 2019 22:10:22 +0000 (15:10 -0700)]
Fix grammar
Eddie Hung [Wed, 17 Apr 2019 22:07:44 +0000 (15:07 -0700)]
Update error message
Eddie Hung [Wed, 17 Apr 2019 22:04:46 +0000 (15:04 -0700)]
Add "-device" argument to synth_ice40
Eddie Hung [Wed, 17 Apr 2019 21:44:08 +0000 (14:44 -0700)]
Missing abc_flop_q attribute on SPRAM
Eddie Hung [Wed, 17 Apr 2019 21:43:45 +0000 (14:43 -0700)]
Cope with inout ports
Eddie Hung [Wed, 17 Apr 2019 20:01:17 +0000 (13:01 -0700)]
Map to SB_LUT4 from fastest input first
Eddie Hung [Wed, 17 Apr 2019 19:33:32 +0000 (12:33 -0700)]
Working ABC9 script
Eddie Hung [Wed, 17 Apr 2019 19:28:19 +0000 (12:28 -0700)]
Stop topological sort at abc_flop_q
Eddie Hung [Wed, 17 Apr 2019 19:27:45 +0000 (12:27 -0700)]
Mark seq output ports with "abc_flop_q" attr
Eddie Hung [Wed, 17 Apr 2019 19:27:02 +0000 (12:27 -0700)]
Also update Makefile.inc
Eddie Hung [Wed, 17 Apr 2019 19:22:03 +0000 (12:22 -0700)]
synth_ice40 to use renamed files
Eddie Hung [Wed, 17 Apr 2019 19:15:34 +0000 (12:15 -0700)]
Rename to abc.*
Eddie Hung [Wed, 17 Apr 2019 18:10:20 +0000 (11:10 -0700)]
Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
This reverts commit
a7632ab3326c5247b8152a53808413b259c13253.
Eddie Hung [Wed, 17 Apr 2019 18:10:04 +0000 (11:10 -0700)]
Try using an ICE40_CARRY_LUT primitive to avoid ABC issues
Eddie Hung [Wed, 17 Apr 2019 18:08:42 +0000 (11:08 -0700)]
Remove init* from xaiger, also topo-sort cells for box flow
Eddie Hung [Wed, 17 Apr 2019 18:01:15 +0000 (11:01 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Wed, 17 Apr 2019 17:55:23 +0000 (10:55 -0700)]
Ignore a/i/o/h XAIGER extensions
Eddie Hung [Wed, 17 Apr 2019 15:40:50 +0000 (08:40 -0700)]
Fix spacing
Clifford Wolf [Wed, 17 Apr 2019 11:51:34 +0000 (13:51 +0200)]
Update to ABC
d1b6413
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 17 Apr 2019 04:05:44 +0000 (21:05 -0700)]
Optimise
Eddie Hung [Wed, 17 Apr 2019 00:34:11 +0000 (17:34 -0700)]
Add SB_LUT4 to box library
Eddie Hung [Tue, 16 Apr 2019 23:39:30 +0000 (16:39 -0700)]
Add ice40 box files
Eddie Hung [Tue, 16 Apr 2019 23:39:16 +0000 (16:39 -0700)]
abc9 to output some more info
Eddie Hung [Tue, 16 Apr 2019 23:37:47 +0000 (16:37 -0700)]
CIs before PIs; also sort each cell's connections before iterating
Eddie Hung [Tue, 16 Apr 2019 22:04:20 +0000 (15:04 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Tue, 16 Apr 2019 22:01:45 +0000 (15:01 -0700)]
Port from xc7mux branch
Eddie Hung [Tue, 16 Apr 2019 20:10:35 +0000 (13:10 -0700)]
Re-enable partsel.v test
Eddie Hung [Tue, 16 Apr 2019 20:10:13 +0000 (13:10 -0700)]
abc9 to call "setundef -zero" behaving as for abc
Eddie Hung [Tue, 16 Apr 2019 18:59:21 +0000 (11:59 -0700)]
Merge pull request #939 from YosysHQ/revert895
Revert #895 (mux-to-shiftx optimisation)
Eddie Hung [Tue, 16 Apr 2019 18:07:51 +0000 (11:07 -0700)]
Revert #895
Eddie Hung [Tue, 16 Apr 2019 04:56:45 +0000 (21:56 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Tue, 16 Apr 2019 01:39:20 +0000 (18:39 -0700)]
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Tue, 16 Apr 2019 00:52:45 +0000 (17:52 -0700)]
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Mon, 15 Apr 2019 19:22:05 +0000 (12:22 -0700)]
Merge pull request #936 from YosysHQ/README-fix-quotes
README: fix some incorrect quoting
whitequark [Mon, 15 Apr 2019 14:29:46 +0000 (14:29 +0000)]
README: fix some incorrect quoting.
Eddie Hung [Sat, 13 Apr 2019 01:22:44 +0000 (18:22 -0700)]
Forgot backslashes
Eddie Hung [Sat, 13 Apr 2019 01:21:16 +0000 (18:21 -0700)]
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
Eddie Hung [Sat, 13 Apr 2019 01:16:50 +0000 (18:16 -0700)]
abc to ignore __dummy_o__ and __const[01]__ when re-integrating
Eddie Hung [Sat, 13 Apr 2019 01:16:25 +0000 (18:16 -0700)]
Output __const0__ and __const1__ CIs
Eddie Hung [Sat, 13 Apr 2019 00:09:24 +0000 (17:09 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Sat, 13 Apr 2019 00:02:24 +0000 (17:02 -0700)]
Fix inout handling for -map option
Eddie Hung [Fri, 12 Apr 2019 23:31:12 +0000 (16:31 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Fri, 12 Apr 2019 23:30:53 +0000 (16:30 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 12 Apr 2019 23:29:14 +0000 (16:29 -0700)]
Use -map instead of -symbols for aiger
Eddie Hung [Fri, 12 Apr 2019 23:17:48 +0000 (16:17 -0700)]
ci_bits and co_bits now a list, order is important for ABC
Eddie Hung [Fri, 12 Apr 2019 23:17:12 +0000 (16:17 -0700)]
Also cope with duplicated CIs
Eddie Hung [Fri, 12 Apr 2019 21:13:11 +0000 (14:13 -0700)]
WIP
Eddie Hung [Tue, 9 Apr 2019 17:09:43 +0000 (10:09 -0700)]
Comment out
Eddie Hung [Tue, 9 Apr 2019 17:06:44 +0000 (10:06 -0700)]
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
Eddie Hung [Fri, 12 Apr 2019 19:27:07 +0000 (12:27 -0700)]
Cope with an output having same name as an input (i.e. CO)
Eddie Hung [Fri, 12 Apr 2019 19:21:48 +0000 (12:21 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 12 Apr 2019 18:52:45 +0000 (11:52 -0700)]
Merge pull request #928 from litghost/add_xc7_sim_models
Add additional cells sim models for core 7-series primitives.
Keith Rothman [Fri, 12 Apr 2019 16:30:49 +0000 (09:30 -0700)]
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 12 Apr 2019 12:57:36 +0000 (14:57 +0200)]
Merge pull request #933 from dh73/master
Fixing issues in CycloneV cell sim
Clifford Wolf [Fri, 12 Apr 2019 12:57:01 +0000 (14:57 +0200)]
Merge pull request #932 from YosysHQ/eddie/fixdlatch
Recognise default entry in case even if all cases covered (fix for #931)
Diego [Fri, 12 Apr 2019 00:59:03 +0000 (19:59 -0500)]
Fixing issues in CycloneV cell sim
Eddie Hung [Thu, 11 Apr 2019 22:03:40 +0000 (15:03 -0700)]
Add default entry to testcase
Eddie Hung [Thu, 11 Apr 2019 19:34:51 +0000 (12:34 -0700)]
Recognise default entry in case even if all cases covered (#931)
Eddie Hung [Thu, 11 Apr 2019 01:06:33 +0000 (18:06 -0700)]
Add non-input bits driven by unrecognised cells as ci_bits
Eddie Hung [Wed, 10 Apr 2019 21:02:23 +0000 (14:02 -0700)]
parse_aiger() to rename all $lut cells after "clean"
Keith Rothman [Tue, 9 Apr 2019 18:43:19 +0000 (11:43 -0700)]
Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Keith Rothman [Tue, 9 Apr 2019 16:01:53 +0000 (09:01 -0700)]
Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Eddie Hung [Mon, 8 Apr 2019 23:46:33 +0000 (16:46 -0700)]
Fix a few typos
Eddie Hung [Mon, 8 Apr 2019 23:40:17 +0000 (16:40 -0700)]
More space fixing
Eddie Hung [Mon, 8 Apr 2019 23:37:22 +0000 (16:37 -0700)]
Fix spacing
Eddie Hung [Mon, 8 Apr 2019 23:31:59 +0000 (16:31 -0700)]
Merge branch 'master' into xaig
Clifford Wolf [Mon, 8 Apr 2019 19:14:05 +0000 (21:14 +0200)]
Merge pull request #919 from YosysHQ/multiport_transp
memory_bram: Fix multiport make_transp
David Shah [Sun, 7 Apr 2019 15:56:31 +0000 (16:56 +0100)]
memory_bram: Fix multiport make_transp
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 5 Apr 2019 15:31:49 +0000 (17:31 +0200)]
Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 4 Apr 2019 16:10:10 +0000 (18:10 +0200)]
Added missing argument checking to "mutate" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 3 Apr 2019 13:27:41 +0000 (06:27 -0700)]
Merge pull request #913 from smunaut/fix_proc_mux
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
Sylvain Munaut [Wed, 3 Apr 2019 12:50:12 +0000 (14:50 +0200)]
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Clifford Wolf [Wed, 3 Apr 2019 08:00:18 +0000 (10:00 +0200)]
Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
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