openpower-isa.git
2 years agobrainmelt moment, added a comma into a comment in a csv file
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 11:35:34 +0000 (12:35 +0100)]
brainmelt moment, added a comma into a comment in a csv file

2 years agouse maxvl not vl in impicit-RS
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 11:05:33 +0000 (12:05 +0100)]
use maxvl not vl in impicit-RS

2 years agopower_insn: remove the whitespaces properly
Dmitry Selyutin [Sun, 4 Sep 2022 11:23:45 +0000 (14:23 +0300)]
power_insn: remove the whitespaces properly

2 years agocomments for 3-in 2-out ops
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:45:32 +0000 (11:45 +0100)]
comments for 3-in 2-out ops

2 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:32:08 +0000 (11:32 +0100)]
whitespace cleanup

2 years agocomments on ffmadds fft 3-in 2-out
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:29:05 +0000 (11:29 +0100)]
comments on ffmadds fft 3-in 2-out

2 years agoassert prints out XO
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:14:49 +0000 (11:14 +0100)]
assert prints out XO

2 years agomore comments
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:10:48 +0000 (11:10 +0100)]
more comments

2 years agopower_insn: refactor immediate operands
Dmitry Selyutin [Sun, 4 Sep 2022 10:06:24 +0000 (13:06 +0300)]
power_insn: refactor immediate operands

2 years agopower_insn: inherit Operands from tuple
Dmitry Selyutin [Sun, 4 Sep 2022 09:49:42 +0000 (12:49 +0300)]
power_insn: inherit Operands from tuple

2 years agocode-cleanup (comments) and rename "i" to "XO"
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:08:19 +0000 (11:08 +0100)]
code-cleanup (comments) and rename "i" to "XO"

2 years agopower_insn: support immediate operands
Dmitry Selyutin [Sun, 4 Sep 2022 09:26:48 +0000 (12:26 +0300)]
power_insn: support immediate operands

2 years agopower_insn: make operand classes public
Dmitry Selyutin [Sun, 4 Sep 2022 09:04:29 +0000 (12:04 +0300)]
power_insn: make operand classes public

2 years agoRevert "target_addr in b and bc pseudo-code has no corresponding"
Dmitry Selyutin [Sun, 4 Sep 2022 08:58:08 +0000 (11:58 +0300)]
Revert "target_addr in b and bc pseudo-code has no corresponding"

This reverts commit 7656b425de39cb28e6c52b9ee32c0f12517bae69.

2 years agoRevert "svbranch.mdwn: replace target_addr with BD"
Dmitry Selyutin [Sun, 4 Sep 2022 08:57:57 +0000 (11:57 +0300)]
Revert "svbranch.mdwn: replace target_addr with BD"

This reverts commit 617e5af215856d2b80f3c0d7c92d97e4a4e0b2fc.

2 years agopower_insn: switch back to target_addr
Dmitry Selyutin [Sun, 4 Sep 2022 09:02:41 +0000 (12:02 +0300)]
power_insn: switch back to target_addr

2 years agoreallocate opcodes for ffadds (converted to X-FORM) and fdmadds to make space for...
Jacob Lifshay [Sun, 4 Sep 2022 07:53:30 +0000 (00:53 -0700)]
reallocate opcodes for ffadds (converted to X-FORM) and fdmadds to make space for fptrans

2 years agoclear up assert, clean up table columns
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 01:18:32 +0000 (02:18 +0100)]
clear up assert, clean up table columns

2 years agofix power_table.py to use multi-entries
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 01:14:38 +0000 (02:14 +0100)]
fix power_table.py to use multi-entries

2 years agopower_insn: support SVP64 verbose mode
Dmitry Selyutin [Sat, 3 Sep 2022 21:15:22 +0000 (00:15 +0300)]
power_insn: support SVP64 verbose mode

2 years agopower_insn: refactor verbose output
Dmitry Selyutin [Sat, 3 Sep 2022 21:06:46 +0000 (00:06 +0300)]
power_insn: refactor verbose output

2 years agopower_insn: support verbose binary
Dmitry Selyutin [Sat, 3 Sep 2022 20:50:18 +0000 (23:50 +0300)]
power_insn: support verbose binary

2 years agopower_insn: support PPC multi-records
Dmitry Selyutin [Sat, 3 Sep 2022 20:15:54 +0000 (23:15 +0300)]
power_insn: support PPC multi-records

2 years agopower_insn: update disassembly target_addr
Dmitry Selyutin [Sat, 3 Sep 2022 17:44:33 +0000 (20:44 +0300)]
power_insn: update disassembly target_addr

2 years agopysvp64dis: support verbose mode
Dmitry Selyutin [Sat, 3 Sep 2022 17:07:46 +0000 (20:07 +0300)]
pysvp64dis: support verbose mode

2 years agopower_insn: support verbose disassembly mode
Dmitry Selyutin [Sat, 3 Sep 2022 14:18:39 +0000 (17:18 +0300)]
power_insn: support verbose disassembly mode

2 years agopower_insn: implement mode decoding
Dmitry Selyutin [Sat, 3 Sep 2022 10:52:05 +0000 (13:52 +0300)]
power_insn: implement mode decoding

2 years agopower_insn: support Rc detection
Dmitry Selyutin [Sat, 3 Sep 2022 14:51:48 +0000 (17:51 +0300)]
power_insn: support Rc detection

2 years agopower_insn: drop pack/unpack bit
Dmitry Selyutin [Sat, 3 Sep 2022 13:16:05 +0000 (16:16 +0300)]
power_insn: drop pack/unpack bit

2 years agopower_insn: rename normal field to simple
Dmitry Selyutin [Sat, 3 Sep 2022 11:16:30 +0000 (14:16 +0300)]
power_insn: rename normal field to simple

2 years agopower_insn: decouple IMM/IDX LD/ST modes
Dmitry Selyutin [Sat, 3 Sep 2022 11:08:47 +0000 (14:08 +0300)]
power_insn: decouple IMM/IDX LD/ST modes

2 years agopower_insn: support operands check
Dmitry Selyutin [Sat, 3 Sep 2022 10:09:30 +0000 (13:09 +0300)]
power_insn: support operands check

2 years agopower_insn: canonicalize Rc field name
Dmitry Selyutin [Sat, 3 Sep 2022 10:06:05 +0000 (13:06 +0300)]
power_insn: canonicalize Rc field name

2 years agopower_insn: support mode selector
Dmitry Selyutin [Fri, 2 Sep 2022 22:11:32 +0000 (01:11 +0300)]
power_insn: support mode selector

2 years agopower_insn: support normal mode
Dmitry Selyutin [Fri, 2 Sep 2022 22:04:48 +0000 (01:04 +0300)]
power_insn: support normal mode

2 years agopower_insn: support LD/ST indexed mode
Dmitry Selyutin [Fri, 2 Sep 2022 21:20:16 +0000 (00:20 +0300)]
power_insn: support LD/ST indexed mode

2 years agopower_insn: simplify fields
Dmitry Selyutin [Fri, 2 Sep 2022 21:17:39 +0000 (00:17 +0300)]
power_insn: simplify fields

2 years agopower_insn: decrease LDSTMode class nesting
Dmitry Selyutin [Fri, 2 Sep 2022 21:01:47 +0000 (00:01 +0300)]
power_insn: decrease LDSTMode class nesting

2 years agopower_insn: support LD/ST immediate mode
Dmitry Selyutin [Fri, 2 Sep 2022 20:46:10 +0000 (23:46 +0300)]
power_insn: support LD/ST immediate mode

2 years agopower_insn: make RM class public
Dmitry Selyutin [Fri, 2 Sep 2022 16:56:39 +0000 (19:56 +0300)]
power_insn: make RM class public

2 years agopower_insn: remap RM immediately
Dmitry Selyutin [Fri, 2 Sep 2022 16:34:21 +0000 (19:34 +0300)]
power_insn: remap RM immediately

2 years agopower_fields: allow slicing mappings
Dmitry Selyutin [Fri, 2 Sep 2022 21:34:29 +0000 (00:34 +0300)]
power_fields: allow slicing mappings

2 years agopower_fields: allow slicing fields
Dmitry Selyutin [Fri, 2 Sep 2022 16:34:11 +0000 (19:34 +0300)]
power_fields: allow slicing fields

2 years agopower_fields: create arrays from Array class
Dmitry Selyutin [Fri, 2 Sep 2022 15:04:32 +0000 (18:04 +0300)]
power_fields: create arrays from Array class

2 years agosv_binutils: shorten and simplify the output
Dmitry Selyutin [Fri, 2 Sep 2022 21:48:01 +0000 (00:48 +0300)]
sv_binutils: shorten and simplify the output

2 years agocreate list of opcodes by dict entry
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:38:53 +0000 (19:38 +0100)]
create list of opcodes by dict entry

2 years agocorrect table header
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:32:34 +0000 (19:32 +0100)]
correct table header

2 years agouse opcode directly
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:30:08 +0000 (19:30 +0100)]
use opcode directly

2 years agodivpoint 2 to match v3.1
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:07:39 +0000 (19:07 +0100)]
divpoint 2 to match v3.1

2 years agocreate correct divpoint to make match against v3.0 Appendix C
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:05:45 +0000 (19:05 +0100)]
create correct divpoint to make match against v3.0 Appendix C

2 years agocomplete markdown table
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 17:43:29 +0000 (18:43 +0100)]
complete markdown table

2 years agocorrect table-matching
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 17:00:54 +0000 (18:00 +0100)]
correct table-matching

2 years agoenumeration almost there
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 16:48:09 +0000 (17:48 +0100)]
enumeration almost there

2 years agoMSB0-order, xomask 31-start
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 16:37:47 +0000 (17:37 +0100)]
MSB0-order, xomask 31-start

2 years agoadd power_table.py start of creating markdown Appendix D tables
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 16:33:46 +0000 (17:33 +0100)]
add power_table.py start of creating markdown Appendix D tables

2 years agoadd svshape2 offset test demonstrating RA being offset by one
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 12:45:12 +0000 (13:45 +0100)]
add svshape2 offset test demonstrating RA being offset by one

2 years agoRevert "add inv option to svshape2 (only 1 bit)"
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 12:13:55 +0000 (13:13 +0100)]
Revert "add inv option to svshape2 (only 1 bit)"

This reverts commit 77a4f7104968859385e0b8117ea74041cbe6e436.

the reason is that the inclusion of an inv bit can only be
done by reducing the range of "offset", from 0-15 to 0-7.

as this is the *only way* to get at elements on EXTRA2-encoding
it is considered "unwise"

2 years agoadd inv option to svshape2 (only 1 bit)
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 11:59:06 +0000 (12:59 +0100)]
add inv option to svshape2 (only 1 bit)
https://bugs.libre-soc.org/show_bug.cgi?id=911

there is precious space: an sv.svshape2 can add more bits later

2 years agoupdate sv_analysis to create separate SVMode.LDST_IDX from SVMode.LDST_IMM
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 11:06:00 +0000 (12:06 +0100)]
update sv_analysis to create separate SVMode.LDST_IDX from SVMode.LDST_IMM
to help distinguish the two SVP64.RM LD/ST types

2 years agofix test_caller_svshape2.py
Jacob Lifshay [Sat, 3 Sep 2022 01:50:01 +0000 (18:50 -0700)]
fix test_caller_svshape2.py

2 years agoformat code
Jacob Lifshay [Sat, 3 Sep 2022 01:44:08 +0000 (18:44 -0700)]
format code

2 years agoadd test_caller_svshape2.py and make corrections to csv and fields.txt
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 20:46:53 +0000 (21:46 +0100)]
add test_caller_svshape2.py and make corrections to csv and fields.txt
yx needed to be SVM2-form and was in a different bitposition
offs needed to be 6:9 not 6:10
XO was off-by-one in minor_22.csv

2 years agoadd first svshape2 pseudocode, based on svindex
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 17:44:22 +0000 (18:44 +0100)]
add first svshape2 pseudocode, based on svindex
it is near-identical but is actually back to svshape in terms of
the SHAPE bits set. bits 18-20 of SVSHAPEn are set in "Matrix" mode
not "Indexed" mode though.

2 years agoadd svshape2 to ISACaller
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 17:41:52 +0000 (18:41 +0100)]
add svshape2 to ISACaller
first recognising the persistence mode bit, second as not an illegal op

2 years agoadd svshape2 to sv/trans/svp64.py
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 15:33:01 +0000 (16:33 +0100)]
add svshape2 to sv/trans/svp64.py
https://bugs.libre-soc.org/show_bug.cgi?id=911

2 years agoadd svshape2 to list of instructions in power_enums.py
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 15:29:11 +0000 (16:29 +0100)]
add svshape2 to list of instructions in power_enums.py

2 years agowhoops bit 25 is sk not vf in svshape2. matches with svindex
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 15:25:52 +0000 (16:25 +0100)]
whoops bit 25 is sk not vf in svshape2. matches with svindex

2 years agodisallow reserved SVrm values in svshape, svp64.py
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 15:16:47 +0000 (16:16 +0100)]
disallow reserved SVrm values in svshape, svp64.py

2 years agoadd svshape2 (stub pseudocode) fields, Form, and CSV file minor_22.csv
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 14:43:17 +0000 (15:43 +0100)]
add svshape2 (stub pseudocode) fields, Form, and CSV file minor_22.csv
https://bugs.libre-soc.org/show_bug.cgi?id=911

also added missing SVI-Form (svindex) SVd and rmm which are exactly
the same.  svshape2 is weird, it is a hybrid of svindex and svshapes

2 years agoadd explicit 13 patterns for svshape which make a hole for svshape2
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 14:40:59 +0000 (15:40 +0100)]
add explicit 13 patterns for svshape which make a hole for svshape2
svshape2 will take up 2 out of the 16 4-bit patterns so svshape has
to explicitly list them. this takes advantage of the new feature
added by ghostmansd: opcode merging, commit d5ec553e768

2 years agoshuffle down numbering after SVM to make room for SVM2
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 14:37:50 +0000 (15:37 +0100)]
shuffle down numbering after SVM to make room for SVM2
power_enums.py Form needs to make space for SVM2
(and svshape is no longer temporary)

2 years agoadd fix of out_sel in power_decoder.py formal proof
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 12:32:45 +0000 (13:32 +0100)]
add fix of out_sel in power_decoder.py formal proof
but there are others.  basically the list of enums needs to be
automatically listed and put into the matches

2 years agofix RCOE.RC_ONLY in formal test_decoder2.py
Luke Kenneth Casson Leighton [Fri, 2 Sep 2022 12:19:25 +0000 (13:19 +0100)]
fix RCOE.RC_ONLY in formal test_decoder2.py

2 years agopower_insn: drop custom Record representation
Dmitry Selyutin [Fri, 2 Sep 2022 08:43:06 +0000 (11:43 +0300)]
power_insn: drop custom Record representation

2 years agopower_insn: support opcode merging
Dmitry Selyutin [Thu, 1 Sep 2022 19:55:01 +0000 (22:55 +0300)]
power_insn: support opcode merging

2 years agopower_insn: support AA matching
Dmitry Selyutin [Thu, 1 Sep 2022 14:50:54 +0000 (17:50 +0300)]
power_insn: support AA matching

2 years agopower_insn: support LK matching
Dmitry Selyutin [Thu, 1 Sep 2022 13:05:36 +0000 (16:05 +0300)]
power_insn: support LK matching

2 years agopower_insn: refactor name matching algorithm
Dmitry Selyutin [Thu, 1 Sep 2022 12:55:39 +0000 (15:55 +0300)]
power_insn: refactor name matching algorithm

2 years agopower_insn: refactor databases composition
Dmitry Selyutin [Thu, 1 Sep 2022 15:04:24 +0000 (18:04 +0300)]
power_insn: refactor databases composition

2 years agopower_insn: refactor operands
Dmitry Selyutin [Thu, 1 Sep 2022 14:29:07 +0000 (17:29 +0300)]
power_insn: refactor operands

2 years agopower_insn: introduce binutils-like representation
Dmitry Selyutin [Thu, 1 Sep 2022 12:40:16 +0000 (15:40 +0300)]
power_insn: introduce binutils-like representation

2 years agopysvp64dis: refactor instruction loading
Dmitry Selyutin [Thu, 1 Sep 2022 12:32:38 +0000 (15:32 +0300)]
pysvp64dis: refactor instruction loading

2 years agopower_fields: allow comparing references
Dmitry Selyutin [Thu, 1 Sep 2022 12:32:06 +0000 (15:32 +0300)]
power_fields: allow comparing references

2 years agopower_insn: disable disassembly for prefixed instructions
Dmitry Selyutin [Thu, 1 Sep 2022 12:02:14 +0000 (15:02 +0300)]
power_insn: disable disassembly for prefixed instructions

2 years agopower_insn: switch target_addr to real fields
Dmitry Selyutin [Thu, 1 Sep 2022 11:54:11 +0000 (14:54 +0300)]
power_insn: switch target_addr to real fields

2 years agopower_insn: support GPR and FPR operands
Dmitry Selyutin [Wed, 31 Aug 2022 10:45:32 +0000 (13:45 +0300)]
power_insn: support GPR and FPR operands

2 years agopower_insn: support target_addr operands
Dmitry Selyutin [Wed, 31 Aug 2022 10:36:48 +0000 (13:36 +0300)]
power_insn: support target_addr operands

2 years agopower_insn: hide operand classes
Dmitry Selyutin [Wed, 31 Aug 2022 10:13:44 +0000 (13:13 +0300)]
power_insn: hide operand classes

2 years agopower_insn: introduce operand disassembly
Dmitry Selyutin [Wed, 31 Aug 2022 08:37:31 +0000 (11:37 +0300)]
power_insn: introduce operand disassembly

2 years agopysvp64dis: disassemble word instruction operands
Dmitry Selyutin [Tue, 30 Aug 2022 19:32:05 +0000 (22:32 +0300)]
pysvp64dis: disassemble word instruction operands

2 years agopower_insn: support operands
Dmitry Selyutin [Tue, 30 Aug 2022 19:06:00 +0000 (22:06 +0300)]
power_insn: support operands

2 years agomake tests pass again
Jacob Lifshay [Fri, 2 Sep 2022 06:34:11 +0000 (23:34 -0700)]
make tests pass again

2 years agoadd formal_test_temp to .gitignore
Jacob Lifshay [Fri, 2 Sep 2022 06:33:39 +0000 (23:33 -0700)]
add formal_test_temp to .gitignore

2 years agoformat code
Jacob Lifshay [Fri, 2 Sep 2022 06:32:02 +0000 (23:32 -0700)]
format code

2 years agorename proof_decoder*.py -> test_decoder*.py so it gets run by pytest
Jacob Lifshay [Fri, 2 Sep 2022 06:06:56 +0000 (23:06 -0700)]
rename proof_decoder*.py -> test_decoder*.py so it gets run by pytest

2 years agoghostmansd found that extswsli is incorrectly declared
Luke Kenneth Casson Leighton [Thu, 1 Sep 2022 22:56:59 +0000 (23:56 +0100)]
ghostmansd found that extswsli is incorrectly declared
as extswsli RA,RS,SH as XS-Form, where a quick check shows that
there *is* no field "SH" in XS-Form. there *is* however a field "sh"
in XS-Form and the pseudocode *correctly* uses it.

that then led to a review of all the other uses of SH and sh,
which also led to spotting that ME and MB are *also* mis-used
(MD-Form and MDS-Form) and need lower-casing in the operand
declaration but are *also* correct in the pseudo-code
`

2 years agoremove hard-coded list of operations in DecodeOE which rc_only
Luke Kenneth Casson Leighton [Thu, 1 Sep 2022 17:11:28 +0000 (18:11 +0100)]
remove hard-coded list of operations in DecodeOE which
had been bugging the hell out of me for some time

2 years agomissed rlwm* in conversion to RC_ONLY
Luke Kenneth Casson Leighton [Thu, 1 Sep 2022 17:10:55 +0000 (18:10 +0100)]
missed rlwm* in conversion to RC_ONLY

2 years agoupdate CSV files marking those instructions that are RC-only as such
Luke Kenneth Casson Leighton [Thu, 1 Sep 2022 16:16:20 +0000 (17:16 +0100)]
update CSV files marking those instructions that are RC-only as such
there were actually some bugs here, entries that had not been added to
DecodeOE such as (all!) fp operations (which have no OE=1 variant)
and the new AV abs/min/max instructions

2 years agodrat have to use RCOE.RC not RCOE.RC_OE for now otherwise
Luke Kenneth Casson Leighton [Thu, 1 Sep 2022 15:54:39 +0000 (16:54 +0100)]
drat have to use RCOE.RC not RCOE.RC_OE for now otherwise
all CSV entries have to change