litex.git
12 years agofhdl: encapsulate replicated constants
Sebastien Bourdeauducq [Thu, 22 Dec 2011 23:35:13 +0000 (00:35 +0100)]
fhdl: encapsulate replicated constants

12 years agoflow: actor class
Sebastien Bourdeauducq [Thu, 22 Dec 2011 18:37:16 +0000 (19:37 +0100)]
flow: actor class

12 years agocsr: use optree
Sebastien Bourdeauducq [Thu, 22 Dec 2011 18:36:56 +0000 (19:36 +0100)]
csr: use optree

12 years agocorelogic: operator tree
Sebastien Bourdeauducq [Thu, 22 Dec 2011 14:46:19 +0000 (15:46 +0100)]
corelogic: operator tree

12 years agoverilog: comb reset
Sebastien Bourdeauducq [Wed, 21 Dec 2011 23:04:53 +0000 (00:04 +0100)]
verilog: comb reset

12 years agoverilog: break down Convert function
Sebastien Bourdeauducq [Wed, 21 Dec 2011 22:08:50 +0000 (23:08 +0100)]
verilog: break down Convert function

12 years agoverilog: ignore variable property in combinatorial block
Sebastien Bourdeauducq [Wed, 21 Dec 2011 22:00:36 +0000 (23:00 +0100)]
verilog: ignore variable property in combinatorial block

12 years agoConsistent names
Sebastien Bourdeauducq [Wed, 21 Dec 2011 21:57:07 +0000 (22:57 +0100)]
Consistent names

12 years agoREADME: Flow
Sebastien Bourdeauducq [Mon, 19 Dec 2011 23:07:46 +0000 (00:07 +0100)]
README: Flow

12 years agoREADME: Core Logic, Bus, Bank
Sebastien Bourdeauducq [Mon, 19 Dec 2011 22:24:31 +0000 (23:24 +0100)]
README: Core Logic, Bus, Bank

12 years agoREADME: structure + FHDL description
Sebastien Bourdeauducq [Mon, 19 Dec 2011 21:15:10 +0000 (22:15 +0100)]
README: structure + FHDL description

12 years agoexamples: remove old-style declarations
Sebastien Bourdeauducq [Sun, 18 Dec 2011 20:54:39 +0000 (21:54 +0100)]
examples: remove old-style declarations

12 years agocorelogic: fix signal exports
Sebastien Bourdeauducq [Sun, 18 Dec 2011 20:54:28 +0000 (21:54 +0100)]
corelogic: fix signal exports

12 years agofhdl: better matching of assignment
Sebastien Bourdeauducq [Sun, 18 Dec 2011 20:49:48 +0000 (21:49 +0100)]
fhdl: better matching of assignment

12 years agoRemove uses of declare_signal
Sebastien Bourdeauducq [Sun, 18 Dec 2011 20:47:48 +0000 (21:47 +0100)]
Remove uses of declare_signal

12 years agofhdl: also take into account object attributes in _make_signal_name. Get rid of decla...
Sebastien Bourdeauducq [Sun, 18 Dec 2011 20:47:29 +0000 (21:47 +0100)]
fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal

12 years agofhdl: automatic signal name from assignment
Sebastien Bourdeauducq [Sun, 18 Dec 2011 20:26:51 +0000 (21:26 +0100)]
fhdl: automatic signal name from assignment

12 years agobank: support raw registers
Sebastien Bourdeauducq [Sat, 17 Dec 2011 23:28:04 +0000 (00:28 +0100)]
bank: support raw registers

12 years agofhdl: fix series of if/elif/else
Sebastien Bourdeauducq [Sat, 17 Dec 2011 19:31:42 +0000 (20:31 +0100)]
fhdl: fix series of if/elif/else

12 years ago32-device, 8-bit CSR bus
Sebastien Bourdeauducq [Sat, 17 Dec 2011 14:54:49 +0000 (15:54 +0100)]
32-device, 8-bit CSR bus

12 years agoverilog: get the simulator to run the combinatorial process at the beginning
Sebastien Bourdeauducq [Sat, 17 Dec 2011 14:20:22 +0000 (15:20 +0100)]
verilog: get the simulator to run the combinatorial process at the beginning

12 years agoverilog: support for float parameters in instances
Sebastien Bourdeauducq [Sat, 17 Dec 2011 13:59:27 +0000 (14:59 +0100)]
verilog: support for float parameters in instances

12 years agoverilog: user-definable reset and clock
Sebastien Bourdeauducq [Fri, 16 Dec 2011 21:25:05 +0000 (22:25 +0100)]
verilog: user-definable reset and clock

12 years agofhdl: simpler syntax
Sebastien Bourdeauducq [Fri, 16 Dec 2011 20:30:14 +0000 (21:30 +0100)]
fhdl: simpler syntax

12 years agoPay a bit more attention to PEP8
Sebastien Bourdeauducq [Fri, 16 Dec 2011 15:02:55 +0000 (16:02 +0100)]
Pay a bit more attention to PEP8

12 years agowishbone2csr: wait for WB deack
Sebastien Bourdeauducq [Tue, 13 Dec 2011 16:38:59 +0000 (17:38 +0100)]
wishbone2csr: wait for WB deack

12 years agotimeline: only trigger in rest state
Sebastien Bourdeauducq [Tue, 13 Dec 2011 14:25:46 +0000 (15:25 +0100)]
timeline: only trigger in rest state

12 years agoexamples: Wishbone interconnect test bench
Sebastien Bourdeauducq [Tue, 13 Dec 2011 13:10:56 +0000 (14:10 +0100)]
examples: Wishbone interconnect test bench

12 years agoverilog: use blocking assignment in combinatorial process
Sebastien Bourdeauducq [Tue, 13 Dec 2011 13:09:12 +0000 (14:09 +0100)]
verilog: use blocking assignment in combinatorial process

12 years agowishbone: decoder: fix slave cyc generation in registered mode
Sebastien Bourdeauducq [Tue, 13 Dec 2011 13:08:39 +0000 (14:08 +0100)]
wishbone: decoder: fix slave cyc generation in registered mode

12 years agowishbone2csr: fix double-write bug
Sebastien Bourdeauducq [Mon, 12 Dec 2011 23:25:46 +0000 (00:25 +0100)]
wishbone2csr: fix double-write bug

12 years agowishbone: only send ack to the active master in arbiter
Sebastien Bourdeauducq [Mon, 12 Dec 2011 23:25:25 +0000 (00:25 +0100)]
wishbone: only send ack to the active master in arbiter

12 years agofhdl: allow a namespace to be specified for Verilog conversion
Sebastien Bourdeauducq [Mon, 12 Dec 2011 23:24:40 +0000 (00:24 +0100)]
fhdl: allow a namespace to be specified for Verilog conversion

12 years agofhdl: support Constant parameters for Verilog conversion
Sebastien Bourdeauducq [Sun, 11 Dec 2011 19:17:51 +0000 (20:17 +0100)]
fhdl: support Constant parameters for Verilog conversion

12 years agofhdl: fix list references (thanks Lars)
Sebastien Bourdeauducq [Sun, 11 Dec 2011 19:17:29 +0000 (20:17 +0100)]
fhdl: fix list references (thanks Lars)

12 years agobus: fix CSR interconnect data readback
Sebastien Bourdeauducq [Sun, 11 Dec 2011 19:17:12 +0000 (20:17 +0100)]
bus: fix CSR interconnect data readback

12 years agobus: 14-bit CSR addresses
Sebastien Bourdeauducq [Sun, 11 Dec 2011 19:16:50 +0000 (20:16 +0100)]
bus: 14-bit CSR addresses

12 years agobank: fix csrgen address decoder
Sebastien Bourdeauducq [Sun, 11 Dec 2011 19:15:30 +0000 (20:15 +0100)]
bank: fix csrgen address decoder

12 years agobus: Wishbone to CSR bridge
Sebastien Bourdeauducq [Sun, 11 Dec 2011 14:04:34 +0000 (15:04 +0100)]
bus: Wishbone to CSR bridge

12 years agocorelogic: timeline module
Sebastien Bourdeauducq [Sun, 11 Dec 2011 00:11:13 +0000 (01:11 +0100)]
corelogic: timeline module

12 years agofhdl: remove broken fragment iadd
Sebastien Bourdeauducq [Sun, 11 Dec 2011 00:10:59 +0000 (01:10 +0100)]
fhdl: remove broken fragment iadd

12 years agoconvtools: insert reset on variables
Sebastien Bourdeauducq [Sun, 11 Dec 2011 00:10:37 +0000 (01:10 +0100)]
convtools: insert reset on variables

12 years agoautofragment: remove debug
Sebastien Bourdeauducq [Sat, 10 Dec 2011 19:48:23 +0000 (20:48 +0100)]
autofragment: remove debug

12 years agofhdl: autofragment
Sebastien Bourdeauducq [Sat, 10 Dec 2011 19:47:21 +0000 (20:47 +0100)]
fhdl: autofragment

12 years agofhdl: fix += for empty fragment
Sebastien Bourdeauducq [Sat, 10 Dec 2011 19:47:06 +0000 (20:47 +0100)]
fhdl: fix += for empty fragment

12 years agofhdl: pad support in fragments
Sebastien Bourdeauducq [Sat, 10 Dec 2011 19:25:24 +0000 (20:25 +0100)]
fhdl: pad support in fragments

12 years agowishbone: decoder + shared bus interconnect
Sebastien Bourdeauducq [Fri, 9 Dec 2011 12:11:52 +0000 (13:11 +0100)]
wishbone: decoder + shared bus interconnect

12 years agofhdl: replication support
Sebastien Bourdeauducq [Fri, 9 Dec 2011 12:11:34 +0000 (13:11 +0100)]
fhdl: replication support

12 years agowishbone: arbiter
Sebastien Bourdeauducq [Thu, 8 Dec 2011 22:21:25 +0000 (23:21 +0100)]
wishbone: arbiter

12 years agosimplebus: export GetSigName function
Sebastien Bourdeauducq [Thu, 8 Dec 2011 22:06:04 +0000 (23:06 +0100)]
simplebus: export GetSigName function

12 years agocorelogic: multimux module
Sebastien Bourdeauducq [Thu, 8 Dec 2011 22:04:34 +0000 (23:04 +0100)]
corelogic: multimux module

12 years agoverilog: handle default in case statements
Sebastien Bourdeauducq [Thu, 8 Dec 2011 22:04:20 +0000 (23:04 +0100)]
verilog: handle default in case statements

12 years agofhdl: improve automatic signal naming
Sebastien Bourdeauducq [Thu, 8 Dec 2011 20:28:20 +0000 (21:28 +0100)]
fhdl: improve automatic signal naming

12 years agoCorelogic conversion example
Sebastien Bourdeauducq [Thu, 8 Dec 2011 20:25:05 +0000 (21:25 +0100)]
Corelogic conversion example

12 years agocorelogic: MC divider module
Sebastien Bourdeauducq [Thu, 8 Dec 2011 20:19:40 +0000 (21:19 +0100)]
corelogic: MC divider module

12 years agofhdl: support negation operator
Sebastien Bourdeauducq [Thu, 8 Dec 2011 20:15:44 +0000 (21:15 +0100)]
fhdl: support negation operator

12 years agoverilog: fix unary operator conversion
Sebastien Bourdeauducq [Thu, 8 Dec 2011 20:15:24 +0000 (21:15 +0100)]
verilog: fix unary operator conversion

12 years agocorelogic: round-robin module
Sebastien Bourdeauducq [Thu, 8 Dec 2011 20:15:02 +0000 (21:15 +0100)]
corelogic: round-robin module

12 years agoNamed buses
Sebastien Bourdeauducq [Thu, 8 Dec 2011 18:16:08 +0000 (19:16 +0100)]
Named buses

12 years agowishbone: add missing SEL
Sebastien Bourdeauducq [Thu, 8 Dec 2011 18:09:32 +0000 (19:09 +0100)]
wishbone: add missing SEL

12 years agoinstances: signal override
Sebastien Bourdeauducq [Thu, 8 Dec 2011 17:56:14 +0000 (18:56 +0100)]
instances: signal override

12 years agoWishbone declarations
Sebastien Bourdeauducq [Thu, 8 Dec 2011 17:47:41 +0000 (18:47 +0100)]
Wishbone declarations

12 years agoSimple bus base class
Sebastien Bourdeauducq [Thu, 8 Dec 2011 17:47:32 +0000 (18:47 +0100)]
Simple bus base class

12 years agoInstance support
Sebastien Bourdeauducq [Thu, 8 Dec 2011 15:35:32 +0000 (16:35 +0100)]
Instance support

12 years agofhdl: fix implicit slice index
Sebastien Bourdeauducq [Wed, 7 Dec 2011 21:21:30 +0000 (22:21 +0100)]
fhdl: fix implicit slice index

12 years agofhdl: cleanup value bv
Sebastien Bourdeauducq [Wed, 7 Dec 2011 21:21:10 +0000 (22:21 +0100)]
fhdl: cleanup value bv

12 years agoVariable conversion
Sebastien Bourdeauducq [Mon, 5 Dec 2011 21:00:06 +0000 (22:00 +0100)]
Variable conversion

12 years agoCleanup
Sebastien Bourdeauducq [Mon, 5 Dec 2011 18:25:32 +0000 (19:25 +0100)]
Cleanup

12 years agoCase support + register bank generator
Sebastien Bourdeauducq [Mon, 5 Dec 2011 16:43:56 +0000 (17:43 +0100)]
Case support + register bank generator

12 years agoCSR bus definitions
Sebastien Bourdeauducq [Sun, 4 Dec 2011 23:16:44 +0000 (00:16 +0100)]
CSR bus definitions

12 years agoExamples folder
Sebastien Bourdeauducq [Sun, 4 Dec 2011 22:39:48 +0000 (23:39 +0100)]
Examples folder

12 years agoReset insertion
Sebastien Bourdeauducq [Sun, 4 Dec 2011 21:41:50 +0000 (22:41 +0100)]
Reset insertion

12 years agoVerilog generator
Sebastien Bourdeauducq [Sun, 4 Dec 2011 21:26:32 +0000 (22:26 +0100)]
Verilog generator

12 years agoInitial import, FHDL basic structure, divider example
Sebastien Bourdeauducq [Sun, 4 Dec 2011 15:44:38 +0000 (16:44 +0100)]
Initial import, FHDL basic structure, divider example