yosys.git
8 years agoSupport for hierarchical designs in smt2 back-end
Clifford Wolf [Sun, 10 Jul 2016 16:11:25 +0000 (18:11 +0200)]
Support for hierarchical designs in smt2 back-end

8 years agoFurther improved fsm_detect output, attempt to detect self-resetting circuits
Clifford Wolf [Sat, 9 Jul 2016 12:02:49 +0000 (14:02 +0200)]
Further improved fsm_detect output, attempt to detect self-resetting circuits

8 years agoAdded printing of some warning messages to fsm_detect
Clifford Wolf [Sat, 9 Jul 2016 11:23:06 +0000 (13:23 +0200)]
Added printing of some warning messages to fsm_detect

8 years agoAdded warning about adding fsm_encoding attributes to wires to manual
Clifford Wolf [Fri, 8 Jul 2016 16:31:31 +0000 (18:31 +0200)]
Added warning about adding fsm_encoding attributes to wires to manual

8 years agoMinor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
Clifford Wolf [Fri, 8 Jul 2016 12:41:36 +0000 (14:41 +0200)]
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations

8 years agoFixed mem assignment in left-hand-side concatenation
Clifford Wolf [Fri, 8 Jul 2016 12:31:06 +0000 (14:31 +0200)]
Fixed mem assignment in left-hand-side concatenation

8 years agoMerge branch 'eddiehung-vtr'
Clifford Wolf [Fri, 8 Jul 2016 09:56:53 +0000 (11:56 +0200)]
Merge branch 'eddiehung-vtr'

8 years agoRestored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior
Clifford Wolf [Fri, 8 Jul 2016 09:49:55 +0000 (11:49 +0200)]
Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior

8 years agoIn BLIF, a .names without entries already always outputs 0
Clifford Wolf [Fri, 8 Jul 2016 09:41:26 +0000 (11:41 +0200)]
In BLIF, a .names without entries already always outputs 0

8 years agoUndo eddiehung-vtr Makefile changes
Clifford Wolf [Fri, 8 Jul 2016 09:35:15 +0000 (11:35 +0200)]
Undo eddiehung-vtr Makefile changes

8 years agoMerge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddiehung-vtr
Clifford Wolf [Fri, 8 Jul 2016 09:32:36 +0000 (11:32 +0200)]
Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddiehung-vtr

8 years agoFixed autotest.sh handling of `timescale
Clifford Wolf [Sat, 2 Jul 2016 11:32:20 +0000 (13:32 +0200)]
Fixed autotest.sh handling of `timescale

8 years agoMerge branch 'assert-limit'
Clifford Wolf [Fri, 1 Jul 2016 10:24:31 +0000 (12:24 +0200)]
Merge branch 'assert-limit'

8 years agoReplaced "select -assert-limit" with -assert-max and -assert-min
Clifford Wolf [Fri, 1 Jul 2016 10:24:13 +0000 (12:24 +0200)]
Replaced "select -assert-limit" with -assert-max and -assert-min

8 years agoAdded 'assert-limit' option for 'select' command
eshellko [Fri, 1 Jul 2016 06:24:22 +0000 (10:24 +0400)]
Added 'assert-limit' option for 'select' command

For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.

8 years agoImproved ice40_ffinit error reporting
Clifford Wolf [Thu, 30 Jun 2016 07:58:13 +0000 (09:58 +0200)]
Improved ice40_ffinit error reporting

8 years agoMerge pull request #181 from rubund/input_logic_allowed
Clifford Wolf [Tue, 21 Jun 2016 06:44:20 +0000 (08:44 +0200)]
Merge pull request #181 from rubund/input_logic_allowed

Allow defining input ports as "input logic" in SystemVerilog

8 years agoAllow defining input ports as "input logic" in SystemVerilog
Ruben Undheim [Mon, 20 Jun 2016 18:16:37 +0000 (20:16 +0200)]
Allow defining input ports as "input logic" in SystemVerilog

8 years agoBugfix in "abc -script" handling
Clifford Wolf [Sun, 19 Jun 2016 20:19:19 +0000 (22:19 +0200)]
Bugfix in "abc -script" handling

8 years agoMerge branch 'sv_packages' of https://github.com/rubund/yosys
Clifford Wolf [Sun, 19 Jun 2016 13:48:40 +0000 (15:48 +0200)]
Merge branch 'sv_packages' of https://github.com/rubund/yosys

8 years agoAdded "deminout"
Clifford Wolf [Sun, 19 Jun 2016 11:08:16 +0000 (13:08 +0200)]
Added "deminout"

8 years agoA few modifications after pull request comments
Ruben Undheim [Sat, 18 Jun 2016 12:13:36 +0000 (14:13 +0200)]
A few modifications after pull request comments

- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h

8 years agoAdded "read_blif -sop"
Clifford Wolf [Sat, 18 Jun 2016 10:33:13 +0000 (12:33 +0200)]
Added "read_blif -sop"

8 years agoAdded $sop support to BLIF back-end
Clifford Wolf [Sat, 18 Jun 2016 10:28:49 +0000 (12:28 +0200)]
Added $sop support to BLIF back-end

8 years agoAdded support for SystemVerilog packages with localparam definitions
Ruben Undheim [Sat, 18 Jun 2016 08:24:21 +0000 (10:24 +0200)]
Added support for SystemVerilog packages with localparam definitions

8 years agoAdded "dc2" to default ABC scripts
Clifford Wolf [Fri, 17 Jun 2016 18:15:35 +0000 (20:15 +0200)]
Added "dc2" to default ABC scripts

8 years agoFixed init issue in mem2reg_test2 test case
Clifford Wolf [Fri, 17 Jun 2016 18:15:11 +0000 (20:15 +0200)]
Fixed init issue in mem2reg_test2 test case

8 years agoAdded "abc -I <num> -P <num>"
Clifford Wolf [Fri, 17 Jun 2016 17:39:35 +0000 (19:39 +0200)]
Added "abc -I <num> -P <num>"

8 years agoAdded $sop SAT model
Clifford Wolf [Fri, 17 Jun 2016 15:47:30 +0000 (17:47 +0200)]
Added $sop SAT model

8 years agoImproved support for $sop cells
Clifford Wolf [Fri, 17 Jun 2016 14:31:16 +0000 (16:31 +0200)]
Improved support for $sop cells

8 years agoAdded $sop cell type and "abc -sop"
Clifford Wolf [Fri, 17 Jun 2016 11:46:01 +0000 (13:46 +0200)]
Added $sop cell type and "abc -sop"

8 years agoUpdated ABC to hg rev b5df6e2b76f0
Clifford Wolf [Fri, 17 Jun 2016 09:16:31 +0000 (11:16 +0200)]
Updated ABC to hg rev b5df6e2b76f0

8 years agoAdded "nlutmap -assert"
Clifford Wolf [Thu, 9 Jun 2016 09:47:41 +0000 (11:47 +0200)]
Added "nlutmap -assert"

8 years agoDo not run "wreduce" in "prep -ifx"
Clifford Wolf [Wed, 8 Jun 2016 10:14:32 +0000 (12:14 +0200)]
Do not run "wreduce" in "prep -ifx"

8 years agoAdded "proc_mux -ifx"
Clifford Wolf [Mon, 6 Jun 2016 15:15:50 +0000 (17:15 +0200)]
Added "proc_mux -ifx"

8 years agoAdded "setundef -init"
Clifford Wolf [Fri, 3 Jun 2016 09:38:31 +0000 (11:38 +0200)]
Added "setundef -init"

8 years agoFix all undef-muxes in dlatch input cone
Clifford Wolf [Thu, 2 Jun 2016 12:37:07 +0000 (14:37 +0200)]
Fix all undef-muxes in dlatch input cone

8 years agoAvoid creating undef-muxes when inferring latches in proc_dlatch
Clifford Wolf [Wed, 1 Jun 2016 11:25:06 +0000 (13:25 +0200)]
Avoid creating undef-muxes when inferring latches in proc_dlatch

8 years agoAdded opt_expr support for div/mod by power-of-two
Clifford Wolf [Sun, 29 May 2016 10:17:36 +0000 (12:17 +0200)]
Added opt_expr support for div/mod by power-of-two

8 years agoFixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
Clifford Wolf [Fri, 27 May 2016 15:55:03 +0000 (17:55 +0200)]
Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}

8 years agoFixed access-after-delete bug in mem2reg code
Clifford Wolf [Fri, 27 May 2016 15:25:33 +0000 (17:25 +0200)]
Fixed access-after-delete bug in mem2reg code

8 years agofixed typos in error messages
Clifford Wolf [Fri, 27 May 2016 14:37:36 +0000 (16:37 +0200)]
fixed typos in error messages

8 years agoFixed "scc" for cells that have feedback singals _and_ are part of a larger loop
Clifford Wolf [Fri, 27 May 2016 14:33:13 +0000 (16:33 +0200)]
Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop

8 years agoMerge pull request #172 from zeldin/deterministic_hierarchy
Clifford Wolf [Sun, 22 May 2016 16:15:08 +0000 (18:15 +0200)]
Merge pull request #172 from zeldin/deterministic_hierarchy

Made the expansion order of hierarchy deterministic

8 years agoMade the expansion order of hierarchy deterministic
Marcus Comstedt [Sun, 22 May 2016 14:37:47 +0000 (16:37 +0200)]
Made the expansion order of hierarchy deterministic

8 years agoSome fixes in tests/asicworld/*_tb.v
Clifford Wolf [Fri, 20 May 2016 15:13:11 +0000 (17:13 +0200)]
Some fixes in tests/asicworld/*_tb.v

8 years agoImprovements and fixes in autotest.sh script and test_autotb
Clifford Wolf [Fri, 20 May 2016 14:58:02 +0000 (16:58 +0200)]
Improvements and fixes in autotest.sh script and test_autotb

8 years agoMerge branch 'master' of https://github.com/Kmanfi/yosys
Clifford Wolf [Fri, 20 May 2016 14:48:50 +0000 (16:48 +0200)]
Merge branch 'master' of https://github.com/Kmanfi/yosys

8 years agoAlso escape "=" in spice output
Clifford Wolf [Fri, 20 May 2016 14:43:13 +0000 (16:43 +0200)]
Also escape "=" in spice output

8 years agoSmall improvements in Verilog front-end docs
Clifford Wolf [Fri, 20 May 2016 14:21:35 +0000 (16:21 +0200)]
Small improvements in Verilog front-end docs

8 years agoClose opened dump file.
Kaj Tuomi [Thu, 19 May 2016 08:53:29 +0000 (11:53 +0300)]
Close opened dump file.

8 years agoFix for Modelsim transcript line warp issue #164
Kaj Tuomi [Thu, 19 May 2016 08:34:38 +0000 (11:34 +0300)]
Fix for Modelsim transcript line warp issue #164

8 years agoDon't sign-extend memory bram initialization data
Clifford Wolf [Sat, 14 May 2016 22:05:30 +0000 (00:05 +0200)]
Don't sign-extend memory bram initialization data

8 years agoAdded missing "#define HASHLIB_H"
Clifford Wolf [Sat, 14 May 2016 09:43:20 +0000 (11:43 +0200)]
Added missing "#define HASHLIB_H"

8 years agoMinor presentation fixes
Clifford Wolf [Sat, 14 May 2016 09:35:39 +0000 (11:35 +0200)]
Minor presentation fixes

8 years agoUpdated min GCC requirement to GCC 4.8
Clifford Wolf [Wed, 11 May 2016 07:31:53 +0000 (09:31 +0200)]
Updated min GCC requirement to GCC 4.8

8 years agoAdded manual download link to README
Clifford Wolf [Mon, 9 May 2016 10:43:49 +0000 (12:43 +0200)]
Added manual download link to README

8 years agoInclude <cmath> in yosys.h
Clifford Wolf [Sun, 8 May 2016 08:50:39 +0000 (10:50 +0200)]
Include <cmath> in yosys.h

8 years agoMerge pull request #162 from azonenberg/master
Clifford Wolf [Sun, 8 May 2016 08:22:01 +0000 (10:22 +0200)]
Merge pull request #162 from azonenberg/master

Added GP_DELAY cell. Fixed several errors in simulation models.

8 years agoAdded GP_DELAY cell
Andrew Zonenberg [Sun, 8 May 2016 04:29:26 +0000 (21:29 -0700)]
Added GP_DELAY cell

8 years agoFixed typo in port name
Andrew Zonenberg [Sun, 8 May 2016 04:14:42 +0000 (21:14 -0700)]
Fixed typo in port name

8 years agoFixed extra semicolon
Andrew Zonenberg [Sun, 8 May 2016 04:14:18 +0000 (21:14 -0700)]
Fixed extra semicolon

8 years agoFixed typo in parameter name
Andrew Zonenberg [Sun, 8 May 2016 04:14:00 +0000 (21:14 -0700)]
Fixed typo in parameter name

8 years agoAdded simulation timescale declaration
Andrew Zonenberg [Sun, 8 May 2016 04:13:47 +0000 (21:13 -0700)]
Added simulation timescale declaration

8 years agoFixes for MXE build
Clifford Wolf [Sat, 7 May 2016 08:53:18 +0000 (10:53 +0200)]
Fixes for MXE build

8 years agoAdded support for "keep" attribute to shregmap
Clifford Wolf [Sat, 7 May 2016 07:33:16 +0000 (09:33 +0200)]
Added support for "keep" attribute to shregmap

8 years agoAdded synth_ice40 support for latches via logic loops
Clifford Wolf [Fri, 6 May 2016 21:02:37 +0000 (23:02 +0200)]
Added synth_ice40 support for latches via logic loops

8 years agoAdded "write_blif -noalias"
Clifford Wolf [Fri, 6 May 2016 13:05:53 +0000 (15:05 +0200)]
Added "write_blif -noalias"

8 years agoFixed ice40_opt lut unmapping, added "ice40_opt -unlut"
Clifford Wolf [Fri, 6 May 2016 12:32:32 +0000 (14:32 +0200)]
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"

8 years agoFixed preservation of important attributes in techmap
Clifford Wolf [Fri, 6 May 2016 11:59:30 +0000 (13:59 +0200)]
Fixed preservation of important attributes in techmap

8 years agoMerge pull request #159 from azonenberg/master
Clifford Wolf [Thu, 5 May 2016 16:18:48 +0000 (18:18 +0200)]
Merge pull request #159 from azonenberg/master

Fixes to use new I/O pad techmapping, renamed ports for GP_SHREG

8 years agoChanged order of passes for better handling of INIT attributes on "output reg" FFs
Andrew Zonenberg [Thu, 5 May 2016 00:13:54 +0000 (17:13 -0700)]
Changed order of passes for better handling of INIT attributes on "output reg" FFs

8 years agoChanged port names in greenpak shregmap
Andrew Zonenberg [Thu, 5 May 2016 00:04:50 +0000 (17:04 -0700)]
Changed port names in greenpak shregmap

8 years agoRenamed module parameter
Andrew Zonenberg [Thu, 5 May 2016 00:03:45 +0000 (17:03 -0700)]
Renamed module parameter

8 years agoRefactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instea...
Andrew Zonenberg [Wed, 4 May 2016 22:55:16 +0000 (15:55 -0700)]
Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract

8 years agoAdded tristate buffer support to iopadmap
Clifford Wolf [Wed, 4 May 2016 20:48:02 +0000 (22:48 +0200)]
Added tristate buffer support to iopadmap

8 years agoMerge pull request #157 from azonenberg/master
Clifford Wolf [Wed, 4 May 2016 17:12:59 +0000 (19:12 +0200)]
Merge pull request #157 from azonenberg/master

Added GP_ABUF cell, support for tri-state I/O buffers in GreenPak

8 years agoFixed incorrect signal naming in GP_IOBUF
Andrew Zonenberg [Wed, 4 May 2016 15:06:18 +0000 (08:06 -0700)]
Fixed incorrect signal naming in GP_IOBUF

8 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Wed, 4 May 2016 14:23:27 +0000 (07:23 -0700)]
Merge https://github.com/cliffordwolf/yosys

8 years agoMerge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Wed, 4 May 2016 08:48:42 +0000 (10:48 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys

8 years agoFixed iopadmap attribute handling
Clifford Wolf [Wed, 4 May 2016 08:48:23 +0000 (10:48 +0200)]
Fixed iopadmap attribute handling

8 years agoAdded tri-state I/O extraction for GreenPak
Andrew Zonenberg [Wed, 4 May 2016 05:53:29 +0000 (22:53 -0700)]
Added tri-state I/O extraction for GreenPak

8 years agoAdded GreenPak I/O buffer cells
Andrew Zonenberg [Wed, 4 May 2016 05:03:04 +0000 (22:03 -0700)]
Added GreenPak I/O buffer cells

8 years agoAdded comment to clarify GP_ABUF cell
Andrew Zonenberg [Tue, 3 May 2016 03:29:39 +0000 (20:29 -0700)]
Added comment to clarify GP_ABUF cell

8 years agoAdded GP_ABUF cell
Andrew Zonenberg [Tue, 3 May 2016 03:27:41 +0000 (20:27 -0700)]
Added GP_ABUF cell

8 years agoMerge pull request #154 from azonenberg/master
Clifford Wolf [Mon, 2 May 2016 07:49:07 +0000 (09:49 +0200)]
Merge pull request #154 from azonenberg/master

Add GP_PGA cell

8 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Sun, 1 May 2016 17:07:21 +0000 (10:07 -0700)]
Merge https://github.com/cliffordwolf/yosys

8 years agoImproved TCL_VERSION detection so it does not read .tclshrc
Clifford Wolf [Fri, 29 Apr 2016 08:26:22 +0000 (10:26 +0200)]
Improved TCL_VERSION detection so it does not read .tclshrc

8 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Fri, 29 Apr 2016 07:57:37 +0000 (00:57 -0700)]
Merge https://github.com/cliffordwolf/yosys

8 years agoAdded "qwp -v"
Clifford Wolf [Thu, 28 Apr 2016 21:17:30 +0000 (23:17 +0200)]
Added "qwp -v"

8 years agoAdded GP_PGA cell
Andrew Zonenberg [Thu, 28 Apr 2016 06:07:21 +0000 (23:07 -0700)]
Added GP_PGA cell

8 years agoConnections between inputs and inouts are driven by the input
Clifford Wolf [Tue, 26 Apr 2016 17:49:05 +0000 (19:49 +0200)]
Connections between inputs and inouts are driven by the input

8 years agoFixed test_autotb for modules with many cell ports
Clifford Wolf [Mon, 25 Apr 2016 14:37:11 +0000 (16:37 +0200)]
Fixed test_autotb for modules with many cell ports

8 years agoFixed proc_mux performance bug
Clifford Wolf [Mon, 25 Apr 2016 08:43:04 +0000 (10:43 +0200)]
Fixed proc_mux performance bug

8 years agoMerge pull request #150 from azonenberg/master
Clifford Wolf [Mon, 25 Apr 2016 08:33:18 +0000 (10:33 +0200)]
Merge pull request #150 from azonenberg/master

GreenPak analog comparator support

8 years agoMerge https://github.com/cliffordwolf/yosys
Andrew Zonenberg [Mon, 25 Apr 2016 05:11:56 +0000 (22:11 -0700)]
Merge https://github.com/cliffordwolf/yosys

8 years agoRemoved VIN_BUF_EN
Andrew Zonenberg [Mon, 25 Apr 2016 00:01:21 +0000 (17:01 -0700)]
Removed VIN_BUF_EN

8 years agoFixed performance bug in proc_dlatch
Clifford Wolf [Sun, 24 Apr 2016 17:29:56 +0000 (19:29 +0200)]
Fixed performance bug in proc_dlatch

8 years agoAdded "yosys -D ALL"
Clifford Wolf [Sun, 24 Apr 2016 15:12:34 +0000 (17:12 +0200)]
Added "yosys -D ALL"

8 years agoRenamed VOUT to OUT on GP_ACMP cell
Andrew Zonenberg [Sun, 24 Apr 2016 05:53:49 +0000 (22:53 -0700)]
Renamed VOUT to OUT on GP_ACMP cell