litex.git
11 years agoactorlib/structuring/Cast: support inversion
Sebastien Bourdeauducq [Mon, 25 Mar 2013 14:54:09 +0000 (15:54 +0100)]
actorlib/structuring/Cast: support inversion

11 years agobank/csrgen/BankArray: retain name information
Sebastien Bourdeauducq [Mon, 25 Mar 2013 13:44:15 +0000 (14:44 +0100)]
bank/csrgen/BankArray: retain name information

11 years agobank/description/Register: add get_size
Sebastien Bourdeauducq [Mon, 25 Mar 2013 13:43:44 +0000 (14:43 +0100)]
bank/description/Register: add get_size

11 years agogenlib/record: use getattr instead of __dict__
Sebastien Bourdeauducq [Sat, 23 Mar 2013 23:51:01 +0000 (00:51 +0100)]
genlib/record: use getattr instead of __dict__

11 years agogenlib/record: add eq
Sebastien Bourdeauducq [Sat, 23 Mar 2013 23:50:33 +0000 (00:50 +0100)]
genlib/record: add eq

11 years agogenlib/fifo: simple synchronous FIFO
Sebastien Bourdeauducq [Fri, 22 Mar 2013 17:18:38 +0000 (18:18 +0100)]
genlib/fifo: simple synchronous FIFO

11 years agofhdl/module: support clock domain remapping of submodules
Sebastien Bourdeauducq [Fri, 22 Mar 2013 17:17:54 +0000 (18:17 +0100)]
fhdl/module: support clock domain remapping of submodules

11 years agogenlib/cdc/MultiReg: output clock domain defaults to sys
Sebastien Bourdeauducq [Thu, 21 Mar 2013 09:40:02 +0000 (10:40 +0100)]
genlib/cdc/MultiReg: output clock domain defaults to sys

11 years agoexamples/sim/fir: convert to new API
Sebastien Bourdeauducq [Tue, 19 Mar 2013 10:46:27 +0000 (11:46 +0100)]
examples/sim/fir: convert to new API

11 years agofhdl/verilog: optionally disable clock domain creation
Sebastien Bourdeauducq [Mon, 18 Mar 2013 17:45:19 +0000 (18:45 +0100)]
fhdl/verilog: optionally disable clock domain creation

11 years agoexamples/basic/arrays: demonstrate lowering of Array in Instance expression
Sebastien Bourdeauducq [Mon, 18 Mar 2013 17:37:23 +0000 (18:37 +0100)]
examples/basic/arrays: demonstrate lowering of Array in Instance expression

11 years agoLowering of Special expressions + support ClockSignal/ResetSignal
Sebastien Bourdeauducq [Mon, 18 Mar 2013 17:36:50 +0000 (18:36 +0100)]
Lowering of Special expressions + support ClockSignal/ResetSignal

11 years agofhdl/tools/_ArrayLowerer: complete support for arrays as targets
Sebastien Bourdeauducq [Mon, 18 Mar 2013 13:38:01 +0000 (14:38 +0100)]
fhdl/tools/_ArrayLowerer: complete support for arrays as targets

11 years agofhdl/tools/value_bits_sign: support not
Sebastien Bourdeauducq [Mon, 18 Mar 2013 08:52:43 +0000 (09:52 +0100)]
fhdl/tools/value_bits_sign: support not

11 years agofhdl/structure: style fix
Sebastien Bourdeauducq [Sun, 17 Mar 2013 14:33:38 +0000 (15:33 +0100)]
fhdl/structure: style fix

11 years agoMerge pull request #6 from larsclausen/master
Sébastien Bourdeauducq [Sun, 17 Mar 2013 14:33:14 +0000 (07:33 -0700)]
Merge pull request #6 from larsclausen/master

Minor improvements

11 years agogenlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
Sebastien Bourdeauducq [Fri, 15 Mar 2013 18:50:24 +0000 (19:50 +0100)]
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains

11 years agogenlib/cdc/MultiReg: remove idomain
Sebastien Bourdeauducq [Fri, 15 Mar 2013 18:49:24 +0000 (19:49 +0100)]
genlib/cdc/MultiReg: remove idomain

11 years agofhdl/specials: fix rename_clock_domain declarations
Sebastien Bourdeauducq [Fri, 15 Mar 2013 18:47:01 +0000 (19:47 +0100)]
fhdl/specials: fix rename_clock_domain declarations

11 years agosim: remove PureSimulable (superseded by Module)
Sebastien Bourdeauducq [Fri, 15 Mar 2013 18:41:30 +0000 (19:41 +0100)]
sim: remove PureSimulable (superseded by Module)

11 years agostructure: remove Fragment.call_sim
Sebastien Bourdeauducq [Fri, 15 Mar 2013 18:15:48 +0000 (19:15 +0100)]
structure: remove Fragment.call_sim

11 years agosim: compatibility with new ClockDomain API
Sebastien Bourdeauducq [Fri, 15 Mar 2013 18:15:28 +0000 (19:15 +0100)]
sim: compatibility with new ClockDomain API

11 years agoLocal clock domain example
Sebastien Bourdeauducq [Fri, 15 Mar 2013 17:18:32 +0000 (18:18 +0100)]
Local clock domain example

11 years agoMake ClockDomains part of fragments
Sebastien Bourdeauducq [Fri, 15 Mar 2013 17:17:33 +0000 (18:17 +0100)]
Make ClockDomains part of fragments

11 years agoflow/actor/filter_endpoints: deterministic order
Sebastien Bourdeauducq [Thu, 14 Mar 2013 11:20:18 +0000 (12:20 +0100)]
flow/actor/filter_endpoints: deterministic order

11 years agobank/csrgen/BankArray: create banks in sorted order
Sebastien Bourdeauducq [Wed, 13 Mar 2013 22:07:44 +0000 (23:07 +0100)]
bank/csrgen/BankArray: create banks in sorted order

11 years agobank/description: modify reg/mem in-place
Sebastien Bourdeauducq [Wed, 13 Mar 2013 18:46:34 +0000 (19:46 +0100)]
bank/description: modify reg/mem in-place

11 years agoAllow SimActors to produce/consume a constant stream of tokens
Lars-Peter Clausen [Tue, 12 Mar 2013 21:27:19 +0000 (22:27 +0100)]
Allow SimActors to produce/consume a constant stream of tokens

Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.

The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
11 years agoAdd support for negative slice indices
Lars-Peter Clausen [Tue, 12 Mar 2013 20:34:36 +0000 (21:34 +0100)]
Add support for negative slice indices

In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].

Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
11 years agoexamples/pytholite: use new APIs
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:59:24 +0000 (16:59 +0100)]
examples/pytholite: use new APIs

11 years agosim/generic: support implicit get_fragment
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:54:01 +0000 (16:54 +0100)]
sim/generic: support implicit get_fragment

11 years agovpi: make it work by default on Arch
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:51:58 +0000 (16:51 +0100)]
vpi: make it work by default on Arch

11 years agoexamples/basic: use new APIs
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:45:28 +0000 (16:45 +0100)]
examples/basic: use new APIs

11 years agofhdl/verilog: implicit get_fragment
Sebastien Bourdeauducq [Tue, 12 Mar 2013 15:16:06 +0000 (16:16 +0100)]
fhdl/verilog: implicit get_fragment

11 years agofhdl/specials/Memory: automatic name#
Sebastien Bourdeauducq [Tue, 12 Mar 2013 14:58:39 +0000 (15:58 +0100)]
fhdl/specials/Memory: automatic name#

11 years agobank: automatic register naming
Sebastien Bourdeauducq [Tue, 12 Mar 2013 14:45:24 +0000 (15:45 +0100)]
bank: automatic register naming

11 years agofhdl/tracer: recognize CALL_FUNCTION_VAR opcode
Sebastien Bourdeauducq [Tue, 12 Mar 2013 12:48:09 +0000 (13:48 +0100)]
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode

11 years agofhdl/tracer: recognize LOAD_DEREF opcode
Sebastien Bourdeauducq [Tue, 12 Mar 2013 09:31:56 +0000 (10:31 +0100)]
fhdl/tracer: recognize LOAD_DEREF opcode

11 years agofhdl/tracer: remove leading underscores from names
Sebastien Bourdeauducq [Mon, 11 Mar 2013 21:21:58 +0000 (22:21 +0100)]
fhdl/tracer: remove leading underscores from names

11 years agoREADME: update
Sebastien Bourdeauducq [Mon, 11 Mar 2013 19:29:47 +0000 (20:29 +0100)]
README: update

11 years agobus/asmibus: use implicit finalization
Sebastien Bourdeauducq [Mon, 11 Mar 2013 16:11:59 +0000 (17:11 +0100)]
bus/asmibus: use implicit finalization

11 years agoFix Register name conflict between Pytholite and Bank
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:47:21 +0000 (19:47 +0100)]
Fix Register name conflict between Pytholite and Bank

11 years agobank/eventmanager: use module and autoreg
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:29:05 +0000 (19:29 +0100)]
bank/eventmanager: use module and autoreg

11 years agobus/asmibus: use fhdl.module API
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:28:22 +0000 (19:28 +0100)]
bus/asmibus: use fhdl.module API

11 years agofhdl/module: replace autofragment
Sebastien Bourdeauducq [Sun, 10 Mar 2013 18:27:55 +0000 (19:27 +0100)]
fhdl/module: replace autofragment

11 years agobank/description/AutoReg: check that get_memories and get_registers are callable
Sebastien Bourdeauducq [Sun, 10 Mar 2013 17:11:29 +0000 (18:11 +0100)]
bank/description/AutoReg: check that get_memories and get_registers are callable

11 years agobank/csrgen: BankArray
Sebastien Bourdeauducq [Sat, 9 Mar 2013 23:45:16 +0000 (00:45 +0100)]
bank/csrgen: BankArray

11 years agobank/description: AutoReg
Sebastien Bourdeauducq [Sat, 9 Mar 2013 23:43:16 +0000 (00:43 +0100)]
bank/description: AutoReg

11 years agomigen/fhdl/autofragment: factorize
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:23:24 +0000 (23:23 +0100)]
migen/fhdl/autofragment: factorize

11 years agofhdl/autofragment: remove legacy functions
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:05:45 +0000 (23:05 +0100)]
fhdl/autofragment: remove legacy functions

11 years agofhdl/tools/flat_iteration: generalize
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:03:15 +0000 (23:03 +0100)]
fhdl/tools/flat_iteration: generalize

11 years agofhdl/autofragment: fix submodules
Sebastien Bourdeauducq [Sat, 9 Mar 2013 20:15:38 +0000 (21:15 +0100)]
fhdl/autofragment: fix submodules

11 years agofhdl/autofragment: empty build_fragment by default
Sebastien Bourdeauducq [Sat, 9 Mar 2013 18:10:47 +0000 (19:10 +0100)]
fhdl/autofragment: empty build_fragment by default

11 years agoUse common definition for FinalizeError
Sebastien Bourdeauducq [Sat, 9 Mar 2013 18:03:13 +0000 (19:03 +0100)]
Use common definition for FinalizeError

11 years agocsr/SRAM: support for writes with memory widths larger than bus words
Sebastien Bourdeauducq [Fri, 8 Mar 2013 23:50:57 +0000 (00:50 +0100)]
csr/SRAM: support for writes with memory widths larger than bus words

11 years agofhdl/verilog: tristate outputs are always wire
Sebastien Bourdeauducq [Wed, 6 Mar 2013 10:30:52 +0000 (11:30 +0100)]
fhdl/verilog: tristate outputs are always wire

11 years agobus/csr: support memories with larger word width than the bus (read only)
Sebastien Bourdeauducq [Sun, 3 Mar 2013 18:27:13 +0000 (19:27 +0100)]
bus/csr: support memories with larger word width than the bus (read only)

11 years agofhdl/autofragment: bugfixes + add auto_attr
Sebastien Bourdeauducq [Sun, 3 Mar 2013 16:53:06 +0000 (17:53 +0100)]
fhdl/autofragment: bugfixes + add auto_attr

11 years agofhdl/autofragment: FModule
Sebastien Bourdeauducq [Sat, 2 Mar 2013 22:30:54 +0000 (23:30 +0100)]
fhdl/autofragment: FModule

11 years agocsr/SRAM: prefix page register with memory name
Sebastien Bourdeauducq [Fri, 1 Mar 2013 11:06:12 +0000 (12:06 +0100)]
csr/SRAM: prefix page register with memory name

11 years agofhdl/verilog: insert reset before listing signals
Sebastien Bourdeauducq [Wed, 27 Feb 2013 17:10:04 +0000 (18:10 +0100)]
fhdl/verilog: insert reset before listing signals

11 years agobank/description: memprefix
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:14:15 +0000 (23:14 +0100)]
bank/description: memprefix

11 years agofhdl/specials: allow setting memory name
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:14:03 +0000 (23:14 +0100)]
fhdl/specials: allow setting memory name

11 years agouio/ioo: fix specials
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:13:38 +0000 (23:13 +0100)]
uio/ioo: fix specials

11 years agofhdl/specials/Instance: _printintbool -> verilog_printexpr
Sebastien Bourdeauducq [Sun, 24 Feb 2013 12:08:01 +0000 (13:08 +0100)]
fhdl/specials/Instance: _printintbool -> verilog_printexpr

11 years agoexamples/psync: cleanup
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:14:31 +0000 (19:14 +0100)]
examples/psync: cleanup

11 years agoexamples/basic/psync: demonstrate the new features
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:04:11 +0000 (19:04 +0100)]
examples/basic/psync: demonstrate the new features

11 years agogenlib: clock domain crossing elements
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:03:35 +0000 (19:03 +0100)]
genlib: clock domain crossing elements

11 years agofhdl/verilog: support special lowering and overrides
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:03:16 +0000 (19:03 +0100)]
fhdl/verilog: support special lowering and overrides

11 years agoexamples/fir: better filter
Sebastien Bourdeauducq [Fri, 22 Feb 2013 22:19:56 +0000 (23:19 +0100)]
examples/fir: better filter

11 years agocorelogic -> genlib
Sebastien Bourdeauducq [Fri, 22 Feb 2013 22:19:37 +0000 (23:19 +0100)]
corelogic -> genlib

11 years agofhdl: inline synthesis directive support
Sebastien Bourdeauducq [Fri, 22 Feb 2013 18:10:02 +0000 (19:10 +0100)]
fhdl: inline synthesis directive support

11 years agodoc: new 'specials' API
Sebastien Bourdeauducq [Fri, 22 Feb 2013 17:12:42 +0000 (18:12 +0100)]
doc: new 'specials' API

11 years agoNew 'specials' API
Sebastien Bourdeauducq [Fri, 22 Feb 2013 16:56:35 +0000 (17:56 +0100)]
New 'specials' API

11 years agodoc: tristates
Sebastien Bourdeauducq [Tue, 19 Feb 2013 16:52:57 +0000 (17:52 +0100)]
doc: tristates

11 years agofhdl: TSTriple
Sebastien Bourdeauducq [Tue, 19 Feb 2013 16:26:02 +0000 (17:26 +0100)]
fhdl: TSTriple

11 years agofhdl: tristate support
Sebastien Bourdeauducq [Thu, 14 Feb 2013 23:17:24 +0000 (00:17 +0100)]
fhdl: tristate support

11 years agofhdl/autofragment: from_attributes
Sebastien Bourdeauducq [Mon, 11 Feb 2013 17:34:01 +0000 (18:34 +0100)]
fhdl/autofragment: from_attributes

11 years agodoc: fix signal desc layout
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:39:18 +0000 (19:39 +0100)]
doc: fix signal desc layout

11 years agoMerge branch 'master' of github.com:milkymist/migen
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:03:32 +0000 (19:03 +0100)]
Merge branch 'master' of github.com:milkymist/migen

11 years agodoc/dataflow: remove ActorNode
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:03:18 +0000 (19:03 +0100)]
doc/dataflow: remove ActorNode

11 years agodoc/dataflow: remove ALA
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:57:03 +0000 (18:57 +0100)]
doc/dataflow: remove ALA

11 years agodoc: multiple clock domains
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:56:45 +0000 (18:56 +0100)]
doc: multiple clock domains

11 years agodoc: do not inline examples as this never works with most Sphinx setups ...
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:45:06 +0000 (18:45 +0100)]
doc: do not inline examples as this never works with most Sphinx setups ...

11 years agodoc: update to new Migen APIs
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:42:47 +0000 (18:42 +0100)]
doc: update to new Migen APIs

11 years agosim: default runner to Icarus Verilog
Sebastien Bourdeauducq [Sat, 9 Feb 2013 16:04:53 +0000 (17:04 +0100)]
sim: default runner to Icarus Verilog

11 years agoflow/perftools: finish removing ActorNode
Sebastien Bourdeauducq [Sat, 9 Feb 2013 16:03:48 +0000 (17:03 +0100)]
flow/perftools: finish removing ActorNode

11 years agofhdl/structure: store clock domain name
Sebastien Bourdeauducq [Thu, 24 Jan 2013 12:49:49 +0000 (13:49 +0100)]
fhdl/structure: store clock domain name

11 years agofhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
Sebastien Bourdeauducq [Wed, 23 Jan 2013 14:13:06 +0000 (15:13 +0100)]
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()

11 years agocorelogic: complex arithmetic support
Sebastien Bourdeauducq [Sat, 5 Jan 2013 13:18:36 +0000 (14:18 +0100)]
corelogic: complex arithmetic support

11 years agofhdl: support nested statement lists
Sebastien Bourdeauducq [Sat, 5 Jan 2013 13:18:15 +0000 (14:18 +0100)]
fhdl: support nested statement lists

11 years agopytholite: fix bug with constant assignment to register
Sebastien Bourdeauducq [Wed, 19 Dec 2012 15:21:57 +0000 (16:21 +0100)]
pytholite: fix bug with constant assignment to register

11 years agopytholite: prune unused registers
Sebastien Bourdeauducq [Wed, 19 Dec 2012 15:03:05 +0000 (16:03 +0100)]
pytholite: prune unused registers

11 years agoDo not use super()
Sebastien Bourdeauducq [Tue, 18 Dec 2012 13:54:33 +0000 (14:54 +0100)]
Do not use super()

11 years agoexamples/pytholite: fix imports
Sebastien Bourdeauducq [Sun, 16 Dec 2012 19:26:23 +0000 (20:26 +0100)]
examples/pytholite: fix imports

11 years agofhdl/tools: bitreverse
Sebastien Bourdeauducq [Fri, 14 Dec 2012 22:56:16 +0000 (23:56 +0100)]
fhdl/tools: bitreverse

11 years agoactorlib/sim/SimActor: do not drive busy low when generator yields None
Sebastien Bourdeauducq [Fri, 14 Dec 2012 22:56:03 +0000 (23:56 +0100)]
actorlib/sim/SimActor: do not drive busy low when generator yields None

11 years agoToken: support idle_wait
Sebastien Bourdeauducq [Fri, 14 Dec 2012 18:16:22 +0000 (19:16 +0100)]
Token: support idle_wait

11 years agoMove Token to migen.flow.transactions
Sebastien Bourdeauducq [Fri, 14 Dec 2012 14:55:38 +0000 (15:55 +0100)]
Move Token to migen.flow.transactions

11 years agoreplace some forgotten is_abstract()
Sebastien Bourdeauducq [Wed, 12 Dec 2012 21:36:45 +0000 (22:36 +0100)]
replace some forgotten is_abstract()