Brandon Potter [Mon, 11 Mar 2019 18:30:57 +0000 (14:30 -0400)]
sim-se, tests: add a new sim-se test
This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).
After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.
Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.
Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Jordi Vaquero [Tue, 6 Aug 2019 01:45:06 +0000 (03:45 +0200)]
cpu-o3: fix atomic instructions non-speculative
Fix problem with O3 and AMO instructions. At initial stages amo
instruction is considered a type of non-speculative store. After
the instruction has been commited and during the squash step,
acquire_release version of the AMO operation is considered speculative,
that differents results in an assert fault. This fix ensures that AMO
instructions are always considered non-speculative, during early stages
and during squas/removal of the instruction.
Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19815
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jordi Vaquero [Fri, 26 Jul 2019 14:31:39 +0000 (16:31 +0200)]
cpu-o3: added _amo_op parameter in o3 LSQ
Fix bug with AMO (or RMW) instructions where the amo_op variable
is not being propagated to the LSQ request.
Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19814
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Jordi Vaquero [Fri, 5 Jul 2019 17:02:05 +0000 (19:02 +0200)]
arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.
Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19810
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jordi Vaquero [Tue, 6 Aug 2019 13:49:14 +0000 (15:49 +0200)]
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.
Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Thu, 25 Jul 2019 13:58:54 +0000 (14:58 +0100)]
dev-arm: Perform SMMUv3 CFG Invalidation at device interface
In the current SMMUv3 model, multiple micro/mainTLB are present at the
device interface (SMMUv3SlaveInterface), caching translations specific
to a device.
Those distributed TLBs are checked for a translation before checking for
centralized TLBs (shared by devices), like the configuration cache, walk
cache etc. This means that if a hit in these TLBs occurs, there won't
be a need to enter configuration stage (which is where the STE and CD
are retrieved). So if we invalidate a cached configuration (in
ConfigCache), we need to invalidate those interface TLB entries as well,
otherwise in theory we will keep the same translation even after a
change in configuration tables.
Change-Id: I4aa36ba8392a530267517bef7562318b282bee25
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Sat, 3 Aug 2019 10:04:14 +0000 (12:04 +0200)]
mem-cache: Fix non-virtual base destructor of Repl Entry
ReplaceableEntry contains a virtual method, yet its destructor
was not virtual, causing errors in some compilers.
Change-Id: I13deec843f4007d9deb924882a8d98ff6a89c84f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19808
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Brandon Potter [Mon, 11 Mar 2019 18:24:33 +0000 (14:24 -0400)]
sim-se: add new getpgrp system call
This changeset adds new (relatively simple) system call
support. The getpgrp call returns a thread context's
pgid.
Change-Id: I361bdbfb9c01b761ddd5a4923d23f86971f8d614
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17111
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Matthew Sinclair [Tue, 12 Mar 2019 14:37:51 +0000 (10:37 -0400)]
sim-se: adding pipe2 syscall
pipe2 builds on top of the pipe syscall implementation by
adding some extra flags for the files (to avoid have to
make separate calls to fcntl).
Change-Id: I88cf6f1387b9d14e60b33a32db412da9ed93a3e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12310
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 29 Jul 2019 11:38:12 +0000 (12:38 +0100)]
arch-arm: Implement ARMv8.1-PAN, Privileged access never
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state
bit is 1, any privileged data access from EL1 or EL2 to a virtual memory
address that is accessible at EL0 generates a Permission fault.
This feature is mandatory in ARMv8.1 implementations.
This feature is supported in AArch64 and AArch32 states.
The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields
identify the support for ARMv8.1-PAN.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I94a76311711739dd2394c72944d88ba9321fd159
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Tue, 30 Jul 2019 10:34:44 +0000 (11:34 +0100)]
arch-arm: Rewrite MSR immediate instruction class
MSR <pstatefield>, #imm is used for setting a PSTATE field using an
immediate. Current implementation has the following flaws:
* There is no base MSR immediate definition: all the existing
PSTATE fields have a different class definition
* Those implementation make use of a generic data64 base class
which results in a wrong disassembly (pstate register is printed as an
integer register).
This patch is fixing this by defining a new base class (MiscRegImmOp64)
and new related templates. In this way, we aim to ease addition of new
PSTATE fields (in ARMv8.x)
Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Chun-Chen TK Hsu [Tue, 23 Jul 2019 10:40:41 +0000 (18:40 +0800)]
systemc: Provide Port wrapper classes for sc_port
Add Port wrappers for sc_port, sc_interface, and sc_export.
Change-Id: Ib70cb7466461c8d32e3a260bf2a2d60a6ded87c3
Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19788
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Pouya Fotouhi [Tue, 30 Jul 2019 19:21:53 +0000 (14:21 -0500)]
mem-ruby: Remove assertion with incorrect assumption
Current code assumes that only one cacheline would either be in
RW. This is not true for GPU protocols, and may not be true
for some CPU-only protocols with state violations.
Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Brandon Potter [Tue, 28 Aug 2018 22:02:58 +0000 (18:02 -0400)]
sim-se: small refactor on pipe syscall
Change-Id: I02ffb1c4af980554ff12ac7d11d32ba80fe261c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12308
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Fri, 21 Jun 2019 14:24:28 +0000 (16:24 +0200)]
mem: Move eraseIfNullEntry to when holder is updated
The entry should only be tested for deletion when holder is updated.
Change-Id: I5a10b6fa876912709b7467860d43c23c60f38568
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19750
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Wed, 17 Apr 2019 09:23:51 +0000 (11:23 +0200)]
mem: Encapsulate retry variables of SnoopFilter
Group all variables related to the restoration of a snoop filter
entry due to a crossbar retry.
Change-Id: I4e03edb3afd06563b7a5812959739876709eceeb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19749
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Brandon Potter [Mon, 11 Mar 2019 18:08:17 +0000 (14:08 -0400)]
sim-se: small performance optimization
A local variable was being set inside a loop when it should
have been set outside the loop. This changeset moves the
variable to the appropriate place.
Change-Id: If7655b501bd819c39d35dea4c316b4b9ed3173a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17108
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Brandon Potter [Mon, 11 Mar 2019 18:17:07 +0000 (14:17 -0400)]
sim-se: fstat64 bugfix
The fstat64 system call does an upcast on entries in the file
descriptor array to check if the file descriptor has a backing
host-filesystem file opened. It does so because it needs to pass
the host fd into the fstat call (since we rely on the host
filesystem to service filesystem system calls).
The upcast was overly specific. This changeset alters the system
call to use the most general base class of the file descriptor
entries that can satisfy the code.
Change-Id: I10daf820257cea4d678ee6917e01e9cc9cd1cf5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17110
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Brandon Potter [Mon, 11 Mar 2019 18:13:47 +0000 (14:13 -0400)]
sim-se: add new option to getrlimit syscall
The NPROC option was not serviced by the getrlimit syscall.
This changeset adds in the necessary code to service the option.
Change-Id: I679d3949c3bbb0628188f4e33034028d7726fdcb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17109
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tiago Mück [Mon, 29 Jul 2019 18:45:31 +0000 (13:45 -0500)]
mem-cache: mark block as dirty when handling SW prefetch
This addresses the issue described in
64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp.
Previous patch misses cases when the prefetch response is ReadExResp or
UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets
instead of in handleFill covers cases when the prefetch is coalesced with
other requests.
Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19688
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Tue, 30 Jul 2019 07:41:14 +0000 (09:41 +0200)]
mem-cache: Fix set and way of sub-entries
Set and way of sub-entries were not being set previously.
They must be set after the sub-blocks have been assigned
to the main block.
Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19669
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 24 Jul 2019 11:22:05 +0000 (12:22 +0100)]
dev-arm: Rewrite SMMUv3 Commands
This patch is rewriting the SMMUv3::processCommand method for the
following reasons:
* Command names were not matching spec
* Command encoding/opcode was wrong
The patch is not adding any new command: there is still a subset of
unimplemented commands; those are:
* CMD_TLBI_EL3_ALL
* CMD_TLBI_EL3_VA
* CMD_TLBI_EL2_ALL
* CMD_TLBI_EL2_VA
* CMD_TLBI_EL2_VAA
* CMD_TLBI_EL2_ASID
which require StreamWorld support, and
* CMD_ATC_INV
* CMD_PRI_RESP
* CMD_RESUME
* CMD_STALL_TERM
which require in sequence: ATS, PRI, Stall Model support
Change-Id: Ia2dd47b5588738402d9584a00cfc88c94c253ad0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19668
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Chun-Chen TK Hsu [Mon, 29 Jul 2019 15:09:35 +0000 (23:09 +0800)]
configs, arch-arm: Check if gic has cpu_addr attribute
Add this check because Gicv3 does not have the cpu_addr attribute.
Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the
following command to boot Debian.
M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \
--dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \
--kernel $PWD/fs_files/binaries/vmlinux \
--disk $PWD/fs_files/disks/disk.img \
--cpu-type atomic --big-cpus 1 --little-cpus 0
Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Chun-Chen TK Hsu [Mon, 29 Jul 2019 11:51:21 +0000 (19:51 +0800)]
system-arm: Add irq for hypervisor timer in device tree
ARM fast model CPU cannot get timer interrupts without this IRQ setting
in the device tree.
Change-Id: I084c475c04285f4f40eb38a80ddd038207e4764f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19650
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Chun-Chen TK Hsu [Tue, 23 Jul 2019 10:51:16 +0000 (18:51 +0800)]
system-arm: Initialize ICC_SRE_EL3 register
Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized
before accessing other interrupt controller system registers.
Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabor Dozsa [Mon, 4 Feb 2019 14:39:08 +0000 (14:39 +0000)]
cpu: Fix the type of the effective mem request size
A memory request size can be larger than 255 bytes (e.g.
SVE with 2048-bit vector length) which could cause overflow
in the 'uint8_t effSize' variable.
Change-Id: I77e0d02a49ea7f81cacfa5be7e4ae40434af3109
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabor Dozsa [Thu, 15 Nov 2018 17:21:57 +0000 (17:21 +0000)]
cpu-o3: Fix too strict assert condition in writeback()
The assert() in the LSQ writeback() only allowed ReExec faults.
However, a SplitRequest which completed the translation in
PartialFault state (i.e. any but the very first cacheline
translation failed) may end up here. The assert() condition is
extended accordingly.
The patch also removes the superfluous/unused Complete/Squashed
states from the LSQ request. (The completion of the request is
recorded in the flags still.)
Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabor Dozsa [Tue, 18 Dec 2018 15:23:42 +0000 (15:23 +0000)]
arch-arm: Fix reg dependency for SVE gather microops
The first microop of an SVE gather creates a copy of the
source vecreg into AA64FpUreg0. The subsequent microops
must refer to this copy as a source in order to establish
the correct register dependencies.
Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19172
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabor Dozsa [Tue, 18 Dec 2018 15:11:05 +0000 (15:11 +0000)]
arch-arm: Fix tracing code for SVE gather
Printing the entire contents of the dest vecreg for each gather
microop is suboptimal as it creates false positive differences
between Atomic and O3 traces. This fix prints only the memory
data which a microop loads from memory.
Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19171
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Javier Setoain [Tue, 13 Nov 2018 17:32:54 +0000 (17:32 +0000)]
arch-arm: Add SVE LD1RQ[BHWD]
Add both scalar+scalar and scalar+immediate versions.
Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19170
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Adrià Armejach [Tue, 14 Aug 2018 13:27:19 +0000 (15:27 +0200)]
arch-arm: Fix decoding for SVE memory instructions
Some SVE memory instructions are missing the makeSP function for
register operands that can be the SP register. This leads to
segmentation faults on the application side as the wrong register is
decoded.
Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19169
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Javier Setoain [Wed, 4 Apr 2018 15:53:17 +0000 (16:53 +0100)]
arch-arm: Add support for SVE load/store structures
Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabor Dozsa [Wed, 27 Feb 2019 17:26:56 +0000 (17:26 +0000)]
cpu: Add first-/non-faulting load support to Minor and O3
Some architectures allow masking faults of memory load instructions in
some specific circumstances (e.g. first-faulting and non-faulting
loads in Arm SVE). This patch adds support for such loads in the Minor
and O3 CPU models.
Change-Id: I264a81a078f049127779aa834e89f0e693ba0bea
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 24 Jun 2019 15:41:26 +0000 (16:41 +0100)]
dev-arm: Fix SMMUv3 CMDQ wrapping
SMMU circular queues have a wrap bit which is used in order to
distinguish between an empty queue and a full queue.
According to SMMUv3 spec:
Each index has a wrap flag, represented by the next higher bit adjacent
to the index value contained in PROD and CONS. This bit must toggle each
time the index wraps off the high end and back onto the low end of the
buffer. It is the responsibility of the owner of each index, producer or
consumer, to toggle this bit when the owner updates the index after
wrapping. It is intended that software reads the register, increments or
wraps the index (toggling wrap when required) and writes back both wrap
and index fields at the same time.
Change-Id: Idfeb397141f3627c2878caaeaa2625fadf671d2a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19311
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Tue, 23 Jul 2019 08:58:39 +0000 (09:58 +0100)]
dev-arm: Polish SMMUv3 CMDQ setup
The patch is aiming to be spec compliant when it comes to setup
the SMMU command queue (while CR0.CMDQEN = 0), in the following ways:
* Writes to CMDQ_CONS (read index) are allowed during initialization
* Writes to CMDQ_BASE (cmdq pointer) are allowed during initialization
According to spec,
If they happen when the command queue is in fuction (CR0.CMDQEN = 1),
behaviour is constrained unpredictable, with the following options
1) The write is ignored
2) The register takes the value and it is unpredictable whether it
affects the SMMU command queue internal state.
In the model/patch we go for option 1.
Change-Id: I1c55bc571a8b3a1c0b0a525e429ab7b1480544ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19633
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 22 Jul 2019 16:38:29 +0000 (17:38 +0100)]
dev-arm: Define enum masks for SMMU_CR0 register
The configuration register is a vital register in the SMMU, and using
enum masks will make the code more readable/understandable
Change-Id: Ia117db56c457fe876ae38be391c386e502f34384
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19632
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Tue, 23 Jul 2019 15:34:26 +0000 (16:34 +0100)]
dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache
Otherwise a hit after a table walk will result in a 0 value being
read from the ConfigCache.
Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 22 Jul 2019 15:08:26 +0000 (16:08 +0100)]
dev-arm: SMMUv3 Table walks using TnSZ
TnSZ is needed when selecting the starting level of a table
walk, since it directly affects the number of IA bits.
This has been implemented by adding T0SZ and S2T0SZ to the
translation context.
T1SZ is not used at the moment since the current model doesn't
support TTB1.
Change-Id: I75663475c4dc01e5986cd93f8deafcdf7b1ece82
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Mon, 22 Jul 2019 14:06:40 +0000 (15:06 +0100)]
dev-arm: Use override keyword for SMMUv3 PTOPS
Replacing the "virtual" keyword
Change-Id: I0e7b4b683ea222827a67c3a81f0deea0e906c7e5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Michiel Van Tol [Mon, 22 Jul 2019 15:51:48 +0000 (16:51 +0100)]
dev-arm: Add 16K granule support to SMMUv3 model
Added the necessary PageTableOps that match the 16K granule
translation regime.
Change-Id: I46ef07939cb4bdc8c0bbbeeeb6a50a9ab0d64de0
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19628
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Pouya Fotouhi [Wed, 27 Feb 2019 21:25:22 +0000 (13:25 -0800)]
mem-ruby: Adding a new slicc statement - to not evict locked cachelines
Ruby caches block incoming ports with messages on a locked
address to make sure the line would not be replaced by others.
But they do not check the lock upon capacity/conflict misses.
This change adds a new slicc statement "check_on_cache_probe" which takes
two arguments (mandatoryQueue for the controller, and the line subject
to eviction - i.e. address returned by cacheProbe).
If the line is locked, incoming message is delayed for 1 cycle and the
controller skips this request (i.e. does not trigger an event).
Coherence protocols should be updated accordingly. One use case for MESI
Two Level will be added in a separate change.
Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Matthew Poremba [Fri, 12 Jul 2019 17:29:12 +0000 (10:29 -0700)]
arch-x86: Don't free PTW state with inflight requests
If a page table walk is squashed, the walker state is being deleted
in the squash code. If there are in flight requests, the deleted
walker state values may be clobbered, leading to undefined behavior.
This adds a squashed boolean to the walker state which is set if a
walk is squashed while requests are still in flight. When packets
for the in flight request return, we check if the walk was squashed
and return that the walk is complete once the number of in flight
requests reaches zero. The walker state is then freed by the PTW.
Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19568
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Thu, 18 Jul 2019 10:05:12 +0000 (11:05 +0100)]
arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disable
According to the armarm:
ARMv8.1-HPD introduces the facility to disable the hierarchical
attributes, APTable, PXNTable, and UXNTable, in the translation tables.
This disable has no effect on the NSTable bit. This feature is
mandatory in ARMv8.1 implementations.
This feature is added only to the VMSAv8-64 translation regimes. ARMv8.2
extends this to the AArch32 translation regimes, see ARMv8.2-AA32HPD.
The ID_AA64MMFR1_EL1.HPDS field identifies the support for ARMv8.1-HPD.
Change-Id: Ibbf589b82f2c1e4437b43252f8f633e8f6fb0b80
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19610
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Thu, 18 Jul 2019 09:50:21 +0000 (10:50 +0100)]
arch-arm: Add HPD bit for TCR_EL2/EL3
This is controlling Hierarchical Permissions for EL3 and for EL2 when
HCR_EL2.E2H = 0.
Change-Id: I9d6615ff4980cc56a28dc32088cf1524155f0fa4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19609
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 17 Jul 2019 16:00:13 +0000 (17:00 +0100)]
arch-arm: Clean Fault generation when processing Long Descriptor
A new shared method has been introduced: generateLongDescFault
Change-Id: I7eb6fa1347a6c2cf9cb11fd9f2137d983c4f7a40
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19608
Tested-by: kokoro <noreply+kokoro@google.com>
Matteo Andreozzi [Tue, 16 Jul 2019 17:43:56 +0000 (18:43 +0100)]
dev-arm: clang compatibility fix, added missing overrides
Change-Id: I5ee5ff788570178bb1d68878a26ac9e3ce636d8e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19588
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabor Dozsa [Tue, 11 Jun 2019 10:47:26 +0000 (11:47 +0100)]
arch-arm: Add first-/non-faulting load instructions
First-/non-faulting loads are part of Arm SVE.
Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabor Dozsa [Tue, 11 Jun 2019 10:47:16 +0000 (11:47 +0100)]
sim: Add getter to fault virtual address
Change-Id: Ifd493aee9e78b0b4ddcc71e90f48679543acb861
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19176
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Wed, 30 May 2018 12:31:06 +0000 (14:31 +0200)]
mem-cache: Create CPack compressor
Implementation of C-Pack, as described in "C-Pack: A High-
Performance Microprocessor Cache Compression Algorithm".
C-Pack uses pattern matching schemes to detect and compress
frequently appearing data patterns. As in the original paper,
it divides the input in 32-bit words, and uses 6 patterns to
match with its dictionary.
For the patterns, each letter represents a byte: Z is a null
byte, M is a dictionary match, X is a new value. The patterns
are ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX.
Change-Id: I2efc9db2c862620dcc1155300e39be558f9017e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11105
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 1 May 2019 14:21:03 +0000 (15:21 +0100)]
arch-arm: Use ExceptionLevel type in TlbEntry
Replacing uint8_t with ExceptionLevel type in the arm TlbEntry. The
variable is representing the translation regime it is targeting.
Change-Id: Ifcd6e86c5d73f752e8476a2b7fda9ea74a0c7a3b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19488
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Fri, 12 Jul 2019 19:09:30 +0000 (12:09 -0700)]
arch-x86: add unconditional tag to calls/returns
The branch predictor checks whether an instruction is unconditional
branch before adding it or checking the RAS. With this change, the
RAS is significantly more effective for short running x86 workloads.
Change-Id: I60af5f2f583b898ad77f79f4b0478d6cda88fc21
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19448
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Giacomo Travaglini [Wed, 26 Jun 2019 10:50:24 +0000 (11:50 +0100)]
dev-arm: Fix SMMUv3 ContextDescriptor pointer shift
The context descriptor pointer in the STE starts at the sixth LSB
Change-Id: Ifa346b350785b788e9d1e093b662cb26433adfb8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Christo Smallwood <christo.smallwood@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19469
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 28 Jun 2019 09:04:43 +0000 (10:04 +0100)]
cpu: isDrained renamed to isCpuDrained
cpu models inheriting from BaseCPU implement a draining checker called
isDrained. This hides the base Drainable::isDrained method and might
create confusion in the reader.
This patch is renaming it to isCpuDrained in order to avoid any
ambiguity
Change-Id: Ie5221da6a4673432c2403996e42d451cae960bbf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Chun-Chen TK Hsu [Thu, 11 Jul 2019 07:27:41 +0000 (15:27 +0800)]
mem: Check response only when needed in CommMonitor
CommMonitor checks pkt->isResponse() for all packets in recvAtomic().
This assertion fails when packets don't need response, such as WritebackDirty.
This change fixes this.
Signed-off-by: Chun-Chen TK Hsu
Change-Id: I168e349e179b14fa5472698d9300478dc89693fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19428
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Pouya Fotouhi [Fri, 12 Jul 2019 17:28:55 +0000 (12:28 -0500)]
cpu-o3: Set packet data type for IPR read
This change assigns packet data type to static for IPR read.
Caused by change (
e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169),
and has been reported a few times in the mailing list.
Change-Id: I0f02c20a16824e220df876e9e552bbc1c9636f95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19449
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tiago Muck [Thu, 16 May 2019 21:27:36 +0000 (16:27 -0500)]
dev-arm: A9SCU fixup
Shifting instead of expensive power.
Change-Id: I164933257db125e18721c5b8bcaf9702030ebf40
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Javier Bueno Hedo [Wed, 12 Jun 2019 13:42:19 +0000 (15:42 +0200)]
cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)
Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).
Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Gabor Dozsa [Thu, 15 Feb 2018 11:46:19 +0000 (11:46 +0000)]
cpu-o3: Reset fault status for mem access in pushRequest
Reset the fault status always before translation is initiated in
pushRequest() in the LSQ. This avoids the problem when a strictly
ordered load needs to be re-executed multiple times. If the
translation is delayed at one of those attempts then the
internal panicFault (from the previous execution attempt) can get
fired at commit.
Change-Id: I0c22b2f7afd6e2cb00bc359a4a01042efd2d01d2
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19388
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Wed, 8 May 2019 20:18:27 +0000 (22:18 +0200)]
mem-ruby: Fix MultiGrainBloomFilter accessing
When accessing the page filter the page hash should be used
instead of the hash of the base filter.
Change-Id: I17b7c64f2a0d654c7d9a77a7bfb435385d81032c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18739
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Tue, 7 May 2019 07:16:17 +0000 (09:16 +0200)]
mem-ruby: Remove Bloom Filters' ruby dependency
Substitute the common ruby header by base's bitfield to
eliminate all ruby dependency in Bloom Filters.
As a side note, BulkBloomFilter now assumes addresses are
64 bit long.
Change-Id: Ibdb1f926ddcc06c848851c1e6a34863541808360
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18738
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Tue, 7 May 2019 06:51:06 +0000 (08:51 +0200)]
mem-ruby: Parameterize block size in Bloom Filters
Substitute all occurrences of Ruby's block size by a
Python configurable offset.
Change-Id: If4913e842921447deda943b0482fb0c78a44c275
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18737
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Mon, 6 May 2019 21:49:21 +0000 (23:49 +0200)]
mem-ruby: Make Bloom Filters SimObjects
Make all bloom filters SimObjects.
Change-Id: I586293cdfb559361cb868b3198368e8b9b193356
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18736
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Sun, 5 May 2019 22:41:11 +0000 (00:41 +0200)]
mem-ruby: Generalize use of bloom filters' isSet
In general the corresponding entries of an address are considered
to be set when the sum of all of them reach their maximum value
(i.e., they are all set), so generalize that into the base class.
Change-Id: If50b8c56065ad339b4ff2322ddc3c077a3bfc518
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18735
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Sun, 5 May 2019 15:22:56 +0000 (17:22 +0200)]
mem-ruby: Cleanup filters
Renamed member variables to comply with general naming
conventional outside of the ruby folder so that the
filters can be moved out.
Moved code to base to reduce code duplication.
Renamed the private get_index functions to hash, to make their
functionality explicit.
Change-Id: Ic6519cfc5e09ea95bc502a29b27f750f04eda754
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18734
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Wed, 8 May 2019 20:21:06 +0000 (22:21 +0200)]
mem-ruby: Fix MultiGrainBloomFilter total count calculation
Previous value was always 0, and was never incrementing. The
total count should take into account the value stored in the
entry.
Change-Id: I93813e3f388198967b30cf11848a8a8c3a7b91f4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18733
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Sun, 5 May 2019 22:11:08 +0000 (00:11 +0200)]
mem-ruby: Remove index based functions in bloom filters
Most of the index based functions were not implemented, and a
user is more likely to be interested in checking the filter
contents based on an address than an index.
As a side effect, the Bulk's hash function became unused, and
according to the paper permute() was doing more than just
permuting, so it was renamed.
Change-Id: I6423a2565a082fee2e7f11fa489a11f253064d99
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18732
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Wed, 8 May 2019 10:11:36 +0000 (12:11 +0200)]
mem-ruby: Remove Bloom Filter's print()
Print was unused. As a side effect 'using namespace std' is no
longer needed.
Change-Id: Ief10cba1a11dfdd4edb7464eb9291fc83d6668cd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18731
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Wed, 8 May 2019 09:54:41 +0000 (11:54 +0200)]
mem-ruby: Standardize Bloom Filter deletion support
Standard Bloom Filters do not support element deletion by default,
however some variants do. Allow calling the unset function with
all filters, and do nothing by default.
Change-Id: Icf4b0f8b997c4c70fa714b2576474810275db78b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18730
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Mon, 6 May 2019 06:58:07 +0000 (08:58 +0200)]
mem-ruby: Bloom filters - Remove in/decrement
Increment and decrement were functions created to supply the
different naming convention used by the counting bloom filter.
They were removed, and the set and unset functions were used
in their place instead, as in the other filters.
Change-Id: I45732bdfa3083add0a975f374a0f3560003e9d09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18729
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Thu, 27 Jun 2019 12:39:11 +0000 (13:39 +0100)]
dev-arm: Use global import path for MemObject
Change-Id: I66e0ca6df689ec6aeb831ef5545e8e5842bb0418
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19348
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Michiel W. van Tol [Fri, 31 Aug 2018 11:50:20 +0000 (12:50 +0100)]
base: Add argument to Coroutine class to not run on creation
In some cases, the point where you create a Coroutine is not the same as
where you want to start running it (and want it to switch back to). This
leads to the unnecessary overhead of switching in and out of the
Coroutine. This change adds an optional boolean argument to the
constructor for the Coroutine class to allow for overriding the default
behavior of running the Coroutine upon creation, which in specific cases
can be used to avoid the unnecessary overhead and improve simulator
performance.
Change-Id: I044698f85e81ee4144208aee30d133bcb462d35d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18588
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Anouk Van Laer [Fri, 16 Nov 2018 15:45:00 +0000 (15:45 +0000)]
arch, arm: Update miscRegs in getTE
Normally, a translation will start via translateTiming/functional
which will check if the miscRegs have been updated and if so,
will update the TLB state accordingly. However, in a 2 stage
system, if there is a hit in stage 1, the resulting IPA will be
sent to the S2-TLB for translation via a getTE() function call
(via the stage2_lookup object). This will cause the state of the
S2-TLB to be out of sync.
Change-Id: I117e4032fc76d7d31f4f999887b5573a7e5811e6
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14995
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Giacomo Travaglini [Mon, 24 Jun 2019 15:31:08 +0000 (16:31 +0100)]
dev-arm: Remove un-needed Q_CONS_PROD_MASK macro
Change-Id: I858d7eea088bbdd2dc12123e21e59991c896597f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19310
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Adrian Herrera [Tue, 18 Jun 2019 15:56:18 +0000 (16:56 +0100)]
dev-arm: drain implementation for SMMUv3
SMMUv3 is drained when (1) no SMMU translations are pending
on any of its slave interfaces and (2) no commands are stored
in the Command Queue waiting to be processed.
Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Adrian Herrera [Tue, 18 Jun 2019 11:22:15 +0000 (12:22 +0100)]
dev-arm: pending SMMU transl update on constructor/destructor
Change-Id: I6f61651123aab129cfbe5a88aa6355cd21544a5e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19308
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 19 Jun 2019 12:03:38 +0000 (13:03 +0100)]
configs: Fix NULL dram-lowp regressions
The problem arises since there are some scripts (like NULL dram
regressions) which are making use of MemConfig.py without using
Opions.py so they won't have the new enable-dram-powerdown option
Change-Id: Id9769cce2e8a25b57da76f07eeebd279a6e00440
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19268
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Tue, 4 Jun 2019 12:21:30 +0000 (13:21 +0100)]
python: Add support for exporting static class methods from c++
This change adds support for exporting static methods in a c++
SimObject from the coressponsing python wrapper class. This will allow
us to define and use c++ methods without the need to instantiate an
object of the corresponding class.
Change-Id: Iaf24c1aa6f20feb5c91241f46ec8db005a6a0c0c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19168
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tiago Muck [Wed, 31 Oct 2018 21:39:44 +0000 (16:39 -0500)]
misc: dot_writer fixup
In large configs the tooltip may be greater then the maximum line
size graphviz supports when parsing the dot file (typically 16k).
Adding '/' causes graphviz to break the string in multiple lines
while parsing and works around this limitation.
Change-Id: I16a0030127de4165080de97f5213309eed9fdeca
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19208
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Thu, 13 Jun 2019 15:01:02 +0000 (16:01 +0100)]
python: Fix AddrRange legacy ParamValue wrapper
This change fixes a bug that would manifest if a user would
instantiate an AddrRange ParamValue using the kwargs 'intlvBits' and
'intlvHighBit' without specifying the optional 'xorHighBit'.
Change-Id: I2091c432234df9cf907d52af6ba7f0cadd8c37a8
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19248
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Tue, 11 Jun 2019 09:02:16 +0000 (10:02 +0100)]
arch-arm: Move the memacc_code before op_wb in fp loads
This is trying to fix the bug that arises when a memory exception
is generated during a fp flavoured load (A memory load targeting
a SIMD & FP register).
With the previous template a fault was not stopping the register
value to be modified (wrong)
if (fault == NoFault) {
fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
The patch introduces a Load64FpExecute template which is moving the
register write (memacc_code) just before the op_wb
Change-Id: I1c89c525dfa7a4ef489abe0872cd7baacdd6ce3c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 18 Jan 2019 10:19:16 +0000 (10:19 +0000)]
dev-arm: Reapply GICv3 changes that were lost during refactoring
The GICv3 code refactoring performed by:
https://gem5-review.googlesource.com/c/public/gem5/+/16484
reverted the following patches
https://gem5-review.googlesource.com/c/public/gem5/+/16544
https://gem5-review.googlesource.com/c/public/gem5/+/16545/3
This commit is reintroducing them
Change-Id: I2c875c11570ed66ec9203449446faca3864c64d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19229
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tiago Muck [Fri, 17 May 2019 18:15:33 +0000 (13:15 -0500)]
base: AddrRange does not merge single interleaved ranges
AddrRange does not attempt to merge interleaved address ranges if it
has only one of the ranges.
This is needed to allow XBars to accept request targeting only one
part of a interleaved address range. A use case for this would be
modeling distributed LLCs in which a XBar is used solely to
encapsulate the snoop filter of a single LLC slice.
Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18788
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tiago Muck [Tue, 29 Jan 2019 20:25:22 +0000 (14:25 -0600)]
cpu: Additional TrafficGen stats
Additional stats to keep track of read/write latencies and throughput.
Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18418
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tiago Muck [Mon, 28 Jan 2019 21:07:53 +0000 (15:07 -0600)]
cpu: Limit TrafficGen outstanding reqs
Parameter to limit the number of requests waiting for a response.
Change-Id: I6cf9e8782a06ae978fb66f7c4278f4c9e9980c79
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18417
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tiago Muck [Mon, 28 Jan 2019 20:57:17 +0000 (14:57 -0600)]
cpu: TrafficGen as BaseCPU
TrafficGen has additional attributes to behave like a BaseCPU. Python
scripts that expect sim. objects derived from BaseCPU can now be used with
TrafficGen without additional modifications.
Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18416
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Fri, 7 Jun 2019 12:37:56 +0000 (13:37 +0100)]
python: Fix cxx_ini_parse for ScopedEnum
Change-Id: I69534bbbc16b2d24a65fa1dee4926f213c3618ef
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19152
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Fri, 7 Jun 2019 12:31:09 +0000 (13:31 +0100)]
configs: Fix read_config to work with new AddrRange serialization
Change-Id: I122c77c34c2f8c75f8b32682be858f651112ce89
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19151
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Fri, 7 Jun 2019 12:28:07 +0000 (13:28 +0100)]
configs: Add python3 workarounds in read_config
Change-Id: Ib065f41b87e5ada9535b9c2645067162aa69234b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19150
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Sun, 26 May 2019 22:51:28 +0000 (23:51 +0100)]
python: Add binding for the new AddrRange c++ constructor
Change-Id: I5b3fb59a11d8587a753759310dd3b2748ac13a0b
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19132
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Sun, 26 May 2019 22:50:21 +0000 (23:50 +0100)]
base: Extend unit tests for AddrRange
Change-Id: Ia154c3a17c3c8254a0e3d622568ac34f0d62fc9e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19131
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Sun, 26 May 2019 22:33:48 +0000 (23:33 +0100)]
base: Extend AddrRange to support more flexible addressing
Previously an AddrRange could express interleaving using a number of
consecutive bits and in additional optionally a second number of
consecutive bits. The two sets of consecutive bits would be xored and
matched against a value to determine if an address is in the
AddrRange. For example:
sel[0] = a[8] ^ a[12]
sel[1] = a[9] ^ a[13]
where sel == intlvMatch
This change extends AddrRange to allow more flexible interleavings
with an abritary number of set of bits which do not need be
consecutive. For example:
sel[0] = a[8] ^ a[11] ^ a[13]
sel[1] = a[15] ^ a[17] ^ a[19]
where sel == intlvMatch
Change-Id: I42220a6d5011a31f0560535762a25bfc823c3ebb
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19130
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Nikos Nikoleris [Tue, 28 May 2019 20:23:50 +0000 (21:23 +0100)]
base: Fix ctz32 for systems where unsigned int is not 32bit
The implementation of ctz32 uses __builtin_ctz to count the number of
trailing zeros and therefore makes the assumption that an unsigned int
is 32bit. This change checks whether that's the case and if not it
uses __builtin_ctzl instead.
Change-Id: Ic3ed3ada25fd0a93c7eb91d75b954e9924bdbb77
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19129
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Nikos Nikoleris [Sun, 26 May 2019 22:31:22 +0000 (23:31 +0100)]
base: Add function to count trailing zeros in a 64-bit integer
Change-Id: Iaad0679b403bc5015ffeacbf7284313e41a36cd0
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19128
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Ciro Santilli [Tue, 21 May 2019 12:19:24 +0000 (13:19 +0100)]
scons: allow passing arbitrary CCFLAGS and LDFLAGS from the CLI
The flags may be passed as:
scons CCFLAGS_EXTRA='-Wno-error -pedantic' \
LDFLAGS_EXTRA='-g -g' build/<arch>/gem5.opt
The initial motivation for this commit is to help disable warning that
have become errors while bisecting.
scons orders the flags by Append call order, and ideally these flags
should be added last to override the others, since the last GCC flags
take precedence. However I haven't found a simple way to put them at
the very end.
Change-Id: Ida24dfb9604d88b99f113392ab5e47d578ba7259
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19048
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Ciro Santilli [Fri, 31 May 2019 15:08:09 +0000 (16:08 +0100)]
arch-arm: implement VMINNM scalar thumb
VMINNM was implemented at Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 but
the thumb scalar encoding was missing. This patch implements it.
Change-Id: Ia29ec77dbd82f6be6b3d040a0e737794f52c33bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19108
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 3 May 2019 12:51:50 +0000 (13:51 +0100)]
base: Provide a getter for Fiber::started boolean variable
This can be used to check if the fiber has started its execution.
Change-Id: Ie9222b8076756363c9f82c1333c76a352bcaf817
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18648
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 7 Jun 2019 13:10:47 +0000 (14:10 +0100)]
base: Rename TestFiber into SwitchingFiber
This is done since TestFiber is too generic and it is not the only
Fiber's testing subclass in the unit test
Change-Id: Idc386f487091ae9bdadae865090a6719a25583da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19153
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Thu, 6 Jun 2019 22:03:07 +0000 (23:03 +0100)]
arch-arm: Fix WalkerState,Descriptors default constructor
Those POD strutures are not initializing all members at construction.
This could lead to undefined behaviour
Change-Id: Iaa8afb126382b6bfbef686883a026262f24d5ca1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Javier Setoain <javier.setoain@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19149
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Stanislaw Czerniawski [Tue, 5 Mar 2019 10:27:56 +0000 (10:27 +0000)]
dev-arm: Implement a SMMUv3 model
This is an implementation of the SMMUv3 architecture.
What can it do?
- Single-stage and nested translation with 4k or 64k granule. 16k would
be straightforward to add.
- Large pages are supported.
- Works with any gem5 device as long as it is issuing packets with a
valid (Sub)StreamId
What it can't do?
- Fragment stage 1 page when the underlying stage 2 page is smaller. S1
page size > S2 page size is not supported
- Invalidations take zero time. This wouldn't be hard to fix.
- Checkpointing is not supported
- Stall/resume for faulting transactions is not supported
Additional contributors:
- Michiel W. van Tol <Michiel.VanTol@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19008
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Matthew Poremba [Wed, 1 May 2019 18:32:49 +0000 (11:32 -0700)]
mem: Option to toggle DRAM low-power states
Adding an option to enable DRAM low-power states. The low power
states can have a significant impact on application performance
(sim_ticks) on the order of 2-3x, especially for compute-gpu apps.
The options allows for it to easily be enabled/disabled to compare
performance numbers. The option is disabled by default.
Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>