Clifford Wolf [Sun, 14 Sep 2014 14:09:06 +0000 (16:09 +0200)]
Added "synth" command
Clifford Wolf [Sun, 14 Sep 2014 13:34:36 +0000 (15:34 +0200)]
Fixed techmap_wrap for techmap_celltype
Clifford Wolf [Sun, 14 Sep 2014 12:50:15 +0000 (14:50 +0200)]
Using alumacc in techmap.v
Clifford Wolf [Sun, 14 Sep 2014 12:49:53 +0000 (14:49 +0200)]
Various fixes/cleanups in alumacc and maccmap
Clifford Wolf [Sun, 14 Sep 2014 12:49:26 +0000 (14:49 +0200)]
Added techmap_wrap attribute
Clifford Wolf [Sun, 14 Sep 2014 12:00:14 +0000 (14:00 +0200)]
alumacc fix for $pos cells
Clifford Wolf [Sun, 14 Sep 2014 11:23:44 +0000 (13:23 +0200)]
Extract $alu cells in alumacc
Clifford Wolf [Sun, 14 Sep 2014 09:21:37 +0000 (11:21 +0200)]
Merge $macc cells in alumacc pass
Clifford Wolf [Sun, 14 Sep 2014 08:45:28 +0000 (10:45 +0200)]
Basic $macc extract in alumacc
Clifford Wolf [Sun, 14 Sep 2014 08:02:00 +0000 (10:02 +0200)]
alumacc skeleton
Clifford Wolf [Sun, 14 Sep 2014 08:01:30 +0000 (10:01 +0200)]
Cleanup in wreduce
Clifford Wolf [Sat, 13 Sep 2014 15:28:15 +0000 (17:28 +0200)]
Using pkg-config to find libffi
Clifford Wolf [Mon, 8 Sep 2014 15:09:39 +0000 (17:09 +0200)]
Fixed simlib $macc model for xilinx xsim
Clifford Wolf [Mon, 8 Sep 2014 14:59:39 +0000 (16:59 +0200)]
Simplified $fa undef model
Clifford Wolf [Mon, 8 Sep 2014 11:29:13 +0000 (13:29 +0200)]
Fixes and cleanups for blackbox.v
Clifford Wolf [Mon, 8 Sep 2014 11:28:23 +0000 (13:28 +0200)]
Added $lcu cell type
Clifford Wolf [Mon, 8 Sep 2014 10:25:23 +0000 (12:25 +0200)]
Another $clog2 bugfix
Clifford Wolf [Mon, 8 Sep 2014 10:15:39 +0000 (12:15 +0200)]
Added "$fa" cell type
Clifford Wolf [Mon, 8 Sep 2014 09:21:58 +0000 (11:21 +0200)]
Trim msb/lsb zero bits from full adder in maccmap
Clifford Wolf [Mon, 8 Sep 2014 09:12:39 +0000 (11:12 +0200)]
Added "test_cell -const"
Clifford Wolf [Sun, 7 Sep 2014 16:24:08 +0000 (18:24 +0200)]
Using maccmap for $macc and $mul techmap
Clifford Wolf [Sun, 7 Sep 2014 16:23:37 +0000 (18:23 +0200)]
Added 'techmap_maccmap' techmap attribute
Clifford Wolf [Sun, 7 Sep 2014 16:23:04 +0000 (18:23 +0200)]
Added "maccmap" command
Clifford Wolf [Sun, 7 Sep 2014 15:05:41 +0000 (17:05 +0200)]
Added "test_cell -nosat"
Clifford Wolf [Sat, 6 Sep 2014 18:30:46 +0000 (20:30 +0200)]
Various bug fixes (related to $macc model testing)
Clifford Wolf [Sat, 6 Sep 2014 17:44:28 +0000 (19:44 +0200)]
Added $macc eval model
Clifford Wolf [Sat, 6 Sep 2014 17:44:11 +0000 (19:44 +0200)]
Added $macc SAT model
Clifford Wolf [Sat, 6 Sep 2014 17:31:04 +0000 (19:31 +0200)]
Fixed $clog2 (off by one error)
Clifford Wolf [Sat, 6 Sep 2014 15:59:12 +0000 (17:59 +0200)]
Added $macc simlib model (also use as techmap rule for now)
Clifford Wolf [Sat, 6 Sep 2014 15:58:27 +0000 (17:58 +0200)]
Fixed assignment of out-of bounds array element
Clifford Wolf [Sat, 6 Sep 2014 13:47:46 +0000 (15:47 +0200)]
Added $macc cell type
Clifford Wolf [Sat, 6 Sep 2014 10:10:57 +0000 (12:10 +0200)]
Fixed autotest for non-basename arguments
Clifford Wolf [Sat, 6 Sep 2014 09:46:44 +0000 (11:46 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Sat, 6 Sep 2014 09:46:07 +0000 (11:46 +0200)]
Added "test_cell -script"
Clifford Wolf [Sat, 6 Sep 2014 08:15:47 +0000 (10:15 +0200)]
Merge pull request #38 from rubund/master
Corrected spelling mistakes found by lintian
Ruben Undheim [Sat, 6 Sep 2014 06:47:06 +0000 (08:47 +0200)]
Corrected spelling mistakes found by lintian
Clifford Wolf [Thu, 4 Sep 2014 13:07:30 +0000 (15:07 +0200)]
Added tests/various/constmsk_test.ys
Clifford Wolf [Thu, 4 Sep 2014 06:55:58 +0000 (08:55 +0200)]
Fixed "opt_const -fine" for $pos cells
Clifford Wolf [Thu, 4 Sep 2014 00:07:52 +0000 (02:07 +0200)]
Removed $bu0 cell type
Clifford Wolf [Wed, 3 Sep 2014 19:20:59 +0000 (21:20 +0200)]
Using $pos models for $bu0
Clifford Wolf [Wed, 3 Sep 2014 11:43:37 +0000 (13:43 +0200)]
Fixed "test_cells -vlog"
Clifford Wolf [Wed, 3 Sep 2014 11:39:46 +0000 (13:39 +0200)]
Fixes in $alu SAT- and eval-models
Clifford Wolf [Tue, 2 Sep 2014 21:21:59 +0000 (23:21 +0200)]
Undef-related fixes in simlib $alu model
Clifford Wolf [Tue, 2 Sep 2014 21:21:15 +0000 (23:21 +0200)]
Improvements in "test_cell -vlog"
Clifford Wolf [Tue, 2 Sep 2014 20:49:43 +0000 (22:49 +0200)]
Added test_cell -vlog
Clifford Wolf [Tue, 2 Sep 2014 20:49:24 +0000 (22:49 +0200)]
Create a default selection stack in RTLIL::Design::Design()
Clifford Wolf [Tue, 2 Sep 2014 15:48:41 +0000 (17:48 +0200)]
Small bug fixes in $not, $neg, and $shiftx models
Clifford Wolf [Tue, 2 Sep 2014 15:28:13 +0000 (17:28 +0200)]
Added SAT testing to test_cell eval stage
Clifford Wolf [Tue, 2 Sep 2014 02:03:06 +0000 (04:03 +0200)]
Removed references to yosys-svgviewer from docs
Clifford Wolf [Tue, 2 Sep 2014 01:52:46 +0000 (03:52 +0200)]
Removed yosys-svgviewer
Clifford Wolf [Tue, 2 Sep 2014 01:28:46 +0000 (03:28 +0200)]
Using "xdot" instead of "yosys-svgviewer" in show command
Clifford Wolf [Mon, 1 Sep 2014 14:36:04 +0000 (16:36 +0200)]
Added $alu support to test_cell
Clifford Wolf [Mon, 1 Sep 2014 14:35:46 +0000 (16:35 +0200)]
Added ConstEval model for $alu cells
Clifford Wolf [Mon, 1 Sep 2014 14:35:25 +0000 (16:35 +0200)]
Added SAT model for $alu cells
Clifford Wolf [Mon, 1 Sep 2014 13:37:56 +0000 (15:37 +0200)]
Fixed "test_cell -simlib all"
Clifford Wolf [Mon, 1 Sep 2014 13:37:21 +0000 (15:37 +0200)]
Added "test_cell -simlib -v"
Clifford Wolf [Mon, 1 Sep 2014 13:36:29 +0000 (15:36 +0200)]
Added "techmap -autoproc"
Clifford Wolf [Mon, 1 Sep 2014 09:45:47 +0000 (11:45 +0200)]
Fixes in old SAT example.ys
Clifford Wolf [Mon, 1 Sep 2014 09:45:26 +0000 (11:45 +0200)]
Moved "share" and "wreduce" to passes/opt/
Clifford Wolf [Mon, 1 Sep 2014 09:36:02 +0000 (11:36 +0200)]
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
Clifford Wolf [Sun, 31 Aug 2014 16:08:42 +0000 (18:08 +0200)]
Added eval testing to test_cell
Clifford Wolf [Sun, 31 Aug 2014 16:08:26 +0000 (18:08 +0200)]
Fixed return size of const_*() eval functions
Clifford Wolf [Sun, 31 Aug 2014 16:07:48 +0000 (18:07 +0200)]
Added RTLIL::Const::size()
Clifford Wolf [Sun, 31 Aug 2014 15:42:38 +0000 (17:42 +0200)]
Added eval model for $lut cells
Clifford Wolf [Sun, 31 Aug 2014 15:07:07 +0000 (17:07 +0200)]
Typo fixes in cell->*Param() API
Clifford Wolf [Sun, 31 Aug 2014 15:06:36 +0000 (17:06 +0200)]
Added $lut support in test_cell, techmap, satgen
Clifford Wolf [Sat, 30 Aug 2014 17:37:12 +0000 (19:37 +0200)]
Added design->scratchpad
Clifford Wolf [Sat, 30 Aug 2014 16:59:05 +0000 (18:59 +0200)]
Added $alu cell type
Clifford Wolf [Sat, 30 Aug 2014 16:34:07 +0000 (18:34 +0200)]
Added autotest -e (do not use -noexpr on write_verilog)
Clifford Wolf [Sat, 30 Aug 2014 16:18:15 +0000 (18:18 +0200)]
Improved write address decoder generation memory_map
Clifford Wolf [Sat, 30 Aug 2014 16:17:22 +0000 (18:17 +0200)]
Fixed module->addPmux()
Clifford Wolf [Sat, 30 Aug 2014 15:39:08 +0000 (17:39 +0200)]
Using worker class in memory_map
Clifford Wolf [Sat, 30 Aug 2014 13:12:39 +0000 (15:12 +0200)]
Replaced $__alu CO/CS outputs with full-width CO output
Clifford Wolf [Sat, 30 Aug 2014 12:43:06 +0000 (14:43 +0200)]
Don't change existing binary FSM encoding if it is already optimal
Clifford Wolf [Sat, 30 Aug 2014 12:34:49 +0000 (14:34 +0200)]
Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
Clifford Wolf [Sat, 30 Aug 2014 12:11:57 +0000 (14:11 +0200)]
Improved handling of $pmux cells in fsm_extract
Clifford Wolf [Wed, 27 Aug 2014 17:44:12 +0000 (19:44 +0200)]
Fixed inserting of Q-inverters in dfflibmap
Clifford Wolf [Wed, 27 Aug 2014 10:13:53 +0000 (12:13 +0200)]
Fixed printing of multi-line Makefile.conf
Clifford Wolf [Tue, 26 Aug 2014 10:51:08 +0000 (12:51 +0200)]
Implemented "rename -enumerate -pattern"
Clifford Wolf [Tue, 26 Aug 2014 08:11:46 +0000 (10:11 +0200)]
Print Makefile.conf as make info message
Clifford Wolf [Mon, 25 Aug 2014 10:48:20 +0000 (12:48 +0200)]
Checking for valid CONFIG value in Makefile
Clifford Wolf [Sun, 24 Aug 2014 15:08:07 +0000 (17:08 +0200)]
Optimize shift ops with constant rhs in opt_const
Clifford Wolf [Sun, 24 Aug 2014 13:14:45 +0000 (15:14 +0200)]
Added some additional log messages to opt_const
Clifford Wolf [Sun, 24 Aug 2014 13:14:00 +0000 (15:14 +0200)]
Added is_signed argument to SigSpec.as_int() and Const.as_int()
Clifford Wolf [Sun, 24 Aug 2014 11:27:40 +0000 (13:27 +0200)]
azonenberg: Make dump_vcd save model when temporal induction fails due to step limit
Clifford Wolf [Sat, 23 Aug 2014 13:32:00 +0000 (15:32 +0200)]
Only call proc_share_dirname() in techmap when necessary
Clifford Wolf [Sat, 23 Aug 2014 13:14:58 +0000 (15:14 +0200)]
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf [Sat, 23 Aug 2014 13:03:55 +0000 (15:03 +0200)]
Changed frontend-api from FILE to std::istream
Clifford Wolf [Sat, 23 Aug 2014 11:54:21 +0000 (13:54 +0200)]
Changed backend-api from FILE to std::ostream
Clifford Wolf [Fri, 22 Aug 2014 15:20:28 +0000 (17:20 +0200)]
Added "stat -width"
Clifford Wolf [Fri, 22 Aug 2014 14:09:13 +0000 (16:09 +0200)]
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf [Fri, 22 Aug 2014 12:37:14 +0000 (14:37 +0200)]
Added DPI-C documentation to README file
Clifford Wolf [Fri, 22 Aug 2014 12:30:29 +0000 (14:30 +0200)]
Added support for non-standard <plugin>:<c_name> DPI syntax
Clifford Wolf [Fri, 22 Aug 2014 12:22:09 +0000 (14:22 +0200)]
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
Clifford Wolf [Fri, 22 Aug 2014 11:58:36 +0000 (13:58 +0200)]
Added "plugin" command
Clifford Wolf [Fri, 22 Aug 2014 10:20:23 +0000 (12:20 +0200)]
Updated ABC to
4d547a5e065b
Clifford Wolf [Thu, 21 Aug 2014 15:40:49 +0000 (17:40 +0200)]
Cosmetic changes to FSM tests
Clifford Wolf [Thu, 21 Aug 2014 15:33:40 +0000 (17:33 +0200)]
Fixed small memory leak in ast simplify
Clifford Wolf [Thu, 21 Aug 2014 15:22:04 +0000 (17:22 +0200)]
Added support for DPI function with different names in C and Verilog
Clifford Wolf [Thu, 21 Aug 2014 15:11:51 +0000 (17:11 +0200)]
Added AstNode::asInt()