yosys.git
5 years agoRefactor SF2 iobuf insertion, Add clkint insertion
Clifford Wolf [Wed, 6 Mar 2019 08:41:02 +0000 (00:41 -0800)]
Refactor SF2 iobuf insertion, Add clkint insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove igloo2 example
Clifford Wolf [Wed, 6 Mar 2019 04:47:07 +0000 (20:47 -0800)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove igloo2 example
Clifford Wolf [Wed, 6 Mar 2019 04:35:48 +0000 (20:35 -0800)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprovements in SF2 flow and demo
Clifford Wolf [Wed, 6 Mar 2019 03:49:39 +0000 (19:49 -0800)]
Improvements in SF2 flow and demo

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix spelling in pmgen/README.md
Eddie Hung [Wed, 6 Mar 2019 01:55:29 +0000 (17:55 -0800)]
Fix spelling in pmgen/README.md

5 years agoImprove igloo2 exmaple
Clifford Wolf [Wed, 6 Mar 2019 01:27:58 +0000 (17:27 -0800)]
Improve igloo2 exmaple

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #842 from litghost/merge_upstream
Clifford Wolf [Tue, 5 Mar 2019 23:33:19 +0000 (15:33 -0800)]
Merge pull request #842 from litghost/merge_upstream

Changes required for VPR place and route in synth_xilinx

5 years agoMerge pull request #850 from daveshah1/ecp5_warn_conflict
Clifford Wolf [Tue, 5 Mar 2019 23:23:01 +0000 (15:23 -0800)]
Merge pull request #850 from daveshah1/ecp5_warn_conflict

ecp5: Demote conflicting FF init values to a warning

5 years agoAdd missing newline
Clifford Wolf [Tue, 5 Mar 2019 23:21:04 +0000 (15:21 -0800)]
Add missing newline

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #851 from kprasadvnsi/master
Clifford Wolf [Tue, 5 Mar 2019 23:20:03 +0000 (15:20 -0800)]
Merge pull request #851 from kprasadvnsi/master

Added examples/anlogic/

5 years agoMerge pull request #852 from ucb-bar/firrtlfixes
Clifford Wolf [Tue, 5 Mar 2019 23:19:28 +0000 (15:19 -0800)]
Merge pull request #852 from ucb-bar/firrtlfixes

Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails

5 years agoUse "write_edif -pvector bra" for Xilinx EDIF files
Clifford Wolf [Tue, 5 Mar 2019 23:16:13 +0000 (15:16 -0800)]
Use "write_edif -pvector bra" for Xilinx EDIF files

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoEnsure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Jim Lawson [Mon, 4 Mar 2019 21:23:58 +0000 (13:23 -0800)]
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".

5 years agoAdded examples/anlogic/
Kali Prasad [Mon, 4 Mar 2019 17:56:56 +0000 (23:26 +0530)]
Added examples/anlogic/

5 years agoRevert BRAM WRITE_MODE changes.
Keith Rothman [Mon, 4 Mar 2019 17:22:22 +0000 (09:22 -0800)]
Revert BRAM WRITE_MODE changes.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoecp5: Demote conflicting FF init values to a warning
David Shah [Mon, 4 Mar 2019 11:18:53 +0000 (11:18 +0000)]
ecp5: Demote conflicting FF init values to a warning

Signed-off-by: David Shah <dave@ds0.me>
5 years agoImprove igloo2 example
Clifford Wolf [Mon, 4 Mar 2019 07:54:35 +0000 (23:54 -0800)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUpdate igloo2 example to Libero v12.0
Clifford Wolf [Mon, 4 Mar 2019 05:35:57 +0000 (21:35 -0800)]
Update igloo2 example to Libero v12.0

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #848 from YosysHQ/clifford/fix763
Clifford Wolf [Sun, 3 Mar 2019 00:32:58 +0000 (16:32 -0800)]
Merge pull request #848 from YosysHQ/clifford/fix763

Fix error for wire decl in always block, fixes 763

5 years agoMerge pull request #849 from YosysHQ/clifford/dynports
Clifford Wolf [Sun, 3 Mar 2019 00:01:31 +0000 (16:01 -0800)]
Merge pull request #849 from YosysHQ/clifford/dynports

Only run derive on blackbox modules when ports have dynamic size

5 years agoOnly run derive on blackbox modules when ports have dynamic size
Clifford Wolf [Sat, 2 Mar 2019 20:36:46 +0000 (12:36 -0800)]
Only run derive on blackbox modules when ports have dynamic size

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix error for wire decl in always block, fixes #763
Clifford Wolf [Sat, 2 Mar 2019 19:40:57 +0000 (11:40 -0800)]
Fix error for wire decl in always block, fixes #763

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix $global_clock handling vs autowire
Clifford Wolf [Sat, 2 Mar 2019 18:38:13 +0000 (10:38 -0800)]
Fix $global_clock handling vs autowire

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #847 from YosysHQ/clifford/fix785
Clifford Wolf [Sat, 2 Mar 2019 18:27:58 +0000 (10:27 -0800)]
Merge pull request #847 from YosysHQ/clifford/fix785

Fix $readmem[hb] for mem2reg memories, fixes #785

5 years agoFix $readmem[hb] for mem2reg memories, fixes #785
Clifford Wolf [Sat, 2 Mar 2019 17:58:20 +0000 (09:58 -0800)]
Fix $readmem[hb] for mem2reg memories, fixes #785

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #843 from YosysHQ/clifford/mem2regconstidx
Clifford Wolf [Sat, 2 Mar 2019 16:40:54 +0000 (08:40 -0800)]
Merge pull request #843 from YosysHQ/clifford/mem2regconstidx

Use mem2reg on memories that only have constant-index write ports

5 years agoMerge pull request #845 from YosysHQ/clifford/travisnomacos
Clifford Wolf [Sat, 2 Mar 2019 16:40:17 +0000 (08:40 -0800)]
Merge pull request #845 from YosysHQ/clifford/travisnomacos

Disable macOS builds in Travis

5 years agoDisable macOS builds in Travis
Clifford Wolf [Sat, 2 Mar 2019 16:29:28 +0000 (08:29 -0800)]
Disable macOS builds in Travis

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoTry again for passes/pmgen/ice40_dsp_pm.h rule
Larry Doolittle [Sat, 2 Mar 2019 04:15:20 +0000 (20:15 -0800)]
Try again for passes/pmgen/ice40_dsp_pm.h rule

Tested on both in-tree and out-of-tree builds

5 years agoRevert FF models to include IS_x_INVERTED parameters.
Keith Rothman [Fri, 1 Mar 2019 22:41:21 +0000 (14:41 -0800)]
Revert FF models to include IS_x_INVERTED parameters.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoUse singular for disabling of DRAM or BRAM inference.
Keith Rothman [Fri, 1 Mar 2019 22:35:14 +0000 (14:35 -0800)]
Use singular for disabling of DRAM or BRAM inference.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoMinor improvements in README
Clifford Wolf [Fri, 1 Mar 2019 22:29:17 +0000 (14:29 -0800)]
Minor improvements in README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUse mem2reg on memories that only have constant-index write ports
Clifford Wolf [Fri, 1 Mar 2019 21:35:09 +0000 (13:35 -0800)]
Use mem2reg on memories that only have constant-index write ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix "write_edif -gndvccy"
Clifford Wolf [Fri, 1 Mar 2019 20:59:07 +0000 (12:59 -0800)]
Fix "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoModify arguments to match existing style.
Keith Rothman [Fri, 1 Mar 2019 20:14:27 +0000 (12:14 -0800)]
Modify arguments to match existing style.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoChanges required for VPR place and route synth_xilinx.
Keith Rothman [Fri, 1 Mar 2019 19:21:07 +0000 (11:21 -0800)]
Changes required for VPR place and route synth_xilinx.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoMerge pull request #841 from mmicko/master
Clifford Wolf [Fri, 1 Mar 2019 18:53:23 +0000 (10:53 -0800)]
Merge pull request #841 from mmicko/master

Fix ECP5 cells_sim for iverilog

5 years agoFix ECP5 cells_sim for iverilog
Miodrag Milanovic [Fri, 1 Mar 2019 18:25:23 +0000 (19:25 +0100)]
Fix ECP5 cells_sim for iverilog

5 years agoImprove "read" error msg
Clifford Wolf [Fri, 1 Mar 2019 04:34:42 +0000 (20:34 -0800)]
Improve "read" error msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
Clifford Wolf [Fri, 1 Mar 2019 04:27:27 +0000 (20:27 -0800)]
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

5 years agoHotfix for "make test"
Clifford Wolf [Fri, 1 Mar 2019 04:26:54 +0000 (20:26 -0800)]
Hotfix for "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #837 from YosysHQ/clifford/fix835
Clifford Wolf [Fri, 1 Mar 2019 01:40:38 +0000 (17:40 -0800)]
Merge pull request #837 from YosysHQ/clifford/fix835

Fix multiple issues in wreduce FF handling, fixes #835

5 years agoFix multiple issues in wreduce FF handling, fixes #835
Clifford Wolf [Fri, 1 Mar 2019 01:24:46 +0000 (17:24 -0800)]
Fix multiple issues in wreduce FF handling, fixes #835

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoice40: use 2 bits for READ/WRITE MODE for SB_RAM map
Elms [Fri, 1 Mar 2019 00:22:24 +0000 (16:22 -0800)]
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>
5 years agoMerge pull request #834 from YosysHQ/clifford/siminit
Clifford Wolf [Thu, 28 Feb 2019 23:03:55 +0000 (15:03 -0800)]
Merge pull request #834 from YosysHQ/clifford/siminit

Add "write_verilog -siminit"

5 years agoAdd "write_verilog -siminit"
Clifford Wolf [Thu, 28 Feb 2019 22:56:55 +0000 (14:56 -0800)]
Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoReduce amount of trailing whitespace in code base
Larry Doolittle [Tue, 26 Feb 2019 18:28:42 +0000 (10:28 -0800)]
Reduce amount of trailing whitespace in code base

5 years agoFix pmgen for in-tree builds
Clifford Wolf [Thu, 28 Feb 2019 22:56:05 +0000 (14:56 -0800)]
Fix pmgen for in-tree builds

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #794 from daveshah1/ecp5improve
Clifford Wolf [Thu, 28 Feb 2019 22:46:56 +0000 (14:46 -0800)]
Merge pull request #794 from daveshah1/ecp5improve

ECP5 Improvements

5 years agoMerge pull request #827 from ucb-bar/firrtlfixes
Clifford Wolf [Thu, 28 Feb 2019 22:45:04 +0000 (14:45 -0800)]
Merge pull request #827 from ucb-bar/firrtlfixes

Fix FIRRTL to Verilog process instance subfield assignment.

5 years agoFix pmgen for out-of-tree build
Clifford Wolf [Thu, 28 Feb 2019 22:00:58 +0000 (14:00 -0800)]
Fix pmgen for out-of-tree build

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #833 from YosysHQ/clifford/fix831
Clifford Wolf [Thu, 28 Feb 2019 21:40:27 +0000 (13:40 -0800)]
Merge pull request #833 from YosysHQ/clifford/fix831

Fix smt2 code generation for partially initialized memory words, fixe…

5 years agoFix smt2 code generation for partially initialized memowy words, fixes #831
Clifford Wolf [Thu, 28 Feb 2019 20:15:58 +0000 (12:15 -0800)]
Fix smt2 code generation for partially initialized memowy words, fixes #831

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #832 from YosysHQ/supercover
Clifford Wolf [Thu, 28 Feb 2019 20:08:01 +0000 (12:08 -0800)]
Merge pull request #832 from YosysHQ/supercover

Add "supercover" pass

5 years agoImprovements in "supercover" pass
Clifford Wolf [Wed, 27 Feb 2019 19:45:13 +0000 (11:45 -0800)]
Improvements in "supercover" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "supercover" skeleton
Clifford Wolf [Wed, 27 Feb 2019 19:37:08 +0000 (11:37 -0800)]
Add "supercover" skeleton

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agotechlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
Larry Doolittle [Mon, 25 Feb 2019 06:09:54 +0000 (22:09 -0800)]
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module

5 years agoClean up some whitepsace outliers
Larry Doolittle [Mon, 25 Feb 2019 06:08:52 +0000 (22:08 -0800)]
Clean up some whitepsace outliers

5 years agoFix FIRRTL to Verilog process instance subfield assignment.
Jim Lawson [Tue, 26 Feb 2019 00:18:13 +0000 (16:18 -0800)]
Fix FIRRTL to Verilog process instance subfield assignment.
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)

5 years agoecp5: Compatibility with Migen AsyncResetSynchronizer
David Shah [Tue, 19 Feb 2019 19:35:10 +0000 (19:35 +0000)]
ecp5: Compatibility with Migen AsyncResetSynchronizer

Signed-off-by: David Shah <davey1576@gmail.com>
5 years agoMinor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
Clifford Wolf [Sun, 24 Feb 2019 19:41:36 +0000 (20:41 +0100)]
Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #812 from ucb-bar/arrayhierarchyfixes
Clifford Wolf [Sun, 24 Feb 2019 19:39:13 +0000 (11:39 -0800)]
Merge pull request #812 from ucb-bar/arrayhierarchyfixes

Define basic_cell_type() function and use it to derive the cell type …

5 years agoCleanups in ARST handling in wreduce
Clifford Wolf [Sun, 24 Feb 2019 19:34:23 +0000 (20:34 +0100)]
Cleanups in ARST handling in wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #824 from litghost/fix_reduce_on_ff
Clifford Wolf [Sun, 24 Feb 2019 19:29:14 +0000 (11:29 -0800)]
Merge pull request #824 from litghost/fix_reduce_on_ff

Fix WREDUCE on FF not fixing ARST_VALUE parameter.

5 years agoFix handling of defparam for when default_nettype is none
Clifford Wolf [Sun, 24 Feb 2019 19:09:41 +0000 (20:09 +0100)]
Fix handling of defparam for when default_nettype is none

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoCheck if Verific was built with DB_PRESERVE_INITIAL_VALUE
Clifford Wolf [Sun, 24 Feb 2019 18:51:30 +0000 (19:51 +0100)]
Check if Verific was built with DB_PRESERVE_INITIAL_VALUE

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAddress requested changes - don't require non-$ name.
Jim Lawson [Sat, 23 Feb 2019 00:06:10 +0000 (16:06 -0800)]
Address requested changes - don't require non-$ name.
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.

5 years agoFix WREDUCE on FF not fixing ARST_VALUE parameter.
Keith Rothman [Fri, 22 Feb 2019 18:28:28 +0000 (10:28 -0800)]
Fix WREDUCE on FF not fixing ARST_VALUE parameter.

Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoMerge pull request #819 from YosysHQ/clifford/optd
Clifford Wolf [Fri, 22 Feb 2019 05:55:48 +0000 (06:55 +0100)]
Merge pull request #819 from YosysHQ/clifford/optd

Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior

5 years agoMerge pull request #820 from YosysHQ/clifford/fix810
Clifford Wolf [Fri, 22 Feb 2019 05:54:48 +0000 (06:54 +0100)]
Merge pull request #820 from YosysHQ/clifford/fix810

Fix #810 and fix #814

5 years agoMerge pull request #740 from daveshah1/improve_dress
Clifford Wolf [Fri, 22 Feb 2019 00:16:34 +0000 (01:16 +0100)]
Merge pull request #740 from daveshah1/improve_dress

Improve ABC netname preservation

5 years agoFix Travis
Clifford Wolf [Thu, 21 Feb 2019 22:13:14 +0000 (23:13 +0100)]
Fix Travis

It looks like that whole "Fixing Travis's git clone" code was just
there to make the "git describe --tags" work. I simply removed both.

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoHotfix for 4c82ddf
Clifford Wolf [Thu, 21 Feb 2019 18:27:23 +0000 (19:27 +0100)]
Hotfix for 4c82ddf

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #822 from litghost/expand_setundef
Clifford Wolf [Thu, 21 Feb 2019 18:24:16 +0000 (19:24 +0100)]
Merge pull request #822 from litghost/expand_setundef

Add -params mode to force undef parameters in selected cells.

5 years agoAdd -params mode to force undef parameters in selected cells.
Keith Rothman [Thu, 21 Feb 2019 18:16:38 +0000 (10:16 -0800)]
Add -params mode to force undef parameters in selected cells.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoMerge pull request #818 from YosysHQ/clifford/dffsrfix
Clifford Wolf [Thu, 21 Feb 2019 17:58:44 +0000 (18:58 +0100)]
Merge pull request #818 from YosysHQ/clifford/dffsrfix

Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

5 years agoMerge pull request #786 from YosysHQ/pmgen
Clifford Wolf [Thu, 21 Feb 2019 17:56:01 +0000 (18:56 +0100)]
Merge pull request #786 from YosysHQ/pmgen

Pattern Matcher Generator and iCE40 DSP Mapper

5 years agoFix typo in passes/pmgen/README.md
Clifford Wolf [Thu, 21 Feb 2019 17:50:02 +0000 (18:50 +0100)]
Fix typo in passes/pmgen/README.md

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #821 from eddiehung/dff_init
Clifford Wolf [Thu, 21 Feb 2019 17:46:58 +0000 (18:46 +0100)]
Merge pull request #821 from eddiehung/dff_init

Revert "Add -B option to autotest.sh to append to backend_opts"

5 years agoFixes related to handling of autowires and upto-ranges, fixes #814
Clifford Wolf [Thu, 21 Feb 2019 17:40:11 +0000 (18:40 +0100)]
Fixes related to handling of autowires and upto-ranges, fixes #814

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRevert "Add -B option to autotest.sh to append to backend_opts"
Eddie Hung [Thu, 21 Feb 2019 17:22:29 +0000 (09:22 -0800)]
Revert "Add -B option to autotest.sh to append to backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.

5 years agoFix handling of expression width in $past, fixes #810
Clifford Wolf [Thu, 21 Feb 2019 16:55:33 +0000 (17:55 +0100)]
Fix handling of expression width in $past, fixes #810

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix segfault in printing of some internal error messages
Clifford Wolf [Thu, 21 Feb 2019 16:36:51 +0000 (17:36 +0100)]
Fix segfault in printing of some internal error messages

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
Clifford Wolf [Thu, 21 Feb 2019 14:51:59 +0000 (15:51 +0100)]
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
Clifford Wolf [Thu, 21 Feb 2019 13:27:46 +0000 (14:27 +0100)]
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Clifford Wolf [Thu, 21 Feb 2019 12:48:23 +0000 (13:48 +0100)]
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoBugfix in ice40_dsp
Clifford Wolf [Thu, 21 Feb 2019 12:28:46 +0000 (13:28 +0100)]
Bugfix in ice40_dsp

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #817 from eddiehung/dff_init
Eddie Hung [Thu, 21 Feb 2019 01:26:56 +0000 (17:26 -0800)]
Merge pull request #817 from eddiehung/dff_init

Cleanup #805

5 years agoRemove simple_defparam tests
Eddie Hung [Wed, 20 Feb 2019 23:45:45 +0000 (15:45 -0800)]
Remove simple_defparam tests

5 years agoAdd ice40 test_dsp_map test case generator
Clifford Wolf [Wed, 20 Feb 2019 16:18:59 +0000 (17:18 +0100)]
Add ice40 test_dsp_map test case generator

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "synth_ice40 -dsp"
Clifford Wolf [Wed, 20 Feb 2019 15:42:27 +0000 (16:42 +0100)]
Add "synth_ice40 -dsp"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd FF support to wreduce
Clifford Wolf [Wed, 20 Feb 2019 15:36:42 +0000 (16:36 +0100)]
Add FF support to wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove iCE40 SB_MAC16 model
Clifford Wolf [Wed, 20 Feb 2019 11:55:20 +0000 (12:55 +0100)]
Improve iCE40 SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoDetect and reject cases that do not map well to iCE40 DSPs (yet)
Clifford Wolf [Wed, 20 Feb 2019 10:18:19 +0000 (11:18 +0100)]
Detect and reject cases that do not map well to iCE40 DSPs (yet)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix normal (non-array) hierarchy -auto-top.
Jim Lawson [Tue, 19 Feb 2019 22:35:15 +0000 (14:35 -0800)]
Fix normal (non-array) hierarchy -auto-top.
Add simple test.

5 years agoMerge pull request #805 from eddiehung/dff_init
Eddie Hung [Tue, 19 Feb 2019 20:32:40 +0000 (12:32 -0800)]
Merge pull request #805 from eddiehung/dff_init

write_verilog to write initial statement for initial flop state

5 years agoecp5: Add DDRDLLA
David Shah [Tue, 19 Feb 2019 19:34:37 +0000 (19:34 +0000)]
ecp5: Add DDRDLLA

Signed-off-by: David Shah <davey1576@gmail.com>
5 years agoecp5: Add DELAYF/DELAYG blackboxes
David Shah [Tue, 19 Feb 2019 14:10:43 +0000 (14:10 +0000)]
ecp5: Add DELAYF/DELAYG blackboxes

Signed-off-by: David Shah <davey1576@gmail.com>
5 years agoAdd first draft of functional SB_MAC16 model
Clifford Wolf [Tue, 19 Feb 2019 12:42:21 +0000 (13:42 +0100)]
Add first draft of functional SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoInstead of INIT param on cells, use initial statement with hier ref as
Eddie Hung [Sun, 17 Feb 2019 20:18:12 +0000 (12:18 -0800)]
Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf