r600/llvm: Allow arbitrary amount of temps in tgsi to llvm

freedreno/a3xx: add adreno 330 support

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a3xx/compiler: add ROUND

Signed-off-by: Rob Clark <robclark@freedesktop.org>

mesa: Require per-sample shading if the `sample` qualifier is used.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

glsl: Populate gl_fragment_program::IsSample bitfield

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

mesa: add IsSample bitfield to gl_fragment_program

Drivers will need to look at this to decide if they need to do
per-sample fragment shader dispatch.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

glsl: Put `sample`-qualified varyings in their own packing classes

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

glsl: Add ir support for `sample` qualifier; adjust compiler and linker

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

glsl: Add frontend support for `sample` auxiliary storage qualifier

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Don't flag gather quirks for Gen8+

My understanding is that Broadwell retains the same SCS mechanism
that Haswell has, so even if the underlying issue with this format
is not fixed, the w/a will be applied in SCS rather than needing
shader code.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/Gen7: Allow CMS layout for multisample textures

Now that all the pieces are in place, this should provide
a nice performance boost for apps using multisample textures.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vs: Sample from MCS surface when required

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965/fs: Sample from MCS surface when required

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Add shader opcode for sampling MCS surface

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/Gen7: Include bitfield in the sampler key for CMS layout

We need to emit extra shader code in this case to sample the
MCS surface first; we can't just blindly do this all the time
since IVB will sometimes try to access the MCS surface even if
disabled.

V3: Use actual MSAA layout from the texture's mt, rather
then computing what would have been used based on the format.
This is simpler and less fragile - there's at least one case where
we might want to have a texture's MSAA layout change based on what
the app does (CMS SINT falling back to UMS if the app ever attempts
to render to it with a channel disabled.)

This also obsoletes V2's 1/10 -- compute_msaa_layout can now remain
an implementation detail of the miptree code.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965/Gen7: Move decision to allocate MCS surface into intel_mipmap_create

This gives us correct behavior for both renderbuffers (which previously
worked) and multisample textures (which would never get an MCS surface
allocated, even if CMS layout was selected)

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/Gen7: emit mcs info for multisample textures

Previously this was only done for render targets.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/wm: Set copy of sample mask in 3DSTATE_PS correctly for Haswell

The bspec says:

"SW must program the sample mask value in this field so that it matches
with 3DSTATE_SAMPLE_MASK"

I haven't observed this to actually fix anything, but stumbled across it
while adding the rest of the support for CMS layout for multisample
   textures.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: refactor sample mask calculation

Haswell needs a copy of the sample mask in 3DSTATE_PS; this makes that
convenient.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Don't emit empty declaration warning for a struct specifier

The intention is that things like

   int;

will generate a warning.  However, we were also accidentally emitting
the same warning for things like

  struct Foo { int x; };

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68838
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Aras Pranckevicius <aras@unity3d.com>
Cc: "9.2 10.0" <mesa-stable@lists.freedesktop.org>

st/xa: Bump major version number to 2

For some reason this was left out when the version was changed...

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>

nvc0: fixup gk110 and up not being listed in various switch statements

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

i965: Replace non-standard INLINE macro with "inline".

These are identical: main/compiler.h defines INLINE to "inline".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Don't use GL types in files shared with intel-gpu-tools.

sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
       -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
       -e 's/GLshort/int16_t/g' \
       brw_eu* brw_disasm.c brw_structs.h

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop trailing whitespace from the rest of the driver.

Performed via:
$ for file in *; do sed -i 's/  *//g'; done

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop trailing whitespace from files shared with intel-gpu-tools.

Performed via s/  *$//g.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

tools/trace: More tweaks to state dumping.

- Ignore buffer format (it is totally arbitrary)
- Initialize state.
- Handle begin/end_query statements.

trace: Reorder dumping of pipe_rasterizer_state.

Such that it matches the pipe_rasterizer_state declaration, making it
easier to double-check that all state is being actually dumped.

Trivial.

trace: Dump pipe_sampler_state::seamless_cube_map.

Trivial.

radeonsi: Remove some stale XXX / FIXME comments

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

i965: Emit better code for ir_unop_sign.

total instructions in shared programs: 1550449 -> 1550048 (-0.03%)
instructions in affected programs:     15207 -> 14806 (-2.64%)

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965/fs: New peephole optimization to flatten IF/BREAK/ENDIF.

total instructions in shared programs: 1550713 -> 1550449 (-0.02%)
instructions in affected programs:     7931 -> 7667 (-3.33%)

Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965/fs: Emit a MOV instead of a SEL if the sources are the same.

One program affected.

instructions in affected programs:     436 -> 428 (-1.83%)

Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965/fs: Extend SEL peephole to handle only matching MOVs.

Before this patch, the following code would not be optimized even though
the first two instructions were common to the then and else blocks:

   (+f0) IF
   MOV dst0 ...
   MOV dst1 ...
   MOV dst2 ...
   ELSE
   MOV dst0 ...
   MOV dst1 ...
   MOV dst3 ...
   ENDIF

This commit extends the peephole to handle this case.

No shader-db changes.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: New peephole optimization to generate SEL.

fs_visitor::try_replace_with_sel optimizes only if statements whose
"then" and "else" bodies contain a single MOV instruction. It also
could not handle constant arguments, since they cause an extra MOV
immediate to be generated (since we haven't run constant propagation,
there are more than the single MOV).

This peephole fixes both of these and operates as a normal optimization
pass.

fs_visitor::try_replace_with_sel is still arguably necessary, since it
runs before pull constant loads are lowered.

total instructions in shared programs: 1559129 -> 1545833 (-0.85%)
instructions in affected programs:     167120 -> 153824 (-7.96%)
GAINED:                                13
LOST:                                  6

Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965/fs: Add SEL() convenience function.

Reviewed-by: Paul Berry <stereotype441@gmail.com>

glsl: Use fabs() on floating point values.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Print conditional mod in dump_instruction().

Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Externalize conditional_modifier for use in dump_instruction().

Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Print argument types in dump_instruction().

Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Externalize reg_encoding for use in dump_instruction().

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/vec4: Don't print swizzles for immediate values.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/vec4: Print negate and absolute value for src args.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/vec4: Add support for printing HW_REGs in dump_instruction().

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Print ARF registers properly in dump_instruction().

Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Don't print extra (null) arguments in dump_instruction().

Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Remove silly OR(..., 0x0) from ldexp() lowering.

I translated copysign(0.0f, x) a little too literally.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Allow commuting the operands of ADDC for const propagation.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Rename register_coalesce_2() -> register_coalesce().

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Remove now useless register_coalesce() pass.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Let register_coalesce_2() eliminate self-moves.

This is the last thing that register_coalesce() still handled.

total instructions in shared programs: 1561060 -> 1560908 (-0.01%)
instructions in affected programs:     15758 -> 15606 (-0.96%)

Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Allow constant propagation into ASR and BFI1.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Document cur_* variables.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Remove ip & cur from brw_cfg.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Clean up cfg_t constructors.

parent_mem_ctx was unused since db47074a, so remove the two wrappers
around create() and make create() the constructor.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Throw out confusing make_list method.

make_list is just a one-line wrapper and was confusingly called by
NULL objects. E.g., cur_if == NULL; cur_if->make_list(mem_ctx).

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Include only needed headers.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Remove unnecessary endif_stack.

Unnecessary since last commit.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.

Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.

This should be immaterial to dataflow analysis, except for if, break,
endif sequences:

   START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8)     null            g15<8,8,1>F     g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0                 null            0x00000000UD
   END B1 ->B2 ->B4
   START B2 <-B1
   break
0x00000120: break(8) 0 0                    null            0D
   END B2 ->B10
   START B3
0x00000130: endif(8) 2                      null            0x00000002UD
   END B3 ->B4

The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.

This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.

It helps three programs (including two fs8/fs16 pairs).

total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs:     837 -> 771 (-7.89%)

More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Keep pointers to IF/ELSE/ENDIF instructions in the cfg.

Useful for finding the associated control flow instructions, given a
block ending in one.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/cfg: Add code to dump blocks and cfg.

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Remove GL_MESA_texture_array cruft from gl.h

glext.h has had all the necessary bits for years.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Remove support for GL_MESA_texture_array

This extension enabled the use of texture array with fixed-function and
assembly fragment shaders.  No applications are known to use this
extension.

NOTE: This patch regresses GL_TEXTURE_1D_ARRAY and GL_TEXTURE_2D_ARRAY
cases of the copyteximage piglit test.  The test is incorrectly using
texture arrays with fixed function while only requiring the
GL_EXT_texture_array extension.  A fix for the test has been posted to
the piglit mailing list.

http://lists.freedesktop.org/archives/piglit/2013-November/008639.html

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Use a single enable for GL_EXT_texture_array and GL_MESA_texture_array

Every driver that enables one also enables the other.  The difference
between the two is MESA adds support for fixed-function and assembly
fragment shaders, but EXT only adds support for GLSL.  The MESA
extension was created back when Mesa did not support GLSL.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Minor clean-up of target_enum_to_index

Constify the gl_context parameter, and remove suffixes from enums that
have non-suffix versions.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Silence GCC warning in count_tex_size

main/texobj.c: In function 'count_tex_size':
main/texobj.c:886:23: warning: unused parameter 'key' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Silence GCC warning in _mesa_test_texobj_completeness

main/texobj.c: In function '_mesa_test_texobj_completeness':
main/texobj.c:553:34: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
main/texobj.c:553:193: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
main/texobj.c:553:254: warning: signed and unsigned type in conditional expression [-Wsign-compare]
main/texobj.c:553:148: warning: signed and unsigned type in conditional expression [-Wsign-compare]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add missing API check for GL_TEXTURE_3D

There are no 3D textures in OpenGL ES 1.x.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add missing checks for GL_TEXTURE_CUBE_MAP_ARRAY

That enum requires GL_ARB_texture_cube_map_array, and it is only
available on desktop GL.  It looks like this has been an un-noticed
issue since GL_ARB_texture_cube_map_array support was added in commit
e0e7e295.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

wayland: Add an extension to create wl_buffers from EGLImages

This adds an extension called EGL_WL_create_wayland_buffer_from_image
which adds the following single function:

struct wl_buffer *
eglCreateWaylandBufferFromImageWL(EGLDisplay dpy, EGLImageKHR image);

The function creates a wl_buffer which shares its contents with the given
EGLImage. The expected use case for this is in a nested Wayland compositor
which is using subsurfaces to present buffers from its clients. Using this
extension it can attach the client buffers directly to the subsurface without
having to blit the contents into an intermediate buffer. The compositing can
then be done in the parent compositor.

The extension is only implemented in the Wayland EGL platform because of
course it wouldn't make sense anywhere else.

egl/wayland: Damage INT32_MAX x INT32_MAX region for eglSwapBuffers

If we're not using EGL_EXT_swap_buffers_with_damage, we have to
damage the full extent.  EGL operates on buffer coordinates, but
wl_surface.damage takes surface coordinates.  EGL doesn't know the
buffer transformation (rotated or scaled) and can't post accurate
damage in surface coordinates.  The damage event however is clipped to
the surface extents so we can just damage the maximum rectangle.

In case of EGL_EXT_swap_buffers_with_damage, the application knows
the buffer transform and is expected to pass in rectangles in
surface space.

https://bugs.freedesktop.org/show_bug.cgi?id=70250
Cc: "10.0" mesa-stable@lists.freedesktop.org

Enable throttling in SwapBuffers

flush_with_flags, when available, allows the driver to throttle.
Using this suppress input lag issues that can be observed in heavy
rendering situations on non-intel cards.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Cc: "10.0" mesa-stable@lists.freedesktop.org

egl/wayland: Send commit after flushing the driver context

This typically won't make a difference, since we only send the requests at
wl_display_flush() time.  There might be a small race
with another thread calling wl_display_flush() after our commit request,
but before we flush the DRI driver.  Moving the commit below the DRI
driver flush call looks more natural and eliminates the small race.

Cc: "10.0" mesa-stable@lists.freedesktop.org

egl/wayland: Flush the wl_display at the end of SwapBuffers

We would like the compositor to receive the commited buffer
as soon as possible, so it has the time to treat it, and
release old ones. We shouldn't rely on the client
to flush the queue for us.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Cc: "10.0" mesa-stable@lists.freedesktop.org

mesa: reduce memory used for short display lists

Display lists allocate memory in chunks of 256 tokens (1KB) at a time.
If an app creates many short display lists or uses glXUseXFont() this
can waste quite a bit of memory.

This patch uses realloc() to trim short lists and reduce the memory
used.

Also, null/zero-out some list construction fields in _mesa_EndList().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: update/remove display list comments

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove gl_dlist_node::next pointer to reduce dlist memory use

Now, sizeof(gl_dlist_node)==4 even on 64-bit systems.  This can
halve the memory used by some display lists on 64-bit systems.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: begin reducing memory used by display lists

This is a first step in reducing memory used by display lists on
64-bit systems.  On 64-bit systems, the gl_dlist_node union type
is 8 bytes because of the 'data' and 'next' fields.  This causes
every display list node/token to occupy 8 bytes instead of 4 as
originally designed.  This basically doubles the memory used by
some display lists on 64-bit systems.

The fix is to remove the 64-bit 'data' and 'next' pointer fields
from the union and instead store them as a pair of 32-bit values.
Easily done with a few helper functions.

The next patch will take care of the 'next' field.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nouveau: Add lots of comments to the buffer transfer logic

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: wait on the buf's fence before sticking it into pushbuf

This resolves some rendering issues in source games.
See https://bugs.freedesktop.org/show_bug.cgi?id=64323

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2 10.0" <mesa-stable@lists.freedesktop.org>

nouveau: avoid leaking fences while waiting

This fixes a memory leak in some situations. Also avoids emitting an
extra fence if the kick handler does the call to nouveau_fence_next
itself.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2 10.0" <mesa-stable@lists.freedesktop.org>

nv50: fix a small leak on context destroy

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

docs: put MD5 sums in 9.2.4 relnotes file

Signed-off-by: Brian Paul <brianp@vmware.com>

docs: use --disable-dri3 for VMware guest driver build

For the time being at least.  Suggested by Adrian Rangel.

Signed-off-by: Brian Paul <brianp@vmware.com>

mesa: modified _mesa_align_free() to accept NULL pointer

So that it acts like ordinary free().  This lets us remove a bunch of
if statements where the function is called.

v2:
- Avoiding compile error on MSVC and possible warnings on other compilers.
- Added comment regards passing NULL pointer being safe.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: don't leak performance monitors on context destroy

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

nv50: Fix GPU_READING/WRITING bit removal

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
CC: "9.1, 9.2, 10.0" <mesa-stable@lists.freedesktop.org>

pipe-loader: Fix llvmpipe.la path

Fixes

 make[3]: *** No rule to make target `.../src/gallium/drivers/softpipe/libllvmpipe.la', needed by `pipe_swrast.la'.  Stop.

i965: Fix BRW_BATCH_STRUCT to specify RENDER_RING, not UNKNOWN_RING.

I missed this in the boolean -> enum conversion.  C cheerfully casts
false -> 0 -> UNKNOWN_RING.  On Gen4-5, this causes the render ring
prelude hook to get called in the middle of the batch, which is crazy.

BRW_BATCH_STRUCT is not used on Gen6+.

Fixes regressions since 395a32717df494353703f3581edcd3ba380f16d6
("i965: Introduce an UNKNOWN_RING state.").

Fixes "fips -v glxgears" on Ironlake.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

Revert "i965: Move brw_emit_query_begin() to the render ring prelude."

This reverts commit a4bf7f6b6e612626c4e4fc21507ac213a7ba4b00.
It breaks occlusion queries on Gen4-5.  Doing this right will likely
require larger changes, which should be done at a future date.

Some Piglit tests still passed due to other bugs; fixing those revealed
this problem.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Fix OACONTROL assertion failures on Ironlake.

I guarded half of the callers to start/stop_oa_counters with generation
checks, but missed the other half (which were added later).  OACONTROL
doesn't exist on Ironlake, so we better not write it.  Also, there's no
need---Ironlake's performance counters are always running.

This patch moves the generation checks into start/stop_oa_counters,
rather than requiring the caller to do them.

Fixes assertion failures in Piglit's AMD_performance_monitor/measure.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium/radeon: use PRIu64 macro for printing uint64_t

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

pipe-loader: build llvmpipe on top of softpipe

One can select if they want to fallback to softpipe.
Current approach makes this not possible, whereas other
targets (dri-swrast) handle this approapriately.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: resolve typo DTXn/DXTn

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

automake: include only one copy VERSION in tarball

The VERSION file is tracked by git (git ls-files), thus
adding it to EXTRA_FILES will result in a duplicate copy
within the final tarball.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72230
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reported-by: Patrick Steinhardt <ps@pks.im>
Tested-by: Patrick Steinhardt <ps@pks.im>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

glx: Add missing null check in gxl/dri2_glx.c

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glx: Check malloc return value before accessing memory in glx/clientattrib.c

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965: Add extra-alignment for non-msrt fast color clear for all hw (v2)

The BSpec states that the aligment for the non-msrt clear rectangle must
be doubled; the BSpec does not restricit the workaround to specific
hardware.

Commit 9a1a67b applied the workaround to Haswell GT3.  Commit 8b659ce
expanded the workaround to all Haswell variants. This commit expands it
to all hardware.

No Piglit regressions on Ivybridge 0x0166. No fixes either.

I know no Ivybridge nor Baytrail bug related to this workaround.
However, the BSpec says the extra alignment is required, so let's do it.

v2: Apply to all hardware, not just gen7.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

configure.ac: require libdrm_radeon 2.4.50

st/mesa: implement layered framebuffer clear for the clear_with_quad fallback

Same approach as in u_blitter.