mesa.git
9 years agoi965: Implement SIMD16 texturing on Gen4.
Kenneth Graunke [Fri, 20 Feb 2015 23:11:49 +0000 (15:11 -0800)]
i965: Implement SIMD16 texturing on Gen4.

This allows SIMD16 mode to work for a lot more programs.  Texturing is
also more efficient in SIMD16 mode than SIMD8.  Several messages don't
actually exist in SIMD8 mode, so we did SIMD16 messages and threw away
half of the data.  Now we compute real data in both halves.

Also, the SIMD16 "sample" message doesn't require all three coordinate
components to exist (like the SIMD8 one), so we can shorten the message
lengths, cutting register usage a bit.

I chose to implement the visitor functionality in a separate function,
since mixing true SIMD16 with SIMD8 code that uses SIMD16 fallbacks
seemed like a mess.  The new code bails on a few cases where we'd
have to do two SIMD8 messages - we just fall back to SIMD8 for now.

Improves performance in "Shadowrun: Dragonfall - Director's Cut" by
about 20% on GM45 (measured with LIBGL_SHOW_FPS=1 while standing around
in the first mission).

v2: Add ir_txf to the has_lod case (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agoi965: Use SIMD16 instead of SIMD8 on Gen4 when possible.
Kenneth Graunke [Fri, 20 Feb 2015 22:09:17 +0000 (14:09 -0800)]
i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.

Gen5+ systems allow you to specify multiple shader programs - both SIMD8
and SIMD16 - and the hardware will automatically dispatch to the most
appropriate one, given the number of subspans to be processed.

However, that is not the case on Gen4.  Instead, you program a single
shader.  If you enable multiple dispatch modes (SIMD8 and SIMD16), the
shader is supposed to contain a series of jump instructions at the
beginning.  The hardware will launch the shader at a small offset,
hitting one of the jumps.

We've always thought that sounds like a pain, and weren't clear how it
affected performance - is it worth having multiple shader types?  So,
we never bothered with SIMD16 until now.

This patch takes a simpler approach: try and compile a SIMD16 shader.
If possible, set the no_8 flag, telling the hardware to just use the
SIMD16 variant all the time.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agoi965: Respect the no_8 flag on Gen4-5.
Kenneth Graunke [Sat, 10 Jan 2015 21:31:48 +0000 (13:31 -0800)]
i965: Respect the no_8 flag on Gen4-5.

This flag means to ignore the SIMD8 program and only use the SIMD16 one.
It was originally meant for repdata clear shaders, but I plan to use it
for other things on Gen4 as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agoi965/fp: Set coord_components correctly for cube textures.
Kenneth Graunke [Sat, 4 Apr 2015 01:30:57 +0000 (18:30 -0700)]
i965/fp: Set coord_components correctly for cube textures.

I've no idea why this was 4.  It certainly seems wrong.

Prevents assertion failures in fp-incomplete-tex with some upcoming
patches of mine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agoglsl/cse: Maintain a list of free ae_entry objects
Ian Romanick [Thu, 26 Mar 2015 00:23:40 +0000 (17:23 -0700)]
glsl/cse: Maintain a list of free ae_entry objects

The CSE algorithm will continuously allocate new ae_entry objects.  As
each new basic block is exited, all of the previously allocated objects
are dumped.  Instead, put them in a free list and re-use them in the
next basic block.  Reduce, reuse, recycle!

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
9 years agonir: Remove fsin_reduced/fcos_reduced.
Matt Turner [Thu, 2 Apr 2015 01:25:02 +0000 (18:25 -0700)]
nir: Remove fsin_reduced/fcos_reduced.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agost/mesa: Remove unused emit_scs().
Matt Turner [Thu, 2 Apr 2015 01:23:58 +0000 (18:23 -0700)]
st/mesa: Remove unused emit_scs().

Was only used by the sin_reduced/cos_reduced cases, which themselves
were impossible to reach.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoprogram: Remove unused emit_scs().
Matt Turner [Thu, 2 Apr 2015 01:22:52 +0000 (18:22 -0700)]
program: Remove unused emit_scs().

Was only used by the sin_reduced/cos_reduced cases, which themselves
were impossible to reach.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Remove emit_scs() prototype.
Matt Turner [Thu, 2 Apr 2015 01:21:41 +0000 (18:21 -0700)]
i965/vec4: Remove emit_scs() prototype.

This has never existed.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoglsl: Remove never used sin_reduced/cos_reduced.
Matt Turner [Thu, 2 Apr 2015 00:44:16 +0000 (17:44 -0700)]
glsl: Remove never used sin_reduced/cos_reduced.

These were added in commit f2616e56, presumably in preparation for
translating ARB vp/fp into GLSL IR. That never happened, and neither did
a lowering pass that actually generated these instructions.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoglsl: Update the #line behaviour on GLSL 3.30+ and GLSL ES+
Antia Puentes [Tue, 17 Mar 2015 18:12:23 +0000 (19:12 +0100)]
glsl: Update the #line behaviour on GLSL 3.30+ and GLSL ES+

From GLSL 3.30 and GLSL ES 1.00 on, after processing the line
directive (including its new-line), the implementation should
behave as if it is compiling at the line number passed as
argument. In previous versions, it behaved as if compiling
at the passed line number + 1.

Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoglsl: respect the source number set by #line <line> <source>
Antia Puentes [Tue, 17 Mar 2015 18:28:25 +0000 (19:28 +0100)]
glsl: respect the source number set by #line <line> <source>

From GLSL 1.30.10, section 3.3 (Preprocessor):
"#line line source-string-number ... After processing this directive
(including its new-line), the implementation will behave as if it is
compiling at ... source string number source-string-number. Subsequent
source strings will be numbered sequentially, until another #line
directive overrides that numbering."

In the previous implementation the source number was always zero.
Subsequent source strings are still not numbered sequentially, because
in the glShaderSource implementation we are concatenating the source code
strings into one long string.

Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Make sure we always mark array surfaces as such
Iago Toral Quiroga [Tue, 3 Feb 2015 11:34:29 +0000 (12:34 +0100)]
i965: Make sure we always mark array surfaces as such

Even if they only have one slice, otherwise textureSize() won't
produce correct results for the depth value.

Fixes 10 dEQP tests in this category:
dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray*

Reviewed-by: Mark Janes <mark.a.janes at intel.com>
9 years agofreedreno/ir3: add NIR compiler
Rob Clark [Thu, 12 Mar 2015 21:18:33 +0000 (17:18 -0400)]
freedreno/ir3: add NIR compiler

The NIR compiler frontend is an alternative to the TGSI f/e, producing
the same ir3 IR and using the same backend passes for scheduling, etc.

It is not enabled by default yet, as there are still some regressions.
To enable, use 'FD_MESA_DEBUG=nir'.  It is enough to use with, for
example, xonotic or supertuxkart.

With the NIR f/e, scalarizing and a number of other lowering steps
happen in NIR, so we don't have to do them in ir3.  Which simplifies the
f/e and allows the lowered instructions to pass through other
optimization stages.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a3xx: don't decode srgb on mem2gmem
Ilia Mirkin [Wed, 4 Mar 2015 01:36:39 +0000 (20:36 -0500)]
freedreno/a3xx: don't decode srgb on mem2gmem

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/a3xx: pass sprite coord mode through to program emit
Ilia Mirkin [Sat, 4 Apr 2015 06:53:52 +0000 (02:53 -0400)]
freedreno/a3xx: pass sprite coord mode through to program emit

Use the correct sprite replacement depending on the flip of the coord
mode, using either T or 1-T depending on whether we have an upper-left or
lower-left coordinate origin. This fixes all the point sprite piglits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/a3xx: add UBO support
Ilia Mirkin [Tue, 31 Mar 2015 15:51:00 +0000 (11:51 -0400)]
freedreno/a3xx: add UBO support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/ir3: insert nop between sfu/mem operations
Ilia Mirkin [Sat, 4 Apr 2015 17:37:45 +0000 (13:37 -0400)]
freedreno/ir3: insert nop between sfu/mem operations

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: dirty context when reallocating a bound bo
Ilia Mirkin [Sat, 4 Apr 2015 02:29:44 +0000 (22:29 -0400)]
freedreno: dirty context when reallocating a bound bo

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: keep track of buffer valid ranges
Ilia Mirkin [Fri, 3 Apr 2015 06:15:17 +0000 (02:15 -0400)]
freedreno: keep track of buffer valid ranges

Copies nouveau_buffer and radeon_buffer. This allows a write to proceed
to an uninitialized part of a buffer even when the GPU is using the
previously-initialized portions.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: mark resources as being read so that writes flush the queue
Ilia Mirkin [Fri, 3 Apr 2015 00:48:44 +0000 (20:48 -0400)]
freedreno: mark resources as being read so that writes flush the queue

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: don't bother setting resource timestamps
Ilia Mirkin [Sat, 4 Apr 2015 03:39:38 +0000 (23:39 -0400)]
freedreno: don't bother setting resource timestamps

Waiting on a bo being ready is handled in fd_bo_cpu_prep. No need to
keep separate timestamps around.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: add a reading flag to indicate gpu is reading rsc
Ilia Mirkin [Fri, 3 Apr 2015 06:25:58 +0000 (02:25 -0400)]
freedreno: add a reading flag to indicate gpu is reading rsc

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: fix resource flushing confusion
Ilia Mirkin [Fri, 3 Apr 2015 02:28:21 +0000 (22:28 -0400)]
freedreno: fix resource flushing confusion

A resource flush is an upload of a hypothetically-staging texture to the
GPU. For a UMA system, this will largely be a no-op or
cache-maintenance. Move the render flush logic into transfer_map where
it belongs, and clear out the transfer_flush function.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: remove tex_resource
Ilia Mirkin [Fri, 3 Apr 2015 02:26:03 +0000 (22:26 -0400)]
freedreno: remove tex_resource

pipe_sampler_view already contains a texture, remove the redundant
tex_resource member which pointed at the same thing.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/ir3: handle FRAG IN's without interpolation specified
Rob Clark [Wed, 1 Apr 2015 16:31:46 +0000 (12:31 -0400)]
freedreno/ir3: handle FRAG IN's without interpolation specified

Fallback to picking based on semantic name.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/cmdline: add @const headers for immediates
Rob Clark [Wed, 1 Apr 2015 14:52:29 +0000 (10:52 -0400)]
freedreno/ir3/cmdline: add @const headers for immediates

Since NIR f/e currently encodes immediates in instructions (rather than
passing via const), we need to ensure that when const's are used the get
initialized to the proper values.  Otherwise comparing NIR to TGSI
compiler, it will use proper immediate values in one case, and randomly
initialize values in the other.  Which confuses ir3test.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3/cmdline: remove hack for old compiler
Rob Clark [Wed, 1 Apr 2015 14:28:58 +0000 (10:28 -0400)]
freedreno/ir3/cmdline: remove hack for old compiler

Since we dropped the old compiler, we don't need this hack anymore.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3: handle const/immed/abs/neg in cp
Rob Clark [Sun, 29 Mar 2015 15:24:57 +0000 (11:24 -0400)]
freedreno/ir3: handle const/immed/abs/neg in cp

Be smarter about propagating copies from const or immed, or with abs/neg
modifiers.  Also, realize that absneg.s and absneg.f are really "fancy"
mov instructions.

This opens up the possibility to remove more copies.  It helps the TGSI
frontend a bit, but will be really needed for the NIR f/e which builds
everything up in SSA form (ie. will *always* insert a mov from const or
immediate).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3: split float/int abs/neg
Rob Clark [Sun, 29 Mar 2015 15:18:29 +0000 (11:18 -0400)]
freedreno/ir3: split float/int abs/neg

Even though in the end, they map to the same bits, the backend will need
to be able to differentiate float abs/neg vs integer abs/neg.  Rather
than making the backend figure it out based on instruction opcode (which
when combined with mov/absneg instructions, can be awkward), just split
out different flags for each so the frontend can signal it's intentions
more clearly.  Also, since (neg) for bitwise op's is actually a bitwise-
not, split it out into bnot flag.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3: add ir3 builder helpers
Rob Clark [Wed, 18 Mar 2015 23:26:13 +0000 (19:26 -0400)]
freedreno/ir3: add ir3 builder helpers

Add helpers for constructing SSA forms of instructions.

Only partial cat5/cat6 coverage.. but we can add stuff as needed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/ir3: fix sam argument order comment
Rob Clark [Mon, 30 Mar 2015 18:14:31 +0000 (14:14 -0400)]
freedreno/ir3: fix sam argument order comment

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agoxa: support for drivers which use NIR
Rob Clark [Fri, 3 Apr 2015 18:01:47 +0000 (14:01 -0400)]
xa: support for drivers which use NIR

We need to pull in libnir.la and it's dependency libglsl_util.la.  Also,
_mesa_error_no_memory() must be defined.

Fortunately with libnir.la (vs pulling in all of libglsl.la) we don't
also need libstdc++.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agobuild: add libnir.la
Rob Clark [Fri, 3 Apr 2015 17:57:46 +0000 (13:57 -0400)]
build: add libnir.la

If we want to use NIR from state trackers that don't already pull in the
whole of glsl (ie. anything other than mesa state tracker), we need a
separate more minimal libnir.  Possibly NIR should be better split out
from glsl, but for now, generate a second smaller libnir.la for those
who just want NIR but not all of glsl.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agogallium/ttn: MOD is an integer instruction
Rob Clark [Sat, 4 Apr 2015 22:15:24 +0000 (18:15 -0400)]
gallium/ttn: MOD is an integer instruction

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net
9 years agogallium/ttn: add UMAD
Rob Clark [Sat, 4 Apr 2015 22:15:00 +0000 (18:15 -0400)]
gallium/ttn: add UMAD

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: add lowering for idiv/udiv/umod
Rob Clark [Tue, 31 Mar 2015 21:03:39 +0000 (17:03 -0400)]
nir: add lowering for idiv/udiv/umod

Based on the algo from NV50LegalizeSSA::handleDIV() and handleMOD().
See also trans_idiv() in freedreno/ir3/ir3_compiler.c (which was an
adaptation of the nv50 code from Ilia Mirkin).

A python/numpy script which implements the same algorithm (and is
possibly useful for debugging or analysis) can be found here:

  http://people.freedesktop.org/~robclark/div-lowering.py

I've tested this on i965 hacked up to insert the idiv lowering pass,
and on freedreno with NIR frontend.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Eric Anholt <eric@anholt.net> (vc4)
9 years agonir: fix typo for f2b/i2b/b2i expressions (v2)
Rob Clark [Tue, 31 Mar 2015 19:13:00 +0000 (15:13 -0400)]
nir: fix typo for f2b/i2b/b2i expressions (v2)

v2: discovered that i2b/b2i are also confused

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agonir: add option to lower slt/sge/seq/sne
Rob Clark [Tue, 31 Mar 2015 15:25:19 +0000 (11:25 -0400)]
nir: add option to lower slt/sge/seq/sne

In freedreno these get implemented as the matching f* instruction plus a
u2f to convert the result to float 1.0/0.0.  But less lines of code to
just let nir_opt_algebraic handle this for us, plus opens up some small
window for other opt passes to improve (ie. if some shader ended up with
both a flt and slt with same src args, for example).

v2: use b2f rather than u2f

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agomesa: Remove unused variables left over from 107ae27e57d.
Mathias Froehlich [Sun, 5 Apr 2015 07:21:51 +0000 (09:21 +0200)]
mesa: Remove unused variables left over from 107ae27e57d.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
9 years agoi965: Implement support for ARB_clip_control.
Mathias Fröhlich [Sun, 29 Mar 2015 14:52:57 +0000 (16:52 +0200)]
i965: Implement support for ARB_clip_control.

Switch between the two clip space definitions already available
in hardware. Update winding order dependent state according
to the clip control state.
This change did not introduce new piglit quick.test regressions on
an Ivybridge Mobile and a GM45 Express chipset.
Also it enables and passes the clip-control and clip-control-depth-precision
tests on these two chipsets.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
9 years agomesa: Remove the _WindowMap from gl_viewport_attrib.
Mathias Froehlich [Sun, 29 Mar 2015 16:57:46 +0000 (18:57 +0200)]
mesa: Remove the _WindowMap from gl_viewport_attrib.

The _WindowMap can be dropped from gl_viewport_attrib now.
Simplify gl_viewport_attrib handling where possible.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
9 years agotnl: Maintain the _WindowMap matrix in TNLcontext v2.
Mathias Froehlich [Sun, 29 Mar 2015 16:57:45 +0000 (18:57 +0200)]
tnl: Maintain the _WindowMap matrix in TNLcontext v2.

This is the only real user of _WindowMap which has the depth
buffer scaling multiplied in. Maintain the _WindowMap of the
one and only viewport inside TNLcontext.

v2:
Remove unneeded parentheses.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
9 years agoradeon: Make use of _mesa_get_viewport_xform v2.
Mathias Froehlich [Sun, 29 Mar 2015 16:57:45 +0000 (18:57 +0200)]
radeon: Make use of _mesa_get_viewport_xform v2.

Instead of _WindowMap just use the translation and scale
of the viewport transform directly. Thereby avoid dividing by
_DepthMaxF again.

v2:
Change order of assignments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
9 years agoi965: Make use of _mesa_get_viewport_xform.
Mathias Froehlich [Sun, 29 Mar 2015 16:57:45 +0000 (18:57 +0200)]
i965: Make use of _mesa_get_viewport_xform.

Instead of _WindowMap just use the translation and scale
of the viewport transform directly. Thereby avoid dividing by
_DepthMaxF again.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
9 years agonv50: allocate more offset space for occlusion queries
Ilia Mirkin [Sat, 4 Apr 2015 03:57:43 +0000 (23:57 -0400)]
nv50: allocate more offset space for occlusion queries

Commit 1a170980a09 started writing to q->data[4]/[5] but kept the
per-query space at 16, which meant that in some cases we would write
past the end of the buffer. Rotate by 32, like nvc0 does. This ensures
that we always have 32 bytes in front of us, and the data writes will go
within the allocated space.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89679
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Nick Tenney <nick.tenney@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
9 years agonir/lower_samplers: Use the right memory context for realloc'ing tex sources
Jason Ekstrand [Fri, 3 Apr 2015 22:23:20 +0000 (15:23 -0700)]
nir/lower_samplers: Use the right memory context for realloc'ing tex sources

As of da5ec2a, we allocate instruction sources out of the instruction
itself.  When we realloc the texture sources we need to use the right
memory context or ralloc will get angry and assert-fail

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Use brw_nir_cubemap_normalize for NIR shaders
Jason Ekstrand [Fri, 3 Apr 2015 00:04:28 +0000 (17:04 -0700)]
i965: Use brw_nir_cubemap_normalize for NIR shaders

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agonir: Add a cubemap normalizing pass
Jason Ekstrand [Thu, 2 Apr 2015 23:38:30 +0000 (16:38 -0700)]
nir: Add a cubemap normalizing pass

This commit adds a pass to L1-normalize cube-map coordinates.  Some hardware
such as i965 requires that largest cube-map coordinate is +-1.  We had a
pass to perform this normalization in GLSL IR but we need it in NIR for
cube maps on ARB programs to work correctly.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
v2 (Suggested by Eric):
 - Do a vector fabs and split into components later
 - Move to core NIR

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoi965: Check the INTEL_USE_NIR environment variable once at context creation
Jason Ekstrand [Fri, 3 Apr 2015 00:02:43 +0000 (17:02 -0700)]
i965: Check the INTEL_USE_NIR environment variable once at context creation

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agonir/from_ssa: Don't set reg->parent_instr for ssa_undef instructions
Jason Ekstrand [Thu, 2 Apr 2015 19:32:39 +0000 (12:32 -0700)]
nir/from_ssa: Don't set reg->parent_instr for ssa_undef instructions

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agonir: Add a src_get_parent_instr function
Jason Ekstrand [Thu, 2 Apr 2015 18:07:48 +0000 (11:07 -0700)]
nir: Add a src_get_parent_instr function

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agoi965: Use the tex projector lowering pass instead of hand-rolling it.
Eric Anholt [Wed, 1 Apr 2015 18:38:53 +0000 (11:38 -0700)]
i965: Use the tex projector lowering pass instead of hand-rolling it.

This only impacts the ARB_fp path.  We can't quite disable the GLSL-level
lowering pass, because it needs to apply before
brw_do_lower_unnormalized_offset().

total instructions in shared programs: 5667857 -> 5667847 (-0.00%)
instructions in affected programs:     1114 -> 1104 (-0.90%)
helped:                                16
HURT:                                  6

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Add a lowering pass for texture projectors.
Eric Anholt [Fri, 27 Mar 2015 21:18:11 +0000 (14:18 -0700)]
nir: Add a lowering pass for texture projectors.

Not much hardware wants them these days, and it might give us a chance to
do CSE or algebraic at the NIR level.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Add an interface to turn a nir_src into a nir_ssa_def.
Eric Anholt [Fri, 27 Mar 2015 21:19:46 +0000 (14:19 -0700)]
nir: Add an interface to turn a nir_src into a nir_ssa_def.

We use nir_ssa_defs for nir_builder args, so this takes a nir_src and
makes one so it can be passed in.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Add an interface for the builder to insert instructions before.
Eric Anholt [Fri, 27 Mar 2015 21:18:54 +0000 (14:18 -0700)]
nir: Add an interface for the builder to insert instructions before.

So far we'd only used nir_builder to build brand new programs.  But if
we're doing modifications to instructions (like in a lowering pass), then
we want to generate new stuff before the instruction we're modifying.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agogallium: fix gcc compile errors when using _XOPEN_SOURCE=600 but not std=c99
Jose Fonseca [Thu, 2 Apr 2015 15:35:16 +0000 (17:35 +0200)]
gallium: fix gcc compile errors when using _XOPEN_SOURCE=600 but not std=c99

The fpclassify stuff either needs std=c99 or _XOPEN_SOURCE=600 passed
to gcc, but when using the latter the lrint family of function will be defined
too.

9 years agoi965: Rename do_<stage>_prog to brw_compile_<stage>_prog (and export)
Carl Worth [Fri, 20 Mar 2015 19:10:49 +0000 (12:10 -0700)]
i965: Rename do_<stage>_prog to brw_compile_<stage>_prog (and export)

This is in preparation for these functions to be called from other
files.

This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Split out per-stage dirty-bit checking into separate functions
Carl Worth [Fri, 20 Mar 2015 19:01:33 +0000 (12:01 -0700)]
i965: Split out per-stage dirty-bit checking into separate functions

The dirty-bit checking from each brw_upload_<stage>_prog function is
split out into its a new brw_<stage>_state_dirty function.

This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Split out brw_<stage>_populate_key into their own functions
Carl Worth [Mon, 23 Feb 2015 22:44:39 +0000 (14:44 -0800)]
i965: Split out brw_<stage>_populate_key into their own functions

This commit splits portions of the existing brw_upload_vs_prog and
brw_upload_gs_prog function into new brw_vs_populate_key and
brw_gs_populate_key functions. This follows the same style as is
already present for all other stages, (see brw_wm_populate_key, etc.).

This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agonv50/ir: avoid folding immediates into imad operations
Ilia Mirkin [Thu, 2 Apr 2015 22:42:31 +0000 (18:42 -0400)]
nv50/ir: avoid folding immediates into imad operations

Commit 09ee907266 added logic to fold immediates into mad operations,
but the emission code is only there for fmad. Only allow it on float
types.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonv50/ir: fix imad emission when dst == src2
Ilia Mirkin [Thu, 2 Apr 2015 22:33:55 +0000 (18:33 -0400)]
nv50/ir: fix imad emission when dst == src2

Commit fb63df22151f added 4-byte mad support, but only supported
emission for floats. Disable it for ints for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonir: Allocate nir_tex_instr::sources out of the instruction itself.
Kenneth Graunke [Sat, 28 Mar 2015 07:02:37 +0000 (00:02 -0700)]
nir: Allocate nir_tex_instr::sources out of the instruction itself.

The lifetime of the sources array needs to be match the nir_tex_instr
itself.  So, allocate it using the instruction itself as the context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Allocate predecessor and dominance frontier sets from block itself.
Kenneth Graunke [Sat, 28 Mar 2015 04:29:07 +0000 (21:29 -0700)]
nir: Allocate predecessor and dominance frontier sets from block itself.

These sets are part of the block, and their lifetime needs to match the
block itself.  So, allocate them using the block itself as the context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Allocate register fields out of the register itself.
Kenneth Graunke [Sat, 28 Mar 2015 03:21:59 +0000 (20:21 -0700)]
nir: Allocate register fields out of the register itself.

The lifetime of each register's use/def/if_use sets needs to match the
register itself.  So, allocate them using the register itself as the
context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Make nir_create_function() strdup the function name.
Kenneth Graunke [Sat, 28 Mar 2015 02:23:36 +0000 (19:23 -0700)]
nir: Make nir_create_function() strdup the function name.

glsl_to_nir passes in the ir_function's name field; we were copying the
pointer, but not duplicating the memory.

We want to be able to free the linked GLSL IR program after translating
to NIR, so we'll need to create a copy of the function name that the NIR
shader actually owns.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Free dead variables when removing them.
Kenneth Graunke [Fri, 27 Mar 2015 23:19:27 +0000 (16:19 -0700)]
nir: Free dead variables when removing them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Combine remove_dead_local_vars() and remove_dead_global_vars().
Kenneth Graunke [Fri, 27 Mar 2015 23:17:20 +0000 (16:17 -0700)]
nir: Combine remove_dead_local_vars() and remove_dead_global_vars().

We can just pass a pointer to the list of variables, and reuse the code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoralloc: Implement a new ralloc_adopt() API.
Kenneth Graunke [Sat, 28 Mar 2015 02:24:33 +0000 (19:24 -0700)]
ralloc: Implement a new ralloc_adopt() API.

ralloc_adopt() reparents all children from one context to another.
Conceptually, ralloc_adopt(new_ctx, old_ctx) behaves like this
pseudocode:

   foreach child of old_ctx:
      ralloc_steal(new_ctx, child)

However, ralloc provides no way to iterate over a memory context's
children, and ralloc_adopt does this task more efficiently anyway.

One potential use of this is to implement a memory-sweeper pass: first,
steal all of a context's memory to a temporary context.  Then, walk over
anything that should be kept, and ralloc_steal it back to the original
context.  Finally, free the temporary context.  This works when the
context is something that can't be freed (i.e. an important structure).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir/opt_peephole_ffma: Fix a couple typos in a comment
Jason Ekstrand [Thu, 2 Apr 2015 17:42:12 +0000 (10:42 -0700)]
nir/opt_peephole_ffma: Fix a couple typos in a comment

Acked-by: Matt Turner <mattst88@gmail.com>
9 years agomesa: add ARB_depth_buffer_float to ES3.0 required extension list
Ilia Mirkin [Wed, 1 Apr 2015 20:19:09 +0000 (16:19 -0400)]
mesa: add ARB_depth_buffer_float to ES3.0 required extension list

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agovc4: Add support for nir_iabs.
Eric Anholt [Wed, 1 Apr 2015 22:19:38 +0000 (15:19 -0700)]
vc4: Add support for nir_iabs.

Tested using the GLSL 1.30 tests for integer abs().  Not currently used,
but it was one of the new opcodes used by robclark's idiv lowering.

9 years agoi965/generator: Get rid of the ! in the unreachable statement
Jason Ekstrand [Wed, 1 Apr 2015 23:18:31 +0000 (16:18 -0700)]
i965/generator: Get rid of the ! in the unreachable statement

Reviewed-by: Mark Janes <mark.a.janes@intel.com>
9 years agonir/print: Correctly print swizzles for explicitly sized alu sources
Jason Ekstrand [Wed, 1 Apr 2015 23:16:52 +0000 (16:16 -0700)]
nir/print: Correctly print swizzles for explicitly sized alu sources

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agofreedreno/a3xx: add MRT support
Ilia Mirkin [Sun, 15 Feb 2015 08:39:43 +0000 (03:39 -0500)]
freedreno/a3xx: add MRT support

The hardware only supports 4 MRTs. It should be possible to emulate
support for 8, but doesn't seem worth the trouble.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: convert blit program to array for each number of rts
Ilia Mirkin [Wed, 1 Apr 2015 05:14:39 +0000 (01:14 -0400)]
freedreno: convert blit program to array for each number of rts

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: add support for laying out MRTs in gmem
Ilia Mirkin [Mon, 30 Mar 2015 00:54:42 +0000 (20:54 -0400)]
freedreno: add support for laying out MRTs in gmem

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: add core infrastructure support for MRTs
Ilia Mirkin [Mon, 30 Mar 2015 00:39:48 +0000 (20:39 -0400)]
freedreno: add core infrastructure support for MRTs

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/ir3: add support for FS_COLOR0_WRITES_ALL_CBUFS property
Ilia Mirkin [Mon, 30 Mar 2015 00:24:57 +0000 (20:24 -0400)]
freedreno/ir3: add support for FS_COLOR0_WRITES_ALL_CBUFS property

This will enable the driver to tell which regids to link up to which
MRT outputs.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno/a3xx: add independent blend function support
Ilia Mirkin [Mon, 30 Mar 2015 00:04:38 +0000 (20:04 -0400)]
freedreno/a3xx: add independent blend function support

This is needed for MRT support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agofreedreno: remove alpha key from ir3_shader
Ilia Mirkin [Sun, 29 Mar 2015 23:59:38 +0000 (19:59 -0400)]
freedreno: remove alpha key from ir3_shader

This complication is unnecessary and makes MRTs more complicated and
likely to generate tons of variants.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agoi915g: Implement EGL_EXT_image_dma_buf_import
Stéphane Marchesin [Thu, 2 Apr 2015 03:00:08 +0000 (20:00 -0700)]
i915g: Implement EGL_EXT_image_dma_buf_import

This adds all the plumbing to get EGL_EXT_image_dma_buf_import in
i915g.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
9 years agoi965/fs: Relax type check in cmod propagation.
Matt Turner [Thu, 26 Mar 2015 17:09:54 +0000 (10:09 -0700)]
i965/fs: Relax type check in cmod propagation.

The thing we want to avoid is int/float comparisons, but int/unsigned
comparisons with 0 are equivalent.

total instructions in shared programs: 6194829 -> 6193996 (-0.01%)
instructions in affected programs:     117192 -> 116359 (-0.71%)
helped:                                471

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Remove useless ftrunc inside f2i/f2u.
Matt Turner [Thu, 26 Mar 2015 17:09:42 +0000 (10:09 -0700)]
nir: Remove useless ftrunc inside f2i/f2u.

No shader-db changes, probably because they're all removed by the GLSL
compiler optimization added in commit 69ad5fd4.

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Recognize (a < b || a < c) as a < max(b, c).
Matt Turner [Thu, 26 Mar 2015 17:09:21 +0000 (10:09 -0700)]
nir: Recognize (a < b || a < c) as a < max(b, c).

Doesn't work for analogous && cases, because of NaNs.

total instructions in shared programs: 6195712 -> 6194829 (-0.01%)
instructions in affected programs:     42000 -> 41117 (-2.10%)
helped:                                403

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Add addition/multiplication identities of exp/log.
Matt Turner [Thu, 26 Mar 2015 18:08:01 +0000 (11:08 -0700)]
nir: Add addition/multiplication identities of exp/log.

instructions in affected programs:     2858 -> 2808 (-1.75%)
helped:                                12

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Add identities for the log function.
Matt Turner [Thu, 26 Mar 2015 17:07:58 +0000 (10:07 -0700)]
nir: Add identities for the log function.

The rcp(log(x)) pattern affects instruction counts.

instructions in affected programs:     144 -> 138 (-4.17%)
helped:                                6

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Add identities for the exponential function.
Matt Turner [Thu, 26 Mar 2015 17:16:24 +0000 (10:16 -0700)]
nir: Add identities for the exponential function.

No changes in shader-db.

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Recognize another open coded lrp.
Matt Turner [Thu, 26 Mar 2015 17:36:42 +0000 (10:36 -0700)]
nir: Recognize another open coded lrp.

total instructions in shared programs: 6195924 -> 6195768 (-0.00%)
instructions in affected programs:     4876 -> 4720 (-3.20%)
helped:                                58
HURT:                                  10

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Recognize open coded lrp.
Matt Turner [Wed, 25 Mar 2015 22:03:52 +0000 (15:03 -0700)]
nir: Recognize open coded lrp.

total instructions in shared programs: 6197614 -> 6195924 (-0.03%)
instructions in affected programs:     34773 -> 33083 (-4.86%)
helped:                                147
HURT:                                  6

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Use _mesa_flsll(InputsRead) in prog->nir.
Kenneth Graunke [Mon, 30 Mar 2015 23:09:51 +0000 (16:09 -0700)]
nir: Use _mesa_flsll(InputsRead) in prog->nir.

InputsRead is a 64-bit bitfield.  Using _mesa_fls would silently
truncate off the high bits, claiming inputs 32..56 (VARYING_SLOT_MAX)
were never read.

Using <= here was a hack I threw in at the last minute to fix programs
which happened to use input slot 32.  Switch back to using < now that
the underlying problem is fixed.

Fixes crashes in "Euro Truck Simulator 2" when using prog->nir, which
uses input slot 33.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agomesa: Implement _mesa_flsll().
Kenneth Graunke [Mon, 30 Mar 2015 23:08:26 +0000 (16:08 -0700)]
mesa: Implement _mesa_flsll().

This is _mesa_fls() for 64-bit values.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: In prog->nir, don't wrap dot products with ptn_channel(..., X).
Kenneth Graunke [Mon, 30 Mar 2015 12:17:56 +0000 (05:17 -0700)]
nir: In prog->nir, don't wrap dot products with ptn_channel(..., X).

ptn_move_dest and nir_fadd already take care of replicating the last
channel out, so we can just use a scalar and skip splatting it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoi965: Use the same nir options for all gens
Jason Ekstrand [Mon, 23 Mar 2015 22:58:34 +0000 (15:58 -0700)]
i965: Use the same nir options for all gens

If we tell NIR to split ffma's, then we don't need seperate options
anymore.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/nir: Run DCE again before going out of SSA
Jason Ekstrand [Wed, 1 Apr 2015 19:37:43 +0000 (12:37 -0700)]
i965/nir: Run DCE again before going out of SSA

We run lowering and optimization passes that might leave garbage lying
around. This keeps the FS cse from having to clean it up.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/nir: Run the ffma peephole after the rest of the optimizations
Jason Ekstrand [Mon, 23 Mar 2015 22:08:31 +0000 (15:08 -0700)]
i965/nir: Run the ffma peephole after the rest of the optimizations

The idea here is that fusing multiply-add combinations too early can reduce
our ability to perform CSE and value-numbering.  Instead, we split ffma
opcodes up-front, hope CSE cleans up, and then fuse after-the-fact.
Unless an algebraic pass does something silly where it inserts something
between the multiply and the add, splitting and re-fusing should never
cause a problem.  We run the late algebraic optimizations after this so
that things like compare-with-zero don't hurt our ability to fuse things.

shader-db results for fragment shaders on Haswell:
total instructions in shared programs: 4390538 -> 4379236 (-0.26%)
instructions in affected programs:     989359 -> 978057 (-1.14%)
helped:                                5308
HURT:                                  97
GAINED:                                78
LOST:                                  5

This does, unfortunately, cause some substantial hurt to a shader in Kerbal
Space Program.  However, the damage is caused by changing a single
instruction from a ffma to an add.  This, in turn, *decreases* register
pressure in one part of the program causing it to fail to register allocate
and spill.  Given the overwhelmingly positive results in other shaders and
the fact that the NIR for the Kerbal shaders is actually better, this
should be considered a positive.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir/peephole_ffma: Be less agressive about fusing multiply-adds
Jason Ekstrand [Mon, 23 Mar 2015 21:55:20 +0000 (14:55 -0700)]
nir/peephole_ffma: Be less agressive about fusing multiply-adds

shader-db results for fragment shaders on Haswell:
total instructions in shared programs: 4395688 -> 4389623 (-0.14%)
instructions in affected programs:     355876 -> 349811 (-1.70%)
helped:                                1455
HURT:                                  14
GAINED:                                5
LOST:                                  0

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: Add a dedicated ffma peephole optimization
Jason Ekstrand [Sat, 21 Mar 2015 19:21:21 +0000 (12:21 -0700)]
nir: Add a dedicated ffma peephole optimization

i965/nir: Use the dedicated ffma peephole

total instructions in shared programs: 4418748 -> 4394618 (-0.55%)
instructions in affected programs:     1292790 -> 1268660 (-1.87%)
helped:                                5999
HURT:                                  457
GAINED:                                4
LOST:                                  9

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir: Move the compare-with-zero optimizations to the late section
Jason Ekstrand [Tue, 24 Mar 2015 00:36:22 +0000 (17:36 -0700)]
nir: Move the compare-with-zero optimizations to the late section

total instructions in shared programs: 4422307 -> 4422363 (0.00%)
instructions in affected programs:     4230 -> 4286 (1.32%)
helped:                                0
HURT:                                  12

While this does hurt some things, the losses are minor and it prevents the
compare-with-zero optimization from fighting with ffma which is much more
important.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonir/algebraic: Add a seperate section for "late" optimizations
Jason Ekstrand [Tue, 24 Mar 2015 00:11:49 +0000 (17:11 -0700)]
nir/algebraic: Add a seperate section for "late" optimizations

i965/nir: Use the late optimizations

Reviewed-by: Matt Turner <mattst88@gmail.com>