Marek Olšák [Thu, 13 Aug 2020 19:14:19 +0000 (15:14 -0400)]
nir: add interpolation qualifiers for color sysvals into shader_info
needed by radeonsi
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
Marek Olšák [Fri, 14 Aug 2020 23:13:52 +0000 (19:13 -0400)]
nir: add shader_info::io_lowered
This will drive decisions in many NIR passes and st/mesa.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
Marek Olšák [Fri, 14 Aug 2020 05:54:19 +0000 (01:54 -0400)]
nir: properly identify texcoords for lowered IO in nir_lower_drawpixels
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
Marek Olšák [Fri, 14 Aug 2020 23:34:27 +0000 (19:34 -0400)]
nir: print IO semantics (v2)
v2: print GS streams readably
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
Marek Olšák [Fri, 14 Aug 2020 23:33:50 +0000 (19:33 -0400)]
nir: update IO semantics in nir_io_add_const_offset_to_base
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
Marek Olšák [Fri, 14 Aug 2020 23:31:46 +0000 (19:31 -0400)]
nir: gather all IO info from IO intrinsics
nir_io_add_const_offset_to_base will shrink num_slots, so it's better to
call it before nir_shader_gather_info.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
Marek Olšák [Wed, 12 Aug 2020 03:48:12 +0000 (23:48 -0400)]
nir: save IO semantics in lowered IO intrinsics
This enables drivers and utils to get all IO information from intrinsics,
so that they don't have to walk the complex types of NIR variables to find
out other information about IO intrinsics.
NIR in/out variables can be removed after nir_lower_io. We could remove
the variables in the pass, but for now I just decided to remove
the variables in radeonsi before shaders are returned to st/mesa.
(st/mesa just needs adjustments to work without NIR in/out variables)
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
Lionel Landwerlin [Mon, 24 Aug 2020 10:52:59 +0000 (13:52 +0300)]
intel/perf: fix raw query kernel metric selection
The raw query is meant to be used with MDAPI [1]. When using this
metric without this library, we usually selected the TestOa metric to
provide some default sensible values (instead of undefined).
Historically this TestOa metric lived in the kernel at ID=1. We
removed all metrics from the kernel in kernel commit
9aba9c188da136
("drm/i915/perf: remove generated code").
This fixes the Mesa code to use a valid metric set ID (1 could work
some of the time, but not guaranteed).
[1] : https://github.com/intel/metrics-discovery
v2: Store fallback metric at init time
v3: Drop TestOa lookout
v4: Skip the existing queries (Marcin)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
CC: <mesa-stable@lists.freedesktop.org>
Tested-by: Marcin Ślusarz <marcin.slusarz@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6438>
Lionel Landwerlin [Mon, 24 Aug 2020 13:42:42 +0000 (16:42 +0300)]
intel/perf: store query symbol name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6438>
Eric Anholt [Fri, 21 Aug 2020 20:37:07 +0000 (13:37 -0700)]
nir/load_store_vectorizer: Clean up unit test swizzle assertions.
They're hard to write and read, so put together a little helper to clean
up both the code and the gtest output on failure.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6431>
Eric Anholt [Tue, 18 Aug 2020 22:45:02 +0000 (15:45 -0700)]
freedreno/ir3: Replace our custom vec4 UBO intrinsic with the shared lowering.
This gets us fewer comparisons in the shaders that we need to optimize
back out, and reduces backend code.
total instructions in shared programs:
11547270 ->
7219930 (-37.48%)
total full in shared programs: 334268 -> 319602 (-4.39%)
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
Eric Anholt [Tue, 18 Aug 2020 18:38:41 +0000 (11:38 -0700)]
nir: Add a lowering pass for backends wanting load_ubo with vec4 offsets.
This is very common for backends -- r600, freedreno, and nir_to_tgsi all
needed versions of it. Make a common intrinsic to use for it with a
shared, slightly-tuned-from-ir3 lowering pass.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
Eric Anholt [Fri, 21 Aug 2020 18:21:33 +0000 (11:21 -0700)]
nir: Add nir_[iu]shr_imm and nir_udiv_imm helpers and use them.
I was doing math manually in a lowering pass for converting a division to
a ushr, and this will let the pass be expressed more naturally.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
Eric Anholt [Fri, 21 Aug 2020 18:15:24 +0000 (11:15 -0700)]
nir: Make the nir_builder *_imm helpers consistently handle bit size.
We always want to demote the y to the bit size of the ssa def, but also
want to sanity check that our input and our masking is big enough.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
Timur Kristóf [Sat, 22 Aug 2020 18:45:54 +0000 (20:45 +0200)]
aco: Fix convert_to_SDWA when instruction has 3 operands.
Previously, when the instruction had 3 operands, this would cause
possible corruption because of writing to sdwa->sel[2].
This was noticed thanks to GCC 10's -Wstringop-overflow warning.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6436>
Timur Kristóf [Sat, 22 Aug 2020 18:41:45 +0000 (20:41 +0200)]
aco: Fix unused variable warning by adding ASSERTED.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6436>
Alyssa Rosenzweig [Thu, 20 Aug 2020 15:45:53 +0000 (11:45 -0400)]
r300: Use util_blend_factor_uses_dest
v2: Fix missing { and #include (trivial)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Marek Olšák <marek.olsak@amd.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
Alyssa Rosenzweig [Thu, 20 Aug 2020 15:35:39 +0000 (11:35 -0400)]
si: Use util_blend_factor_uses_dest
Driver-local copy is redundant.
v2: Fix missing #include (trivial)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Marek Olšák <marek.olsak@amd.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
Alyssa Rosenzweig [Thu, 20 Aug 2020 15:45:38 +0000 (11:45 -0400)]
gallium: Add util_blend_uses_dest helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
Alyssa Rosenzweig [Tue, 18 Aug 2020 21:28:38 +0000 (17:28 -0400)]
gallium: Add util_blend_factor_uses_dest helper
Drivers may be able to optimize cases where blending is enabled but the
destination colour is not used. This helps detect that case.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
Samuel Pitoiset [Tue, 18 Aug 2020 16:52:35 +0000 (18:52 +0200)]
radv: use the trap handler to detect faulty shaders/instructions
It should reliably report the faulty shader but the faulty instruction
is inacurate, especially for memory violations because it's reported
when the addr is processed. It will be improved by emitting more
wait-states.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Tue, 18 Aug 2020 06:49:11 +0000 (08:49 +0200)]
radv: enable the trap handler and configure the shader exceptions
When TRAP_PRESENT is not enabled, all traps and exceptions are ignored.
Only EXCP_EN.mem_viol is currently supported because the other
exceptions have to be tested/validated first.
EXCP_EN.mem_viol is used to detect any sort of invalid memory
access like VM fault. When a memory violation is reported, the
hw jumps to the trap handler.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Tue, 18 Aug 2020 16:51:46 +0000 (18:51 +0200)]
radv: add initial trap handler support with RADV_TRAP_HANDLER=1
A trap handler is used to handle shader exceptions like memory
violations, divide by zero etc. The trap handler shader code will
help to identify the faulty shader/instruction and to report
more information for better debugging.
This has only been tested on GFX8, though it should work on GFX6-GFX7.
It seems we need a different implemenation for GFX9+.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Tue, 18 Aug 2020 16:44:07 +0000 (18:44 +0200)]
radv: add a small interface for creating the trap handler shader
Similar to the GS copy shader except that NIR is unused because
the shader is written directly using ACO IR.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Fri, 21 Aug 2020 09:33:22 +0000 (11:33 +0200)]
aco: skip unnecessary compiler pass for the trap handler program
The shader is written by hands with assigned registers, so most of
the pass are unnecessary.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Tue, 18 Aug 2020 16:39:20 +0000 (18:39 +0200)]
aco: add a helper for building a trap handler shader
It's way easier to write a trap handler shader using ACO IR
instead of writing disassembly by hand + clrxasm + copy&paste.
This trap handler is quite simple for now, it just loads a
buffer descriptor from the TMA BO, it saves ttmp0-1 which
contain various info about the faulty instruction, and it
stores some hw registers about the wave/trap status.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Wed, 19 Aug 2020 07:41:42 +0000 (09:41 +0200)]
aco: validate that SMEM operands can use fixed registers
To fix a validation error when loading the scalar tma buffer
descriptor because it's not a temp but a fixed reg (tma_lo/tma_hi).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Tue, 18 Aug 2020 07:26:48 +0000 (09:26 +0200)]
aco: add TBA/TMA/TTMP0-11 physical registers definitions
The TBA/TMA scalar registers are only available on GFX6-GFX8.
On GFX9+, TBA/TMA addr are stored in hardware registers and
the number of TTMP scalar registers is thus increased by 4.
Just keep in mind that tba_lo is actually ttmp0. Best would
be to support ttmp registers in RA but that's more complicated.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Tue, 18 Aug 2020 12:54:51 +0000 (14:54 +0200)]
amd/registers: add some SQ_WAVE_* register definitions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Samuel Pitoiset [Tue, 18 Aug 2020 06:34:33 +0000 (08:34 +0200)]
amd/registers: add missing TBA registers on GFX6-GFX8
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
Erik Faye-Lund [Fri, 10 Jan 2020 21:59:54 +0000 (22:59 +0100)]
nir: add iabs-lowering code
Microsoft's DXIL is based on LLVM, which doesn't have an integer ABS
opcode, but instead needs it lowered to NEG + MAX. We need to do this
with an option, to prevent an already existing optimization rule from
undoing this.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5211>
Eric Engestrom [Mon, 3 Aug 2020 23:31:52 +0000 (01:31 +0200)]
egl: drop invalid shebang
This file exports a variable that is then used in a python script,
but it can never be executed by itself, so having a shebang here
makes no sense.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6166>
Jason Ekstrand [Fri, 14 Aug 2020 20:48:59 +0000 (15:48 -0500)]
clover: Call clang with -O0 for the SPIR-V path
SPIRV-LLVM-Translator isn't really built for handling optimized LLVM IR.
It tends to fall over when, for instance, an optimization generates an
i96 type which isn't legal in SPIR-V. Pass -O0 to avoid these cases.
See https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/203.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6432>
Jason Ekstrand [Thu, 13 Aug 2020 20:12:15 +0000 (15:12 -0500)]
clover/spirv: Don't call llvm::regularizeLlvmForSpirv
writeSpirv() already takes care of that, and calling it twice seems to
duplicate functions and cause problems when processing execution modes.
Fixes: 2043c5f37cf "clover/llvm: Add functions for compiling from..."
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6306>
Jason Ekstrand [Fri, 21 Aug 2020 04:59:54 +0000 (23:59 -0500)]
intel/nir: Allow splitting a single load into up to 32 loads
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
Jason Ekstrand [Wed, 19 Aug 2020 23:53:32 +0000 (18:53 -0500)]
intel/fs: Fix an assert in load_scratch
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
Jason Ekstrand [Fri, 21 Aug 2020 04:47:51 +0000 (23:47 -0500)]
iris: Always re-upload sysvals when we have kernel inputs
They can change on every dispatch and clover never gives us a heads up.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
Jason Ekstrand [Fri, 21 Aug 2020 16:31:18 +0000 (11:31 -0500)]
iris: Normalize all compute shaders to MESA_SHADER_COMPUTE
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
Jason Ekstrand [Sat, 15 Aug 2020 05:26:05 +0000 (00:26 -0500)]
iris: ref/unref the GLSL type singleton in screen_create/destroy
Otherwise, we can run into trouble if the driver is dynamically loaded
via pipe-loader.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
Jason Ekstrand [Wed, 19 Aug 2020 23:56:01 +0000 (18:56 -0500)]
iris: Stop advertising clover-only caps
Both of these are clover-only caps. We don't really support clover and,
even if we did, the number of address bits is wrong and we definitely
don't support the CL path for images.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
Jason Ekstrand [Thu, 20 Aug 2020 15:30:23 +0000 (10:30 -0500)]
iris: Stop advertising PIPE_SHADER_IR_NIR_SERIALIZED
This prevents clover from trying to initialize and crashing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
Karol Herbst [Wed, 19 Aug 2020 14:02:55 +0000 (16:02 +0200)]
clover/nir: add support for global invocation id offsets
v2: create variables only once
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Karol Herbst [Fri, 21 Aug 2020 16:46:33 +0000 (18:46 +0200)]
nir: fix nir_variable_create for kernels
We ended up with INTERP_MODE_SMOOTH but we really just want to have NONE.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Jesse Natalie [Tue, 28 Jul 2020 17:37:09 +0000 (10:37 -0700)]
spirv: Use new global invocation offset system value
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Jesse Natalie [Fri, 21 Aug 2020 17:40:45 +0000 (10:40 -0700)]
nir: Add options to nir_lower_compute_system_values to control compute ID base lowering
If no options are provided, existing intrinsics are used.
If the lowering pass indicates there should be offsets used for global
invocation ID or work group ID, then those instructions are lowered to
include the offset.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Jesse Natalie [Fri, 21 Aug 2020 17:18:14 +0000 (10:18 -0700)]
nir: Move compute system value lowering to a separate pass
The actual variable -> intrinsic lowering stays where it is, but
ops which convert one intrinsic to be implemented in terms of
another have moved.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Erik Faye-Lund [Mon, 13 Jan 2020 09:35:40 +0000 (10:35 +0100)]
compiler/nir: make lowering global-id to local-id optional
For D3D12, we don't want to lower this, as there's a dedicated global-id
system-value that might be faster to use, depending on the hardware.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Jesse Natalie [Mon, 27 Jul 2020 23:56:21 +0000 (16:56 -0700)]
nir: Add new system values and intrinsics for dealing with CL work offsets
New intrinsics are added for global invocation IDs and work group IDs to
deal with offsets in both. The only one of these that needs a system value
is global invocation offset, for CL's get_global_offset().
Note that CL requires very large work group sizes, so these intrinsics
are modified to be able to use 64bit values, for 64bit SPIR-V.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Jesse Natalie [Fri, 29 May 2020 18:09:37 +0000 (11:09 -0700)]
nir: Populate some places where existing system values were missing
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
Eric Anholt [Wed, 19 Aug 2020 18:41:51 +0000 (11:41 -0700)]
ci/bare-metal: Try rebooting chezas again if they get stuck during tftp.
Occasionally something goes weird in the network and a group of chezas
will produce streams of these errors during the tftp process, eventually
timing out after 60 minutes in the job. By the time we notice, the next
jobs seem to go through fine, so watch for them and try rebooting the
cheza to see if that gets our jobs to pass again.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6398>
Eric Anholt [Wed, 19 Aug 2020 23:28:27 +0000 (16:28 -0700)]
ci/bare-metal: Retry booting chezas instead of failing when !POWER_GOOD
If we get this error, we can just try rebooting again and see if it comes
up then. The POWER_GOOD failures are clustered in time, but it's better
to retry a few times in a row in one job (which has its own 60min timeout)
than to spuriously fail someone's pipeline.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6398>
Eric Anholt [Wed, 19 Aug 2020 22:23:24 +0000 (15:23 -0700)]
ci/bare-metal: Convert the main cros-servo boot code to python
Switching this part to python makes the code clearer and cleans up our
logs as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6398>
Eric Anholt [Wed, 19 Aug 2020 20:00:25 +0000 (13:00 -0700)]
ci/bare-metal: Use a new serial buffer tool.
This one uses python threads to move some of our logic from shell
pipelines to python, and opens the door to doing better serial output
tracking in the future (the SerialBuffer.lines() method)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6398>
Chia-I Wu [Thu, 2 Jul 2020 18:40:43 +0000 (11:40 -0700)]
virgl: update protocol headers
Copied from virglrenderer. Some in-development features are guarded by
VIRGL_RENDERER_UNSTABLE_APIS and they should not be used without knowing
the consequences.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6235>
Chia-I Wu [Thu, 2 Jul 2020 18:06:15 +0000 (11:06 -0700)]
virgl: move protocol headers to a common place
Tested with meson. Android.mk changes are not tested.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6235>
Lepton Wu [Fri, 14 Aug 2020 02:14:13 +0000 (19:14 -0700)]
util/ralloc: fix ralloc alignment.
On some malloc implementation, malloc doesn't always align to 16
bytes even on 64 bits system. To make sure ralloc_header always
starts at the wanted alignment, just force the size to be aligned at
the alignment of ralloc_header. This fixes crashed on instruction
like "movaps %xmm0,0x10(%rax)" which requires aligned memory access.
Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6314>
Charmaine Lee [Thu, 20 Aug 2020 22:45:47 +0000 (15:45 -0700)]
svga: fix draw elements with 8-bits indices
With commit
2122b902b80, u_index_translator can return U_TRANSLATE_MEMCPY
for 8-bits indices, and in this case we need to call the translation function
instead of a simple passthrough to the device.
Fixes piglit spec@nv_primitive_restart tests.
Fixes: 2122b902b8 "gallium/indices: don't expand prim-type for 8-bit indices"
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6414>
Charmaine Lee [Thu, 20 Aug 2020 23:43:00 +0000 (16:43 -0700)]
winsys/svga: fix display corruption after surface_init
When we initialize the buffer surface, do not map the existing storage
with DONTBLOCK, leave it as a synchronized map.
This patch also sets the surface rebind flag after it is bound to a
new buffer and sets the surface buffer pointer accordingly.
This fixes display corruption issue seen with running steam.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6415>
Charmaine Lee [Fri, 21 Aug 2020 00:11:22 +0000 (17:11 -0700)]
st/mesa: increase size of gl_register_file bitfields
Bump up the size of the bitfields for gl_register_file type for MSVC.
Also add ASSERT_BITFIELD_SIZE check where this bitfield is used.
Fixes spec@arb_shader_atomic_counter_ops tests in MSVC.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6417>
Karol Herbst [Tue, 18 Aug 2020 17:51:57 +0000 (19:51 +0200)]
nir: rename nir_op_fne to nir_op_fneu
It was always fneu but naming it fne causes confusion from time to time. So
lets rename it. Later we also want to add other unordered and fne, this is
a smaller preparation for that.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6377>
Rhys Perry [Thu, 20 Aug 2020 13:01:58 +0000 (14:01 +0100)]
bifrost: use nir_intrinsic_has_type
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6402>
Rhys Perry [Thu, 20 Aug 2020 13:01:36 +0000 (14:01 +0100)]
aco: use nir_intrinsic_has_access
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6402>
Rhys Perry [Thu, 20 Aug 2020 13:01:23 +0000 (14:01 +0100)]
nir: add and use nir_intrinsic_has_ helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6402>
Rhys Perry [Mon, 17 Aug 2020 10:28:07 +0000 (11:28 +0100)]
aco: fix non-rtz pack_half_2x16
We were using the wrong conversion opcode. The high bits are also not
zero'd on GFX10, which can cause v_cvt_pk_u16_u32 to clamp.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: df645fa369d ('aco: implement VK_KHR_shader_float_controls')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6346>
Danylo Piliaiev [Tue, 18 Aug 2020 07:41:31 +0000 (10:41 +0300)]
glsl: Eliminate out-of-bounds triop_vector_insert
Section 5.11 (Out-of-Bounds Accesses) of the GLSL 4.60 spec says:
"In the subsections described above for array, vector, matrix and
structure accesses, any out-of-bounds access produced undefined
behavior.... Out-of-bounds writes may be discarded or overwrite
other variables of the active program."
Fixes crashes when dereferencing gl_ClipDistance and gl_TessLevel*, e.g:
int index = -1;
gl_ClipDistance[index] = -1;
When LowerCombinedClipCullDistance is true.
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6363>
Danylo Piliaiev [Mon, 17 Aug 2020 15:22:47 +0000 (18:22 +0300)]
glsl: Eliminate assigments to out-of-bounds elements of vector
Several optimization paths, including constant folding, can lead to
indexing vector with an out of bounds index.
Out-of-bounds writes could be eliminated per spec:
Section 5.11 (Out-of-Bounds Accesses) of the GLSL 4.60 spec says:
"In the subsections described above for array, vector, matrix and
structure accesses, any out-of-bounds access produced undefined
behavior.... Out-of-bounds writes may be discarded or overwrite
other variables of the active program."
Fixes piglit tests:
spec@glsl-1.20@execution@vector-out-of-bounds-access@fs-vec4-out-of-bounds-1
spec@glsl-1.20@execution@vector-out-of-bounds-access@fs-vec4-out-of-bounds-6
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6363>
Danylo Piliaiev [Mon, 17 Aug 2020 15:13:24 +0000 (18:13 +0300)]
ir_constant: Return zero on out-of-bounds vector accesses
Several optimization paths, including constant folding, can lead to
accessing an ir_constant vector with an out of bounds index.
Return 0 since GL_ARB_robustness and GL_KHR_robustness encourage
us to do so.
Fixes piglit tests:
spec@glsl-1.20@execution@vector-out-of-bounds-access@fs-vec4-out-of-bounds-2
spec@glsl-1.20@execution@vector-out-of-bounds-access@fs-vec4-out-of-bounds-4
spec@glsl-1.20@execution@vector-out-of-bounds-access@fs-vec4-out-of-bounds-5
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2604
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6363>
Ricardo Quesada [Thu, 2 Jul 2020 13:46:11 +0000 (06:46 -0700)]
anv: support fd==-1 in ImportSemaphoreFdKHR
If fd==-1 is passed in ImportSemaphoreFdKHR, instead of importing the
fd, in creates an already signaled syncobj.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6427>
Samuel Pitoiset [Wed, 19 Aug 2020 08:40:35 +0000 (10:40 +0200)]
aco: add ACO_DEBUG=force-waitcnt to emit wait-states
Sounds useful for debugging missing wait-states and for improving
detection of the faulty instruction in case of memory violations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6386>
Jesse Natalie [Tue, 17 Mar 2020 17:53:33 +0000 (10:53 -0700)]
wgl: Switch to Win10 version defines to enable usage of Win10 WGL callbacks
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6228>
Samuel Pitoiset [Wed, 19 Aug 2020 11:42:57 +0000 (13:42 +0200)]
radv: ignore BB labels when splitting the disassembly string
Ignore everything that is not an instruction. This should fix
the annotated UMR disassembly.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6387>
Tapani Pälli [Thu, 20 Aug 2020 09:49:46 +0000 (12:49 +0300)]
anv: take depth in to account in anv_GetImageSubresourceLayout
Fixes dEQP-VK.image.subresource_layout.3d* tests on gen9.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6400>
Caleb Callaway [Thu, 20 Aug 2020 00:12:10 +0000 (17:12 -0700)]
iris: Add missing newline to debug log message
Without this newline, log messages get lumped together on a single line,
making the debug log difficult to read.
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6413>
Eric Anholt [Wed, 19 Aug 2020 17:51:50 +0000 (10:51 -0700)]
ci/freedreno: List more common flakes reported recently.
Now that adding to our flakes list won't disturb the test order
(potentially just moving the flake to a different result), we can be more
aggressive in listing new flakes.
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6392>
Eric Anholt [Wed, 19 Aug 2020 17:43:54 +0000 (10:43 -0700)]
ci/freedreno: Move our skips lists over to being known-flakes lists.
This makes sure that we keep executing the tests so that we can get our
alerts in IRC and know whether the tests are still flaking. It also keeps
us from having adjustments to the skip list causing failures/flakes to
move to different tests (as seen with a530 having to move some xfails
around after changing the skip list)
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6392>
Eric Anholt [Wed, 19 Aug 2020 17:30:12 +0000 (10:30 -0700)]
ci/deqp-runner: Add a post-deqp-run filter list for known flakes.
So far, we've been putting our known flakes that intermittently fail CI
into the skips list. This has two downsides:
1) You don't know when the flakes stop happening and when to delist them
from skips, unless you go do a bunch of manual runs with the skips list
cleared.
2) If the flake was because the previous test left some broken state in
the HW, you may just move your intermittent to a new test.
With this new path, you can list your flakes in the flakes file to keep
them from erroring out people's pipelines. They still get run and
reported as is.
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6392>
Eric Anholt [Wed, 19 Aug 2020 17:17:17 +0000 (10:17 -0700)]
ci/deqp-runner: Drop unused "count" variable
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6392>
Eric Anholt [Wed, 19 Aug 2020 17:15:12 +0000 (10:15 -0700)]
ci/deqp-runner: Drop stale comment from deqp-runner.sh.
We don't rerun to detect flakes ourselves any more since the runner does
it internally.
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6392>
Jesse Natalie [Wed, 19 Aug 2020 21:34:11 +0000 (14:34 -0700)]
nir: Use 'unsigned' instead of enum types in nir_variable::data
MSVC treats enums as signed, so storing values that use the topmost
bit of the explicitly sized field loads as a negative value instead.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6393>
Jason Ekstrand [Wed, 19 Aug 2020 23:21:33 +0000 (18:21 -0500)]
nir: Add an LOD parameter to image_*_size
The OpenCL image_width/height/depth functions have variants which can
take an LOD parameter. More importantly, LLVM-SPIRV-Translator always
generates OpImageQuerySizeLod even if the LOD is guaranteed to be zero.
Given that over half the hardware out there has an LOD field for image
size queries (based on a rudimentary scan through their NIR -> whatever
code), we may as well just add the source to the NIR intrinsic. If this
is ever a problem for anyone, the lowering is pretty trivial.
I've also added asserts to everyone's drivers that should alert them if
they ever see an LOD other than zero. This will never happen with GL or
Vulkan so there's no need for panic.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6396>
Arcady Goldmints-Orlov [Mon, 10 Aug 2020 03:17:01 +0000 (22:17 -0500)]
broadcom/compiler: Enable PER_QUAD for UBO and SSBO loads.
Helper invocations need to be able to read from UBOs since those values
can be used for flow control, but writes from helper invocations need to
be dropped.
Fixes CTS tests:
dEQP-VK.glsl.derivate.*.uniform_loop.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6356>
Arcady Goldmints-Orlov [Sat, 25 Jul 2020 15:39:31 +0000 (10:39 -0500)]
broadcom/compiler: Add a constant folding pass after nir_lower_io
The nir_lower_io pass produces a bunch of constant arithmetic, and
assumes that constant folding will simplify it away.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6356>
Arcady Goldmints-Orlov [Sat, 25 Jul 2020 20:20:02 +0000 (15:20 -0500)]
broadcom/compiler: support nir_intrinsic_load_sample_id
This adds support for the intrinsic as well as the vir_SAMPID
instruction that corresponds to it in vir.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6356>
Karol Herbst [Sat, 15 Aug 2020 19:49:05 +0000 (21:49 +0200)]
clover/spirv: pass list of supported extensions to the translator
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5038>
Pierre Moreau [Sun, 10 May 2020 21:21:56 +0000 (23:21 +0200)]
clover/nir: Register callback for translation messages (v2)
This allows us to add SPIR-V to NIR translation failure messages to the
program’s compilation log, which can then be queried by the user.
v2: Replace the if-statement in `debug_function()` with an assert.
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Serge Martin <edb@sigluy.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5038>
Pierre Moreau [Mon, 18 May 2020 16:08:37 +0000 (18:08 +0200)]
clover/llvm: Use the highest supported SPIR-V version (v4)
v2:
a) Move `supported_spirv_verssions()` to `spirv::` (Francisco Jerez)
b) Introduce a `SPV_MAKE_VERSION` macro to avoid making mistakes and
making it more readable than its uint representation.
v3: Replaced an if-statement with a `std::min()` in
`spirv::get_spirv_translator_options()` (Karol Herbst)
v4: Turn `SPV_MAKE_VERSION()` into a function (Francisco Jerez)
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5038>
Pierre Moreau [Tue, 5 May 2020 11:44:12 +0000 (13:44 +0200)]
meson: Raise minimum version for SPIR-V OpenCL deps (v4)
SPIRV-LLVM-Translator had API-breaking changes during version 0.2.1.
Since the new API was being used, a higher version has to be requested.
While at it and since SPIRV-LLVM-Translator added a new API to request a
specific SPIR-V version as well as allowed SPIR-V extensions, increase
the version number to the first including those new features.
v2: Require an LLVM version which is compatible with the
SPIRV-LLVM-Translator that was found; that requirement was
previously implicit and would be ensured when that library was
built. Making it explicit will help in cases where multiple versions
of LLVM might be installed.
v3: fix use of undefined _minimum_llvmspirvlib_version_array
v4 (Karol): fix creating the minimum requested version
Simplifing the code
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Serge Martin <edb@sigluy.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5038>
Pierre Moreau [Tue, 5 May 2020 11:14:26 +0000 (13:14 +0200)]
clover/spirv: Print linked SPIR-V module if asked
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Serge Martin <edb@sigluy.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5038>
Pierre Moreau [Tue, 5 May 2020 11:16:55 +0000 (13:16 +0200)]
clover/spirv: Remove unused tuple header
Fixes: 21473865050 ("clover/spirv: Add functions for parsing arguments, linking programs, etc.")
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Serge Martin <edb@sigluy.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5038>
Karol Herbst [Sat, 15 Aug 2020 11:19:52 +0000 (13:19 +0200)]
clover/spirv: rework handling of spirv extensions
What extensions we support depends on spirv_to_nir but it doesn't give us a
list. So hardcode one and add extensions we know we support and hit in the
wild.
v2: move into spirv lib
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5038>
Alyssa Rosenzweig [Thu, 20 Aug 2020 17:36:46 +0000 (13:36 -0400)]
panfrost: Fix alignment on Bifrost
This was real "fun" to debug...
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 373a204bdd7 ("panfrost: Pass alignments explicitly")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6410>
Connor Abbott [Thu, 2 Jul 2020 09:34:54 +0000 (11:34 +0200)]
tu: Enable VK_KHR_multiview
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Thu, 2 Jul 2020 09:33:42 +0000 (11:33 +0200)]
tu: Implement multiview pipeline state
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Mon, 13 Jul 2020 17:27:53 +0000 (19:27 +0200)]
tu: Add multiview lowering pass
For now this only handles an a630 quirk where PC_MULTIVIEW_MASK doesn't
exist. However in the future it will also handle multi-position output.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Thu, 2 Jul 2020 09:12:13 +0000 (11:12 +0200)]
tu: Implement multiview query interactions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Thu, 2 Jul 2020 09:07:34 +0000 (11:07 +0200)]
tu: Improve timestamp queries
As the original comment says, we can't really give the user what they
want if there's a timestamp inside a GMEM renderpass, but we can give
them a better approximation of it. At least sysmem renderpasses will now
have an accurate timestamp.
Also, don't emit the WFI if it's not necessary, based on the stage
flags.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Thu, 2 Jul 2020 09:25:54 +0000 (11:25 +0200)]
tu: Implement multiview clear/resolve interactions
Loads, stores, clears, and resolves now happen per-view. Since we only
support multiview with sysmem rendering, we only implement this for
sysmem clears and resolves.
There aren't any tests that mix multiview and MSAA, so no coverage of
the resolve path.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Thu, 2 Jul 2020 09:16:50 +0000 (11:16 +0200)]
tu: Parse multiview render pass info
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Thu, 2 Jul 2020 08:46:27 +0000 (10:46 +0200)]
tu: Translate VkRenderPassMultiviewCreateInfo to VkRenderPassCreateInfo2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
Connor Abbott [Wed, 1 Jul 2020 14:46:22 +0000 (16:46 +0200)]
ir3: Add support for gl_ViewIndex in VS & FS
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5720>
projects / mesa.git / log