dev-arm: GenericTimer, freq as 32-bit value

The System Counter frequency is now a 32-bit value. This is consistent
with CNTFRQ and CNTFRQ_EL0 register sizes.

Change-Id: I39886a3767adbe9c58887b8b6d5f30ebc6035bcc
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22424
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Disambuiguate NumFloatV7ArchRegs usage

Sometimes NumFloatV7ArchRegs is used to specify the maximum number of
AArch32 floating point registers. Sometimes it is just used for indexing
a free register storage to be used by microcode.  In that scenario,
VecSpecialElem should be used, which is a index to the first available
non architectural register for floating point.

Change-Id: I4e84740701f0e7041cf1acad2afed471361c423a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23107
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Unify VLdmStm behaviour when reg out of index

The generic VLdmStm class (modelling A32 VLDM/VSTM) is handling a wrong
register list in a inconsistent way. Some instructions are opting
for being decoded as Unknown, while others handle it inside the
macro instruction constructor by manually adjusting the reglist.

Those are two valid implementation of the CONSTRAINT UNPREDICTABLE
behaviour (1 and 3):

"If regs > 16 || (d+regs) > 32 , then one of the following behaviors must
occur:
1) The instruction is UNDEFINED .
2) The instruction executes as NOP .
3)  One or more of the SIMD and floating-point registers are UNKNOWN . If
the instruction specifies writeback, the base register becomes UNKNOWN .
This behavior does not affect any general-purpose registers."

This patch unfies the behaviour by always opting for option 1) over 3)

Change-Id: I4f98409243d5a2ec64113fe9c87e961a391abe94
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23106
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix NumVecV7ArchRegs value (64->16)

In armv7 there are 16 only quadword (vector) registers which are usable
by SIMD instructions (Q0-Q15). Those completely overlap with the 32
double word registers (D0-D31).

NumVecV7ArchRegs  = 16; // Q0-Q15

Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Reorder arch/arm/registers.hh constants

This is putting some order in the constants definition, respecting
the description which divides:

* Constants Related to the number of registers
 (example: const int NumFloatRegs = 0)

from:

* Semantically meaningful register indices (to indicate special
  registers)
 (example: const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs)

Change-Id: I1760b7f786b6f6becbe8ab445e65fc3fa17206cb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23104
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs

gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)

Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>

tests: AArch64 Linux as quick regressions (instead of AArch32)

NOTE: Following the discussion on the current patch review, some
regressions have been moved to the long list (realview64-simple-atomic
and realview64-simple-timing) in order to reduce computation time. These
should be moved back to the quick list as soon as we get more computing
power.

Change-Id: I07b98c968ad35bf4c7b3646cb72d870e6b07b0d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22686
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Add Request::isMasked to check for byte strobing

This is trying to overcome the following problem: At the moment a memory
request with a non empty byteEnable mask will be considered masking even
if all elements in the vector are true.

Change-Id: I16ae2c0ea8c3f3370e397bab9d79d6d60c3784bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23284
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add byteEnable copy to Request copy constructor

Change-Id: Ie97543e62524bb244ae65eef096411af4605c175
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23283
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Increase jenkins test timeout to 4 hours.

Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23463
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: set MaxMiscDestRegs to 2

In an earlier patch, the FCSR was split into its two components, FRM and
FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With
the O3 CPU model, which defers them both to later, this creates a bug
where an assertion that the number of CSR writes must be less than
MaxMiscDestRegs fails because that constant is 1. This patch sets it to
2 so the O3 CPU is compatible with this scheme.

Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23220
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Set the partial linking group for EXTRAS dirs.

Partial linking heuristically links together files in the same
directory by setting a special automatic tag. That tag needs to also
be maintained when scanning EXTRAS dirs so that they don't all get
lumped in with the last normal directory that was processed.

Change-Id: I2408ea0a1eeffcf6d9994c36415a35760b225b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23300
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Fixes to improve python 3 support.

Some simple fixes to improve python 3 compatability in scons.

Change-Id: I89aba6ed9d73ee733307c57e033c636029d9cb7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23264
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a git commit-msg hook

Add a git commit-msg hook that verifies that commit messages follow
gem5 guidelines.

Commit messages must contain the following components:
    <gem5_tags>: <title>

    <description>
    <patch_tags>

<gem5_tags> are comma separated keywords (found in MAINTAINERS) that
describe which sections of gem5 are being modified by the patch.
Two special keywords can also be used to imply that the author is
looking for feedback on the way their commit was implemented (RFC),
and to inform that the commit is a work in progress (WIP).

<title> A short and concise description of the commit without trailing
whitespaces

<description> is an optional (yet highly recommended) detailed
description of the objective of the commit.

<patch_tags> describe the metadata of the commit, and most of them
are automatically added by Gerrit.

Change-Id: Ib6fb6edf6d1417bfda23729b35c5b8ed44d2cf51
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21739
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

kvm,arm: Update the KVM ARM v8 CPU to use vector regs.

The exact mapping of the KVM registers and the gem5 registers is direct and
may not actually be correct.

Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: fix asmtest concurrent issues.

riscv asmtest uses multiprocessing.Pool to run multiple gem5
processes concurrently.

By using gem5 default options, processes will fail because:
 - accessing to the same m5out directory
 - listening too many remote gdb ports at the same time

This will set independent m5out directories and disable remote gdb
ports for asmtest gem5 processes.

Change-Id: Ie4c81232210568cd1945adc2b99eebc019d705b6
Signed-off-by: Xin Ouyang <xin.ouyang@streamcomputing.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22863
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: missing override specifier

Change-Id: I5a6db4632ec5b670cbfeb7d52190a7545c0b985f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23380
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Adding LDDQU instruction

Tested with simple c binaries.

Signed-off-by: marjanfariborz <mfariborz@ucdavis.edu>
Change-Id: I2f0852b136f966381d29af523e8ffdbca795afcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a suppression mechanism to the SyscallReturn class.

It makes more sense to specify whether something should be returned
based on the return, not intrinsically on the syscall. This is
especially true in cases like execve where the expected behavior
is not constant.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I95b53b6d69445c7a04c0049fbb0f439238d971e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23166
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Small style fixes in sim/syscall_return.hh.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I485004843393c2e10c1ff4dbd84fc30ca4fd490c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23165
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Change the syscall executor to a std::function.

This will enable using other types of callable like a lambda.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: If9f7176205492830824b5fe3c00f2c7710f57f70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23164
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Fix the getresuidFunc prototype.

When the syscall signature was changed to not take a Process pointer,
the prototype for getresuidFunc was not updated.

Change-Id: I887cc3e3aa8483fc608df9963876a0ac6fa2251d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23320
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Fix the predecoder's moreBytes method.

Endianness transformation was moved from the CPU into this method,
making the "inst" parameter guest endian instead of host endian. The
emi member of the decoder was set using the betoh method, ensuring that
it was still stored in host order. Unfortunately, the "inst" parameter
was used in some places when setting up the rest of emi.

This change replaces those uses of inst with emi.

Change-Id: I0c7f9a1833db4b64fc1a5015cf10f6ba3f7c26a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23163
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Purposefully *expose* bind in the initiator socket.

Apparently the base version of bind actually *is* supposed to be
accessible, so expose it with using instead of hiding it.

Change-Id: Ie762c35d6322e744696ed597189b7773ea68c3b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23322
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Switch the diagnostic pragmas to GCC from clang.

Clang can handle both, and GCC throws a fit if it sees pragmas for
clang.

Change-Id: Ie9f2789f45706223b11ed5acdf8b371de6e7ee24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23321
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: CONTRIBUTING.md to advise linking Jira Issues in commits

Jira Issue: https://gem5.atlassian.net/browse/GEM5-186

Change-Id: I9fa1471627aed139c0ff207e35a32d9faa82eeb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,sim-se: move error checks in syscall methods

There is a check on a global flag denoting that the simulator
has been configured to run in fullsystem mode. The check is
conducted at runtime during calls to syscall methods.

The high-level models are checking the flag when the check
could be conducted further down the call chain (nearer to the
actual Process invocation). Moving the checks should result
in less copy-pasta as new models are developed. It might be
argued that the checks should stay in place since an error
would detected earlier; that may be true, but the error
would be the same and the simulation should fail in either
case. This arrangement requires fewer lines of code.

The changeset also changes the check into a fatal error
instead of a panic since usage (in fs mode) should result
in immediate corruption.

Change-Id: If387e27f166ac1374f3fe8b7befe3546e69adba7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23240
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc,fastmodel: Use the gem5_scons error and warning functions.

Use them in place of messing with termcap directly.

Change-Id: I093efa95e6b6ea7af198dc1395dce05ca6d6575f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23263
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Suppress a spurious clang warning in the systemc headers.

Change-Id: Ife2251d370133383debda9b0439cb84eca80978d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Fix up some lingering Accellera specific code in TLM v1.

This was missed initially, but clang complained about it.

Change-Id: Ie6d240447a74f96faf9da87bd2f1134c1d82be8e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23128
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: add the FmtStackTrace debug option

If given, a stack trace is printed after every debug message.

This helps to localize where debug messages are being called from,
which is often the critical information needed to debug certain
problems.

Change-Id: I82b8990c0d286393d5bdab05f718be3e89eadc40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22003
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Avoid function overloading for syscall implementation

This patch is aligning the readlink and access syscalls to the open one,
which is not overloading the openFunc, but it is factoring the
implementation into a openImpl, which is used by both open and openat.

This is needed if passing them to std::function, whose constructor is
not able to handle overloaded functions.

Change-Id: I50a8aacdfd675181b6fe9a2696220ee29cc5bc4b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23260
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Add a bunch of missing overrides to the systemc headers.

Change-Id: I664d7b5e7c3b4dd6128d261c95fabaa3d1a97d88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23125
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Suppress a spurious warning on clang for amba_pv.h.

This header comes from the fast model distribution and so we can't
(easily) disable the warning locally.

Change-Id: I2c1eee48f8970bb17466f0759f0077a5d45e76af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23123
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling of immediate for c.lui instruction

For compressed instruction c.lui, the 6-bit immediate is left-shifted by 12
bits in decoding. While the original Gem5 gives the left-shifted value
directly in disassembly.
This patch fixes the problem by adding a new template CILuiExecute to
resume the immediate before outputting it in disassembly.
Note: The immediate is sign-extended to 20-bit to be compatible with GCC.

Change-Id: If73f72d3e8f85a8b10ce7a323379d8ad6c4c3085
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22567
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Automatically assign PCI device ids in attachPciDevice

Simulation scripts currently need to assign PCI device addresses when
adding new devices. This change moves this responsibility to the
VExpress_GEM5_BASE::attachPciDevice method.

Change-Id: I6d62af8a8f9176d964cc011dd8fb9744154bbb87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22830
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev-arm: device name in AmbaFake accesses

This patch prints the name of the AmbaFake device being accessed.
This is useful for identifying the device triggering the warning.

Change-Id: I69ca06d5d9bce73d918b8c8b46bb43e92597933b
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22847
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Avoid hiding a virtual method in the dictionary compressor.

The non-virtual version is later used in overrides of the virtual
version whcih takes more arguments.

Change-Id: I102d1185c7a616337c2a0429daa998706189292f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23127
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Remove a std::move clang says is unnecessary.

It also says it prevents an optimization.

Change-Id: I9c21dc1a0c53cf70cefd1400564de07d1e845a75
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23124
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Make sure not to shift off of the end of a uint32_t in KVM.

The methods which set or get an attribute from the virtual GIC use a
shift constant which is 32, but they store their result in a 32 bit
variable and, according to clang, are used to shift 32 bit inputs. This
is undefined behavior in terms of the shift, and will truncate off the
value regardless.

Change-Id: Ie9543ab9e6e1d5f86317a9210d220928b23ffaf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23129
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

base, python: Allow dirname selection for the interpreter

This is the second step towards being able to run dynamically linked
applications when the guest ISA != than host ISA.

Once the guest interpreter is loaded to memory, we are able to redirect
shared object loads through the redirectPath interface.
How do we load the guest interpreter?
The elf file is for example asking for the /lib/ld-linux-aarch64.so
interpreter.
That would point to a valid dynamic linker/loader if guest ISA == host
ISA, but if we are running on X86 we should point to the guest
(aarch64 in the example) toolchain wherever it is installed.

This patch is adding the --interp-dir option to point to the parent
folder of the guest /lib in the host fs.

Change-Id: Id27b97c060008d2e847776a49323d45c8809a27f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23066
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add --redirects for syscall emulation

This is the first step towards being able to run dynamically linked
applications when the guest ISA != than host ISA.

(Like running a arm application on x86)

By using the --redirects command line option it is possible to specify
via CLI a set of path redirections to be used in SE mode.

This is needed when running a dynamically linked binary in
SE mode in a guest ISA different than the host. The linker will look
for SOs (e.g. libc.so) in /lib/, but will only find the host libraries.
With this option we can redirect to the guest toolchain/file system.

Usage:

gem5.opt [example script]
    --redirects /dir1=/path/to/host/dir1 \
    --redirects /dir2=/path/to/host/dir2

Change-Id: I558838be2ad6802891707e9a1cc454786859db15
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23065
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix DPRINTF_UNCONDITIONAL on gem5.fast

Change-Id: I1e559f9c5daae1e9af307cd352791c1b1ac9bbdb
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23108
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add root redirect path in SE mode only when set

As it is now, the default behaviour, if chroot is not specified, is to
add a redirect path which is simply mappping "/" in guest to "/" in
host.  This patch avoids this unnecessary mapping, and adds a redirect
path to root only if chroot is specified.

Change-Id: Icbe863887330d7071e0005333b408ffc8cad41d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23064
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Check Path redirection when mmapping

Every syscall file access should go through the redirection process

Change-Id: I1ba2063b5a254e11f47392bdad0bf0887ba73d3d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23063
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix baremetal platform

With 224da08be767b51e8148e5f3e6e0da2e2ea77add some MemConfig
functionalities have been moved to the ObjectList module

Change-Id: Iab073b6f8be5a5ea0e49e8974960d7734a5640ba
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23083
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: prefix --debug-flags Event logs with the flag name

Sample output of FmtFlag,ExecAll,Event:

   0: Event: Event_70: generic event rescheduled @ 18446744073709551615
   0: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue
   0: Event: AtomicSimpleCPU tick.wrapped_function_event
 500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+4
 500: Event: AtomicSimpleCPU tick.wrapped_function_event
1000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8
1000: Event: AtomicSimpleCPU tick.wrapped_function_event
1500: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+12
1500: Event: AtomicSimpleCPU tick.wrapped_function_event

Change-Id: I7f252b57d7778a15a3dda40d909bdb4425557a40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22009
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: prefix ExecEnable to the native trace to match DPRINTF

The trace mechanism appears to be the only debug flag that does not
go through DPRINTF, presumably for performance reasons.

This patch manually adds that to make things uniform with other debug
flags, e.g. with FmtFlag,ExecAll,SyscallBase a sample output looks like
(truncated to fit into commit message lengths):

   0: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue
 500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+4
1000: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+8
1500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+12
2000: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+16
2500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+20
3000: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+24
3500: ExecEnable: system.cpu : A0 T0 : @asm_main_after_prologue+28

Change-Id: Ic371ebc8b0827656f1b78fcfd3f28505a5100274
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22007
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: generalize ExecTicks to all messages with FmtTicksOff

If FmtTicksOff is given, ticks are disabled for all log messages.

The original motivation of this is to bring the implementation of native
traces closer to that of other traces to help refactoring done in future
patches.

One additional advantage of this is that sometimes we want to compare
traces of a given program under different conditions, so the start of the
ROI is different, and the different initial timestamp makes a diff
useless by showing differences on every line.

Change-Id: Idd6cb105d301b3b9b064996043f4ca75ddafe0af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22006
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: create DPRINTF_UNCONDITIONAL

This is similar to DPRINTFN, but it also prints a given flag to allow
communicating to users which flag enabled a given log.

This is useful for logs which are enabled with DTRACE instead of directly
with DPRINTF.

Change-Id: Ife2d2ea88aede1cdcb713f143340a8788a755b01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22005
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: add the --debug-flag to DPRINTF output with FmtFlag

This makes it easier to determine which messages come from which
flags when enabling multiple flags at once.

This commit covers the bulk of the debug messages, which use the DPRINTF*
family of macros. There however macros that use DTRACE to check for
enable, those will be covered in future patches.

Change-Id: I6738b18f08ccfd1e11f2874b426c1827b42e82a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22004
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Make the Tarmac parsed registers case insensitive

This will make parsing more robust, considering the tarmac
format changes between AA32 and AA64.

Change-Id: I0e4905d70e2e494104706a4c6c75b8169deaecf9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22845
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix immediate decoding for integer shift immediate instructions

The "shamt" in integer shift immediate instructions is an unsigned
immediate encoded in bits[25:20]. While the original Gem5 uses bits[31:20]
as an int64_t. This patch fixes the problem by:
- Adding a new parameter "imm_code" for format IOp and use the correct
bitfields SHAMT5 or SHAMT6 to assign "imm_code" for each instruction.
- Use uint64_t instead of default int64_t to assign parameter "imm_type"
of format IOp.

The instructions affected include:
- Shift Left Logical Immediate, slli
- Shift Right Logical Immediate, srli
- Shift Right Arithmetic Immediate, srai
- Shift Left Logical Word Immediate, slliw
- Shift Right Logical Word Immediate, srliw
- Shift Right Arithmetic Word Immediate, sraiw

Change-Id: Iad34ccd036c11630409f84f6de2b939224e100e6
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22563
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling for fence and fence.i

The original Gem5 does not give correct disassembly for instruction fence
and fence.i. This patch fixes the problem by adding two bitfields PRED and
SUCC and a new format FenceOp and a template FenceExecute, in which
operands are generated based on PRED and SUCC in the disassembling
function.

Change-Id: I78dbf125fef86ce40785c498a318ffb1569da46c
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22569
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.

This conditional compilation was unnecessary and makes gem5 more
brittle and harder to understand.

Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Stop serializing ISA values wihch are cached from the system.

These values are not really part of the ISA state and could be
retrieved from the system during execution. Also these values are
already being set in the ISA constructor.

Change-Id: Iea5f9bbb27add4ecebc6391da6c1c1e49e76508f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22543
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: default MIDR for Armv8 ISA processors

Software such as Trusted Firmware-A checks the MIDR register
to identify which core model is present in the platform.
The previous default value referred to a Cortex-A15 Armv7-A
processor, however when AArch64 is enabled, an Armv8 processor
is expected.
This patch assigns the Cortex-A57 MIDR if AArch64 is enabled.

Change-Id: Id1677a77d2f04843423f7b013405445f3d253399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22846
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Adjust off_chip ranges in VExpress_GEM5 platform

This is need after commit b4c9996d894118be04cdf4ed793b35a1d5001942
which makes the AddrRange end address non inclusive.

Change-Id: I859b84f6a91107815236b67c4596291c78881fe3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23003
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: log thread activate and suspend with --debug-flags Thread

The original motivation of this is to help debug syscall emulation
deadlocks.

Change-Id: I1c4f611fa2f2e464a30dc92baac89ca819e16a97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21759
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: don't wake up threads that are halted on futex

At Ia6b4d3e6148c64721d810b8f1fffaa208a394b06 the futex wake up started
skipping selecting threads that are already awake, which already prevented
some deadlocks.

However, threads that are Halting or Halted should not be woken up either,
as those represent cores in which processes have already exited.

Before this commit, this could lead an exited core to wake up, which would
then immediately re-execute the exit syscall, and possibly leave one
genuinely sleeping core locked and:

Exiting @ tick 18446744073709551615 because simulate() limit reached

Change-Id: I1531b56d605d47252dc0620bb3e755b7cf84df97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22963
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling for atomic instructions

The original Gem5 does not give correct disassembly for atomic
instructions, which are implemented with one or two micro instructions.
The correct register indices are not decoded until subsequent micro
instruction is processed. This patch fixes the problem by getting the
register indices and other properties (aq and rl) from certain bitfields
of the machine code in the disassembling function.

Change-Id: I2cdaf0b3c48ff266f19ca707a5de48c9050b3897
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22568
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix disassembling of operand list for compressed instructions

In disassembling compressed instructions, the original Gem5 gives needless
operands, such as register or immediate. This patch fixes the problem.
- Existing formats fixed: CIOp, CJOp, CBOp and Jump.
- New formats added: CIAddi4spnOp (for c.addi4spn only) and CompressedROp (with
  templates CBasicDeclare and CBasicExecute)

Change-Id: Ic293836983256a59d3a7aca091c8184b410516a4
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22566
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

arch-riscv: Fix disassembling of immediate for U-type instructions

For U-type instructions auipc and lui, the 20-bit immediate is left-shifted
by 12 bits in decoding. While the original Gem5 gives the left-shifted
value directly in disassembly.
This patch fixes the problem by
- Assign the original 20-bit immediate to internal variable "imm".
- Output "imm" directly in disassembly, as how the original Gem5 does.
- Do the left-shift to "imm" later in the function defining of each
instruction, rather than in decoding.

Change-Id: I300e26fd9c79478783c39fcd6ff70ea06db88884
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22564
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix bug in serialize and unserialize of Interrutps

When serialize and unserialize an variable, the parameters passed to
SERIALIZE_SCALAR() and UNSERIALIZE_SCALAR() must be the same and should be a
general variable name. If not, the expected item would not be found with
UNSERIALIZE_SCALAR() and a fatal error would be introduced.
This patch fix the bug in class Interrupts of RISCV.

Change-Id: I7dd7ab6805651149304959bdf7ee9f3be9d9eaff
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22643
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

scons: Use the new error() and warning() methods.

Also clean up some error messages which were missing capitalization,
etc.

Change-Id: Iaef6b4343a693d30b579e72218cbb7723ebf7d48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22886
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add "warning" and "error" methods.

These methods will make reporting errors less verbose and more
consistent, since they'll handle some formating, setting colors,
prefixing with an appropriate "Warning:" or "Error:" tag, and exiting
in the case of an error.

Change-Id: Iddea5bf342a4fc4b26002d8e98292f9dc57fa8cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22885
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Use HAVE_PROTOC when building protobuf files.

Also wrap PROTOC in {}s which is better form.

Change-Id: I3f80c260593a1d5b7fb5394fe4b71cb774e652ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22884
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Don't use PROTOC for the protoc command and to flag its presence.

Commands that blindly use PROTOC will try to execute "False" which is
very confusing for someone looking at the console output and error
messages. Instead, create a new environment setting HAVE_PROTOC which
is either true or false depending on if the protoc command exists and
passes muster.

Also, if there's an error running protoc, catch that and use it to
mark protoc as unavailable. The previous behavior was to supress errors
and just return an empty string instead, I assume with the expectation
that that would be an invalid version and fail later checks.

Change-Id: I1251b4e7e0e9894cdd3343e59498cc653b648b26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22883
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,base: Added GTests for exec_ecoff.h and exec_aout.h

Change-Id: Iec76ba24a06425caefd28d640c6479720f401c06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22323
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

test,base: Added GTest for base/loader/image_file_data.cc

image_file_data.cc reads an image file, or an image file compressed with
gzip. Mock image file data, and that data in a gzipped state, has been
included in base/loader/small_image_file.test.hh to aid testing.

Change-Id: I69691b93ca03c34d6bd736cbc5c6503115bd7b3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22743
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Remove tests making use of Big/LittleEndianOrder Namespace

Unit tests are currently broken.
commit d40f0bc579fb8b10da7181d3a144cd3e9a0a0e59 is removing the
BigEndianOrder and LittleEndianOrder namespace.
Therefore we shouldn't test them and their helpers.

Change-Id: I68a45f264b782334d0a0f725c2c435c27337e757
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22943
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base,tests: Expanded GTests for addr_range.hh

These tests assume the "end address" is not included in the range. This
exposed some bugs in addr_range.hh which have been fixed. Where
appropriate code comments in addr_range.hh have been extended to improve
understanding of the class's behavior.

Hard-coded AddrRange values in the project have been updated to take
into account that end address is now exclusive. The python params.py
interface has been updated to conform to this new standard.

Change-Id: Idd1e75d5771d198c4b8142b28de0f3a6e9007a52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22427
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: gitignore the aarch64 bootloader object files

Change-Id: I0cb494fb82c557cfce553bc925ea89a8220e4c16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22826
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: ignore .gen directory that contains DTS files

Those files are removed by default because they are intermediary,
but it is possible to explicitly build them with an explicit target:

make .gen/armv7_gem5_v1_1cpu.dts

Change-Id: Id86968fbb2f2b95ce71109de5a0cb8039a048a27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22825
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Use dts include instead of cpp in ARM DTBs

Change-Id: I342691a42e84dfe53659a7acb3b8db04e52e3002
Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22824
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Rework boot loader makefile to be more generic

add all, clean and install rules
use variables for CROSS_COMPILE, CC, LD, DESTDIR
use generic rules to produce objects and link

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
[ciro.santilli@arm.com: Also add BUILDDIR and to allow fully
 out-of-tree builds.]
Signed-off-by: Ciro Santilli <ciro.santilli@arm.com>
Change-Id: Id84bc6a8e5dde409b6fb968925ca268376730196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22823
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests, base: Added GTests for base/intmath.cc

Testing intmath.hh and intmath.cc. Here is the
list of the functions that are tested.
intmath.isPowerOf2, intmath.power, intmath.floorLog2,
intmath.ceilLog2, intmath.divCeil, intmath.roundUp,
intmath.roundDown. Other functions are not tested,
because they are not currently used and are dead code.

Change-Id: I150ac1b5cead93c6698a8c9e9cec80bd87ef181a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22081
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Mahyar Samani <msamani@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests, base: Removed dead code from base/intmath

The below list of functions were dead code and are now
deleted.
intmath.prevPrime, intmath.isPrime, intmath.leastSigBit,
intmath.floorPow2, intmath.ceilPow2, intmath.isHex,
intmath.isOct, intmath.isDec, intmath.hex2Int. The source
file intmath.cc is now effectively useless and deleted.

Change-Id: I28e4350056b8d03e02fecd5c7f7f9c62bc2df7ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22584
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

arch: Get rid of the (Big|Little)EndianGuest namespaces.

These namespaces were used to set up an environment/context where there
was an implicit guest namespace. This is an issue when there may be
multiple guest endiannesses which might be different. In cases where
we don't know what the guest endianness is, we can't rely on it being
an implicit part of our context since that would be ambiguous. In cases
where we do know, for instance in ISA specific code, we can just use
the endianness specific version that's appropriate for that context.

This also (somewhat) removes the assumption that there is a single
endianness that applies for a particular ISA. Practically speaking this
assumption will probably still stand though, since there would likely
be a non-trivial performance penalty to apply a configurable endianness
instead of a fixed one the compiler can optomize/remove.

Change-Id: I2dff338b58726d724f387388efe32d9233885680
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Make and use endian specific versions of the mem helpers.

Rather than using TheISA to pick an endian conversion function, we can
have a version defined for big and little endian and call the right one
from the ISA code.

Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: R/W interface to AArch32 HCR2 misc reg

This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.

Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.

Members `tc` and `ongoingTranslation` were uninitialized in the constructor for
`QueuedPrefetcher::DeferredPacket`. If `ongoingTranslation` is not initialized to
`false` by default, some translation requests from queued prefetchers are not
properly handled and executions are nondeterministic.

Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22844
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix destructor of `BasePrefetcher::PrefetchInfo`.

The destructor of `BasePrefetcher::PrefetchInfo` was calling `delete` for a
dynamically-allocated array. Changed to `delete[]` to remove potential undefined
behaviour.

Change-Id: I6f531bfb6fb7108f1d3e743ae0384d80173e15ef
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22843
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix short descriptors cacheability during table walks

This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits.

Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix long descriptors cacheability during table walks

Prior to this patch table walks were always cacheable unless
cacheability was globally disabled by SCTLR.C being 0.  Arm allows to
select the memory attributes of table walks via the TCR registers.

For example the TCR.IRGN0 bits:

Inner cacheability attribute for memory associated with translation
table walks using TTBR0_EL1.

IRGN0   Meaning
0b00    Normal memory, Inner Non-cacheable.
0b01    Normal memory, Inner Write-Back Read-Allocate Write-Allocate
        Cacheable.
0b10    Normal memory, Inner Write-Through Read-Allocate No
        Write-Allocate Cacheable.
0b11    Normal memory, Inner Write-Back Read-Allocate No Write-Allocate
        Cacheable.

Note: we check IRGNx bits (Inner Shareable domain) instead of ORGNx
(Outer Shareable domain) since in gem5 we consider everything as
Inner Shareable.

Change-Id: If472c218040029c9d165b056a052f522d48d4a82
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22723
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added GTests for byteswap.hh

In addition to the test, "#include base/logging.hh" was added to the
"byteswap.hh". It is is required to compile the header.

Added tests ByteswapTest.swap_byte64, ByteswapTest.swap_byte32,
ByteswapTest.swap_byte16, ByteswapTest.swap_byte, ByteswapTest.htog,
and ByteswapTest.gtoh. The file byteswap.hh is mostly templates.

Added test for BigEndianGuest and LittleEndianGuest namespaces.

Change-Id: I8870a55594ed439fe9e1fb333384f73261d1b1b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22080
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Specify a non-default root folder for regressions

The new testlib library is looking for regressions walking from
a root folder. This by default points to the tests dir.
Since all regressions are supposed to live in the tests/gem5 subdir,
the patch is assigning the gem5 subdir as a root directory.

This will prevent the example garbage to be printed in the ci framework:

Exception thrown while loading
"/tmpfs/src/git/jenkins-gem5-prod/tests/long/fs/10.linux-boot/test.py"
Ignoring all tests in this file.
Exception thrown while loading
"/tmpfs/src/git/jenkins-gem5-prod/tests/long/fs/80.solaris-boot/test.py"
Ignoring all tests in this file.
[...]

Change-Id: Ia12c6bbeda4ceac71ccd38156ab1e3bb98b05c89
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22726
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests, base: Removed ambiguity from base/intmath.hh

The function intmath.leastSigBit is ambiguous given
its name. It does not return the value of the least
significant bit, or the position of the least significant
set bit, but instead 2 to the power of the position of
the least significant set bit. It has thereby been removed
and the function intmath.isPowerOf2 has been refactored to
not require intmath.leastSigBit.

Change-Id: I22479c666cdd059865b8c73b70b5388f98a4584d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22583
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Refactor code to check if gic is GicV2

Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is
only meanful to GicV2.

Test: Boot Android P successfully with the following command:
M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt
./configs/example/arm/fs_bigLITTLE.py --dtb
$PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel
$PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img
--kernel-init "/init" --cpu-type fastmodel --machine-type
VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0
--mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000
console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB
root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2
android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5
androidboot.selinux=permissive audit=0 cma=128M"

Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

config: Add fastmodel cluster in fs_bigLITTLE.py

One can create a system with ARM FastModels CPU and GICv3 with
--cpu-type fastmodel --machine-type VExpressFastmodel options.
Currently the FastmodelCluster only supports one CPU.

Change-Id: I2e985f08f9df01a703e21441c6f9bc1fbae4a222
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20901
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add VExpressFastmodel platform

A VExpress based platform with FastModelGIC as interrupt controller.

Change-Id: I5ef6d04573d271225d7b39c110e93350a290c371
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21359
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Replace most htog and gtoh with htole and letoh.

We already know what endianness to use when with ARM. In places where
a ISA was being supplied through an argument, those were left as htog
or gtoh.

Change-Id: Iff01e8b09a061d9a72e657cdd4570836e0da933f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22372
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: fix routeToHyp for AArch64 in faults

This patch fixes several bugs in Fault classes "routeToHyp" member
function by which mode checking was not taking into account AArch64
execution state. For the particular case of SVC calls from NS EL0, this
prevented a correct routing to EL2 when HCR_EL2.TGE was set.

Change-Id: I5815fe6dcf4501f52bf92f61687ef6d6ef950e52
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22725
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

tests: Added GTests for base/chunk_generator.hh

Change-Id: Ic6ededfc7fed1f91a75e48a0933e61b4670e5af1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21679
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

fastmodel: Implement reading vector registers with readVecReg.

The n other flavors of vector reading functions and all the vector
writing functions are not implemented currently.

Change-Id: I0c25c3ba47c7e4072da3d28596f44f6073b6f609
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

tests: Added GTests for base/types.cc

Change-Id: I9515735efdd452a9f8c98f37f4ec2c27120929f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21659
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,base: Added GTests for base/condcodes.hh

The documentation for the "findParity" and "findCarry" functions in
base/condcodes.hh has been enhanced to better explain their behavior.

Change-Id: I9ba3bf68eb56529a3030e965ec21e41d2dacfad6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21639
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Using super in arm_generic whenever possible

This exclude the case where multiple inheritance is used.

Change-Id: Id1a46ca5c6c526a1a29a2cff7b00d7e3b6a79273
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22685
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Using super for calling superclass __init__

Change-Id: I19906db9ce1b9ffb4107b47fe2bc64a8e005e776
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22684
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Remove Noncoherent cache from regressions

Change-Id: I1d499477acec09fd0b36e3b7c2f5eecee737bd93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22683
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>