i965/disasm: Improve render target write message disassembly.

Previously, we decoded render target write messages as:

   render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0

which made you remember (or look up) what the numbers meant:

1. The binding table index
2. The raw message control, undecoded:
   - Last Render Target Select
   - Slot Group Select
   - Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...)
3. The dataport message type, again (already decoded as "RT write")
4. The write commit bit (0 or 1)

Needless to say, having to decipher that yourself is annoying.  Now, we
do:

   render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0

with optional "Hi" and "WriteCommit" for slot group/write commit.

Thanks to the new brw_inst API, we can also stop duplicating code on a
per-generation basis.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Rename msg_target to SFID.

We haven't used the name "message target" in a while - there are a lot
of things called "target", and it gets confusing.  SFID ("Shared
Function ID") is the term commonly used in the modern documentation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Fix typo in RT UNORM write message.

The name of this message is "Render Target UNORM Write" (Sandybridge
PRM, Volume 4 Part 1, Page 210).  Drop the bogus 'c'.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Use Gen6+ SFID case labels.

Most developers will recognize the Gen6+ SFID names more quickly than
the Gen4-5 ones.  Given that they're the same values, just use the new
names.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: "Handle" Gen8+ HF/DF immediate cases.

We should print something properly, but I'm not sure how to properly
print an HF, and we don't have any DFs today to test with.

This is at least better than the current Gen8 disassembler, which would
simply assert fail.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/disasm: Cut piles of duplicate swizzle printing.

Making a helper function saves us from cut and pasting this four times.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly decode negate source modifiers on Broadwell.

This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da
to brw_disasm.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve disassembly of atomic messages on Haswell+.

This backports the atomic message disassembly support from
gen8_disasm.c, which additionally offers support for decoding atomic
surface read/write messages, and showing SIMD modes and other details.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Actually disassemble Gen7+ URB opcodes.

I never bothered implementing the disassembler for Gen7+ URB opcodes, so
we were just disassembling them as Ironlake/Sandybridge ones.  This
looked pretty bad when running Paul's GS EndPrimitive tests, as the
"write OWord" message was decoded at ff_sync, which doesn't exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Decode Broadwell's invm/rsqrtm math functions.

We don't use these yet, but we may as well disassemble them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble all32h/any32h align1 predicates.

While we're adding things, use symbolic constants rather than magic
numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Add #defines for any32h/all32h predication.

These have existed since Ivybridge.  We don't use them today, but the
Gen8+ disassembler supports them, and I'd like to use symbolic names
rather than magic numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Mark ELSE as having UIP on Gen8+.

This makes brw_disasm.c able to disassemble ELSE instructions correctly
on Broadwell.  (gen8_disasm.c already handles this correctly.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble jump targets on Gen4-5.

Previously, our dissasembly for flow control instructions looked like:

0x00000040: else(8)         ip          65540D     { align16 switch };

It didn't print InstCount properly for ELSE/ENDIF, and didn't even
attempt to disassemble PopCount.

Now it looks like:

0x00000040: else(8)         Jump: 4     Pop: 1     { align16 switch };

which is much more readable.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve disassembly of jump targets on Gen6+.

Previously, flow control instructions generated output like:

(+f0) if(8) 12 8  null         0x000c0008UD { align16 WE_normal 1Q };

which included a dissasembly of the register fields, even though those
are meaningless for flow control instructions---those bits are reused
for another purpose.

It also wasn't immediately obvious which number was UIP and which was
JIP.

With this patch, we instead output:

(+f0) if(8)       JIP: 8       UIP: 12      { align16 WE_normal 1Q };

which is much clearer.

The patch also introduces has_uip/has_jip helper functions which clear
up a some generation/opcode checking mess.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Add support for new Gen8+ register types.

While we're at it, use proper names rather than magic numbers for the
existing fields.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Restyle brw_disasm.c.

brw_disasm.c basically wasn't following the Mesa coding style at all.
It used 4-space indent instead of 3-space, didn't cuddle braces, didn't
put function return types on a separate line, put extra spaces in
function calls (between the name and parenthesis), and a number of other
things.

This made it fairly obnoxious to work on, since my editor is configured
to follow Mesa style in the Mesa source repository.  Fixing it to follow
a consistent style now should save time dealing with it later.

These modifications were originally generated by:
$ indent -br -i3 -npcs -ce -cs -l80 --no-tabs
with some manual changes afterwards to fit our style better.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Create an "opcode" temporary.

This saves typing brw_inst_opcode(brw, inst) everywhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Eliminate opcode pointer.

opcode is just a pointer to opcode_descs; we may as well use that
directly.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

Remove the ATI_envmap_bumpmap extension

As far as I can tell, the Intel mesa driver is the only driver in the world
still supporting this legacy extension.  If someone wants to do bump
mapping, they can use shaders.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Reviewed-by: Ian Romanick <idr@freedesktop.org> [v3]

meta: Use AMD_vertex_shader_layer instead of a GS for layered clears.

On i965, enabling and disabling the GS is not free: you have to do a
full pipeline stall, reconfigure the URB and push constant space, and
emit a bunch of state.  Most clears aren't layered, so the GS isn't
needed in the common case.  But we turned it on universally.

Using AMD_vertex_shader_layer allows us to skip setting up the GS
altogether, while achieving the same effect.

According to Ilia, current nVidia GPUs can't do AMD_vertex_shader_layer.
However, since nouveau is Gallium-based, they're unlikely to ever care
about this path.  Intel and AMD GPUs both support the extension.

Since i965 is the only driver using this path which does layered
rendering, we may as well target it at that.

v2: Improve commit message.  No code changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

docs: mark "Geometry shader multiple streams" as done for i965

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Enable vertex streams up to MAX_VERTEX_STREAMS.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Enable simultaneous queries on different streams.

It should be possible to query the number of primitives written to each
individual stream by a geometry shader in a single draw call. For that
we need to have up to MAX_VERTEX_STREAM separate query objects.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.

So far we have been using CL_INVOCATION_COUNT to resolve this query but this
is no good with streams, as only stream 0 reaches the clipping stage. Instead
we will use SO_PRIM_STORAGE_NEEDED which can keep track of the primitives sent
to each individual stream.

Since SO_PRIM_STORAGE_NEEDED is related to the SOL stage and according to
ARB_transform_feedback3 we need to be able to query primitives generated in
each stream whether transform feedback is active or not what we do is to
enable the SOL unit even if transform feedback is not active but disable all
output buffers in that case. This effectively disables transform feedback
but permits activation of statistics enabling SO_PRIM_STORAGE_NEEDED even
when transform feedback is not active.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Implement GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN with non-zero streams.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

mesa: Include stream information in indexed queries.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: include streamId when reading/printing ir_variable IR.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: include streamId when reading/printing emit-vertex and end-primitive IR.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/gs: Set control data bits for vertices emitted in stream mode.

In stream mode we have to set control data bits with the StreamID
information for every vertex.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Validate vertex emission in geometry shaders.

Check if non-zero streams are used. Fail to link if emitting to unsupported
streams or emitting to non-zero streams with output type other than GL_POINTS.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Add support for EmitStreamVertex() and EndStreamPrimitive().

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Modify ir_end_primitive to have a stream.

This will be necessary to implement EndStreamPrimitive().
EndPrimitive() will produce an ir_end_primitive with the default stream 0.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Modify ir_emit_vertex to have a stream.

This will be necessary to implement EmitStreamVertex().
EmitVertex() will produce an ir_emit_vertex with the default stream 0.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965/gs: Set number of control data bits for stream mode.

If the geometry shader is indeed using streams then we need 2 control data
bits per vertex for the StreamID. If the shader is not using streams then
we don't need control data bits.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Store info about geometry shaders that emit vertices to non-zero streams.

On Intel hardware when a geometry shader outputs GL_POINTS primitives we
only need to emit vertex control bits if it emits vertices to non-zero
streams, so use a flag to track this.

This flag will be set to TRUE when a geometry shader calls EmitStreamVertex()
or EndStreamPrimitive() with a non-zero stream parameter in a later patch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Only geometry shader outputs can be associated with non-zero streams.

This should be ensured by the parser, so assert on that.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Two varyings can't write to the same buffer from different streams.

If this is detected, fail to link.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add methods to retrive a varying's name and streamId.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Fail to link if inter-stage input/outputs are not assigned to stream 0

Outputs that are linked to inputs in the next stage must be output to stream 0,
otherwise we should fail to link.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Assign GLSL StreamIds to transform feedback outputs.

Inter-shader outputs must be on stream 0, which is the default.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Enable transform feedback for streams > 0

Configure hardware to read vertex data for all streams and have all streams
write their varyings to the corresponsing output buffers.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add StreamId information to transform feedback outputs.

For now initialized to the default stream 0.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add parsing support for multi-stream output in geometry shaders.

This implements parsing requirements for multi-stream support in
geometry shaders as defined in ARB_gpu_shader5.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

st/omx: strcpy the string into the allocated buffer

This fixes commit a001ca98e15(st/omx: keep the name,
(name|role)_specific strings dynamically allocated) in which we
dynamically allocated the buffers for name and (name|role)_specific
yet forgot to copy the encoder strings into them.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80614
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: expose ARB_seamless_cubemap_per_texture when supported

All of the bits appear to already be in place to support this in the
sampler (which the original AMD version didn't allow).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/omx: keep the name, (name|role)_specific strings dynamically allocated

... as it's caller (the external program omxregister-bellagio) is the one
who frees all of the allocated memory.

Reported-by: Pedretti Fabio <pedretti.fabio@gmail.com>
Tested-by: Fabio Pedretti <pedretti.fabio@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

docs: Update the status of a few things in GL3.txt

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

nv50: fix dri3 prime buffer creation

This is the same fix than
"nvc0: fix dri3 prime buffer creation"

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nvc0: fix dri3 prime buffer creation

We need to place shared buffers into GART.

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium/dri2: implement blitImage

V3: call flush_resource before flush
V4: Add new flags

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri/image: add blitImage to the specification

It allows to blit two __DRIimages.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium: Add __DRIimageDriverExtension support to gallium

__DRIimageDriverExtension is used by GLX DRI3 and Wayland.

This patch is a rewrite of
http://lists.freedesktop.org/archives/mesa-dev/2014-May/060318.html
and
http://lists.freedesktop.org/archives/mesa-dev/2014-May/060317.html

Previous patches were:
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri3: use invalidate.

This doesn't change anything to the intel DRI3 implementation,
but enables the gallium implementation to use dri2.stamp instead
of relying on the stamp shared with the st backend.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri3: fix image extension checking.

Move the image extension setup in with all the others in
bind_extensions, and improve the check to both version
and function pointer.

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glxext: Send the Drawable's ID in the GLX_BufferSwapComplete event

While the official INTEL_swap_event specification says that the drawable
field should contain the GLXDrawable, not the Drawable, the existing
DRI2 code in dri2.c that translates from DRI2_BufferSwapComplete sends out
GLX_BufferSwapComplete with the Drawable's ID, so existing codebases
like Clutter/Cogl rely on getting the Drawable.

Match DRI2's error here and stuff the event with the X Drawable, not
the GLX drawable.

This fixes apps seeing wrong drawables through an indirect GLX context
or with DRI3, which uses the GLX_BufferSwapComplete event directly on
the wire instead of translates Present in mesa.

At the same time, also modify the structure for the event to make sure
that clients don't make the same mistake. This is not an API or ABI
break, as GLXDrawable and Drawable are both typedefs for XID.

Signed-off-by: Jasper St. Pierre <jstpierre@mecheye.net>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Enable compressed multisample support (CMS) on Broadwell.

Everything is in place and appears to be working.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Add 2x MSAA support to the MCS allocation function.

2x MSAA also uses 8 bits, just like 4x.  More bits are unused.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.

MCS buffers are never allocated on Broadwell, so this does nothing for
now, but puts the infrastructure in place for when they do exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Drop SINT workaround for CMS layout on Broadwell.

According to the documentation, we don't need this SINT workaround on
Broadwell.  (Or at least, it doesn't mention that we need it.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Add plumbing for Broadwell's auxiliary surface support.

Broadwell generalizes the MCS fields to allow for multiple kinds of
auxiliary surfaces.  This patch adds the plumbing to set those values,
but doesn't yet hook any up.

v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1.
v3: Don't forget to subtract 1 from aux_mt->pitch.
v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Add auxiliary surface field #defines for Broadwell.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Disassemble all of DP write message control bits on Gen6.

Prior to the new brw_inst API, the brw_instruction structure split off
bits 4 and 5 of msg_control for specific fields, and we failed to
disassemble them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Pass brw to brw_try_compact_instruction().

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add is_cherryview flag to brw_context.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add CSEL opcode definition for Gen8.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Document which instructions are generation specific.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Don't set UIP for ENDIF/WHILE.

They don't have a UIP. We used UIP in an array dereference, which never
caused problems on Gen < 8, since UIP was a small integer (number of
instructions). On Gen 8 UIP is in bytes, so it's large enough that it
caused us to read out of bounds of the array.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Replace struct brw_compact_instruction with brw_compact_inst.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Convert brw_eu_compact.c to the new brw_compact_inst API.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Introduce a new brw_compact_inst API.

For now nothing uses this, but we can incrementally convert.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Replace 'struct brw_instruction' with 'brw_inst'.

Use this an an opportunity to clean up the formatting of some old code
(brw_ADD, for instance).

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Throw out guts of struct brw_instruction.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Convert brw_gs_emit.c to the new brw_inst API.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Convert brw_disasm.c to the new brw_inst API.

v2: (by Kenneth Graunke)
 - Fix disassembly of Gen4-5 SEND messages to print base MRF correctly.
 - Only print URB opcode on Gen5+, to match previous output (besides,
   there is only one opcode AFAICT.)
 - Only print the low 3 bits of msg_control, to match previous output.
   (We probably should decode all the fields, but hadn't previously due
   to the brw_instruction structure definition splitting out bits 4/5
   for last_render_target and slot_group_select.)
 - Fix 3-source MRF/GRF file decoding on Sandybridge.
 - Fix compression code to use qtr_control rather than cmpt_control
   (which is compaction, not compression).

Signed-off-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [v2]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Pass brw rather than gen to brw_disassemble_inst().

We will need it in order to use the new brw_inst API.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Convert brw_eu_compact.c to the new brw_inst API.

v2: Use brw_inst_bits rather than pulling out individual fields and
    reassembling them.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators.

We're going to use fs_generator/vec4_generator for Gen8+ code soon,
thanks to the new brw_instruction API.  When we do, we'll generally
want to take the Haswell paths on Gen8+ as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Convert test_eu_compact.c to the new brw_inst API.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Convert vec4_generator to the new brw_inst API.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Convert fs_generator to the new brw_inst API.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Convert Gen4-5 clipping code to the new brw_inst API.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Convert brw_sf_emit.c to the new brw_inst API.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Convert brw_eu_emit.c to the new brw_inst API.

v2:
 - Fix IF -> ELSE patching on Sandybridge.
 - Don't set base_mrf on Gen6+ in OWord Block Read functions.  (Although
 - the old code did this universally, it shouldn't have - the field
 - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Convert brw_eu.[ch] to use the new brw_inst API.

v2: Don't set flag_reg_nr prior to Gen7 (as it doesn't exist).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Introduce a new brw_inst API.

This is similar to gen8_instruction, and will eventually replace it.

For now nothing uses this, but we can incrementally convert.
The new API takes the existing brw_instruction pointers to ease
conversion; when done, we can simply drop the old structure and rename
struct brw_instruction -> brw_inst.

v2: (by Matt Turner) Make JIP/UIP functions take a signed argument.
v3: (by Kenneth Graunke)
 - Make Gen4-6 jump target functions take a signed argument.
 - Fix indirect align1 AddrImm bits on Gen4-7.
 - Fix SFID on Sandybridge to use bits 27:24.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [v1, v3+]
Signed-off-by: Matt Turner <mattst88@gmail.com> [v2]
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Pass brw into next_offset().

The new brw_inst API is going to require a brw pointer in order
to access fields (so it can do generation checks).  Plumb it in now.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Remove unneeded VS workaround stalls on Baytrail.

According to the workarounds list, these stalls aren't needed on
production Baytrail systems.  Piglit confirms that as well.

These cause a small slowdown when we are sending a large number of small
batches to the GPU.  Removing these improves performance by up to 5% on
some CPU bound SynMark tests (Batch[4-7], DrvState1, HdrBloom,
Multithread, ShMapPcf).

Signed-off-by: Gregory Hunt <greg.hunt@mobica.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Include marketing names for Broadwell GPUs.

Intel would like us to include the marketing names.  Developers
additionally want "Broadwell GT1/2/3" because it makes it easier
to identify what hardware users have when they request assistance
or report issues.

Including both makes it easy for everyone to map between the names.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

softpipe: use last_level from sampler view, not from the resource

The last_level from the sampler view may be limited by the state tracker
to a value lower than what the base texture provides.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=80541.

Reviewed-by: Brian Paul <brianp@vmware.com>

targets/automake.inc: s/GALLIUM_VIDEO_CFLAGS/GALLIUM_TARGET_CFLAGS/

The flags are not specific to the video targets plus
we can reuse them for targets/xa and targets/gbm.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

auxiliary/vl: Remove no longer used SPLIT_TARGETS

Required for the conversion stage of all VL targets to
a single library per API (static/shared pipe-drivers).

No longer required as per last commit.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/radeonsi/omx: convert to static/shared pipe-drivers

The radeonsi counterpart of previous commit - now libomx-radeonsi is
built into the libomx-mesa library. Providing a single library per API.

v2: Include the radeon winsys only when there is a user for it.
v3: Correcly include the winsys. Now with extra brown bag :\

Note: Make sure to rebuild the .omxregister file, by executing
   $ omxregister-bellagio

This patch concludes the unification. Now libomx-mesa will be used
for all hardware - r600, radeonsi and nouveau.

Cc: Leo Liu <leo.liu@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

targets/r600/omx: convert to static/shared pipe-drivers

The r600 counterpart of previous commit - now the libomx-r600 is
built into the libomx-mesa library. Providing a single library per API.

v2: Include the radeon winsys only when there is a user for it.
v3: Correcly include the winsys. Now with extra brown bag :\

Note: Make sure to rebuild the .omxregister file, by executing
   $ omxregister-bellagio

If you have more than one omx library (libomx-radeonsi, libomx-r600),
make sure to temporary move the unused one. By the end of the series
there will be only one library that will be used for all hardware -
r600, radeonsi and nouveau.

Cc: Leo Liu <leo.liu@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

targets/omx-nouveau: convert to static/shared pipe-drivers

Similar to the vdpau/xvmc targets, we're going to convert the
multiple target libraries into a single one.

The library can be built with the relevant pipe-drivers
statically linked in, or loaded as shared modules.
Currently we default to static.

Note: Make sure to rebuild the .omxregister file, by executing
   $ omxregister-bellagio

If you have more than one omx library (libomx-radeonsi, libomx-r600),
make sure to temporary move the unused one. By the end of the series
there will be only one library that will be used for all hardware -
r600, radeonsi and nouveau.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

st/omx: avoid using dynamic vid_(enc|dec)_base and avc_(name|role)

Strictly speaking we should not have done this in the
first place, as all of the above should be static across
the system.

Currently this may cause some minor issues, which will be
resolved in the following patches, by providing a single
library for the OMX api.

Cleanup a few unneeded strcpy cases while we're around.

Note: Make sure to rebuild the .omxregister file, by executing
   $ omxregister-bellagio

If you have more than one omx library (libomx-radeonsi, libomx-r600),
make sure to temporary move the unused one. By the end of the series
there will be only one library that will be used for all hardware -
r600, radeonsi and nouveau.

Cc: Leo Liu <leo.liu@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

st/omx: provide constant number of components

The number of components and their names/roles should
be kept constant as all of that information cached.

Note: Make sure to rebuild the .omxregister file, by executing
   $ omxregister-bellagio.

Cc: Leo Liu <leo.liu@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

glx: Added missing null check in GetDrawableAttribute()

For GLX_BACK_BUFFER_AGE_EXT query added extra null check.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa/main: In register_surface() verify gl_texture_object was found

Verify _mesa_lookup_texture() returned valid pointer before using it.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>