yosys.git
10 years agoAdded removing of always inactive cells to "share" pass
Clifford Wolf [Sun, 20 Jul 2014 09:41:57 +0000 (11:41 +0200)]
Added removing of always inactive cells to "share" pass

10 years agoProgress in "share" pass
Clifford Wolf [Sun, 20 Jul 2014 08:36:46 +0000 (10:36 +0200)]
Progress in "share" pass

10 years agoAdded std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
Clifford Wolf [Sun, 20 Jul 2014 09:00:09 +0000 (11:00 +0200)]
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion

10 years agoAdded SIZE() macro
Clifford Wolf [Sun, 20 Jul 2014 08:36:14 +0000 (10:36 +0200)]
Added SIZE() macro

10 years agoAdded log_cell()
Clifford Wolf [Sun, 20 Jul 2014 08:35:47 +0000 (10:35 +0200)]
Added log_cell()

10 years agoProgress in "share" pass
Clifford Wolf [Sun, 20 Jul 2014 01:03:04 +0000 (03:03 +0200)]
Progress in "share" pass

10 years agoAdded tests/vloghtb
Clifford Wolf [Sun, 20 Jul 2014 00:19:44 +0000 (02:19 +0200)]
Added tests/vloghtb

10 years agoUse functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend
Clifford Wolf [Sun, 20 Jul 2014 00:16:30 +0000 (02:16 +0200)]
Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend

10 years agoAdded support for $bu0 to verilog backend
Clifford Wolf [Sat, 19 Jul 2014 23:56:16 +0000 (01:56 +0200)]
Added support for $bu0 to verilog backend

10 years agoStarted to implement real resource sharing
Clifford Wolf [Sat, 19 Jul 2014 18:54:32 +0000 (20:54 +0200)]
Started to implement real resource sharing

10 years agoFixed log_id() memory corruption
Clifford Wolf [Sat, 19 Jul 2014 18:53:29 +0000 (20:53 +0200)]
Fixed log_id() memory corruption

10 years agoImproved memory_share log messages
Clifford Wolf [Sat, 19 Jul 2014 13:46:11 +0000 (15:46 +0200)]
Improved memory_share log messages

10 years agoMore verbose memory_share help message
Clifford Wolf [Sat, 19 Jul 2014 13:34:14 +0000 (15:34 +0200)]
More verbose memory_share help message

10 years agoAdded SAT-based write-port sharing to memory_share
Clifford Wolf [Sat, 19 Jul 2014 13:33:55 +0000 (15:33 +0200)]
Added SAT-based write-port sharing to memory_share

10 years agoAdded ModWalker helper class
Clifford Wolf [Sat, 19 Jul 2014 13:33:00 +0000 (15:33 +0200)]
Added ModWalker helper class

10 years agoSome "const" cleanups in SigMap
Clifford Wolf [Sat, 19 Jul 2014 13:32:39 +0000 (15:32 +0200)]
Some "const" cleanups in SigMap

10 years agoFixed bug in memory_share feedback-to-en code
Clifford Wolf [Sat, 19 Jul 2014 13:32:14 +0000 (15:32 +0200)]
Fixed bug in memory_share feedback-to-en code

10 years agoAdded translation from read-feedback to en-signals in memory_share
Clifford Wolf [Fri, 18 Jul 2014 14:46:40 +0000 (16:46 +0200)]
Added translation from read-feedback to en-signals in memory_share

10 years agoImproved seeding of color rng in show command
Clifford Wolf [Fri, 18 Jul 2014 14:44:45 +0000 (16:44 +0200)]
Improved seeding of color rng in show command

10 years agoOnly create collision detect logic in memory_share if necessary
Clifford Wolf [Fri, 18 Jul 2014 12:32:40 +0000 (14:32 +0200)]
Only create collision detect logic in memory_share if necessary

10 years agoBugfix in tests/memories/run-test.sh
Clifford Wolf [Fri, 18 Jul 2014 11:45:25 +0000 (13:45 +0200)]
Bugfix in tests/memories/run-test.sh

10 years agoadded tests/memories
Clifford Wolf [Fri, 18 Jul 2014 11:25:19 +0000 (13:25 +0200)]
added tests/memories

10 years agoAdded memory_share
Clifford Wolf [Fri, 18 Jul 2014 10:40:01 +0000 (12:40 +0200)]
Added memory_share

10 years agoAdded automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
Clifford Wolf [Fri, 18 Jul 2014 09:36:34 +0000 (11:36 +0200)]
Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>

10 years agoApply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
Clifford Wolf [Fri, 18 Jul 2014 08:28:45 +0000 (10:28 +0200)]
Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port

10 years agoAdded function-like cell creation helpers
Clifford Wolf [Fri, 18 Jul 2014 08:27:06 +0000 (10:27 +0200)]
Added function-like cell creation helpers

10 years agoAdded log_id() helper function
Clifford Wolf [Fri, 18 Jul 2014 08:26:01 +0000 (10:26 +0200)]
Added log_id() helper function

10 years agoAlso simulate unmapped memories in "make test"
Clifford Wolf [Thu, 17 Jul 2014 14:53:52 +0000 (16:53 +0200)]
Also simulate unmapped memories in "make test"

10 years agoImplemented dynamic bit-/part-select for memory writes
Clifford Wolf [Thu, 17 Jul 2014 14:49:23 +0000 (16:49 +0200)]
Implemented dynamic bit-/part-select for memory writes

10 years agoFixed simlib.v model for $mem
Clifford Wolf [Thu, 17 Jul 2014 14:48:36 +0000 (16:48 +0200)]
Fixed simlib.v model for $mem

10 years agoAdded support for bit/part select to mem2reg rewriter
Clifford Wolf [Thu, 17 Jul 2014 11:49:32 +0000 (13:49 +0200)]
Added support for bit/part select to mem2reg rewriter

10 years agoAdded support for constant bit- or part-select for memory writes
Clifford Wolf [Thu, 17 Jul 2014 11:13:21 +0000 (13:13 +0200)]
Added support for constant bit- or part-select for memory writes

10 years agoImproved opt_reduce handling of mem wr_en mux bits
Clifford Wolf [Thu, 17 Jul 2014 10:12:04 +0000 (12:12 +0200)]
Improved opt_reduce handling of mem wr_en mux bits

10 years agoFixed RTLIL::SigSpec::append_bit() for appending constants
Clifford Wolf [Thu, 17 Jul 2014 10:10:57 +0000 (12:10 +0200)]
Fixed RTLIL::SigSpec::append_bit() for appending constants

10 years agoAdded support for "blackbox" attribute to iopadmap
Clifford Wolf [Thu, 17 Jul 2014 06:59:07 +0000 (08:59 +0200)]
Added support for "blackbox" attribute to iopadmap

10 years agoAdded support for "blackbox" attribute to flatten/techmap
Clifford Wolf [Thu, 17 Jul 2014 06:58:51 +0000 (08:58 +0200)]
Added support for "blackbox" attribute to flatten/techmap

10 years agoAdded "inout" ports support to read_liberty
Clifford Wolf [Wed, 16 Jul 2014 16:12:46 +0000 (18:12 +0200)]
Added "inout" ports support to read_liberty

10 years agoSet blackbox attribute in "read_liberty -lib"
Clifford Wolf [Wed, 16 Jul 2014 16:12:16 +0000 (18:12 +0200)]
Set blackbox attribute in "read_liberty -lib"

10 years agoFixed spelling of "direction" in read_liberty messages
Clifford Wolf [Wed, 16 Jul 2014 16:02:28 +0000 (18:02 +0200)]
Fixed spelling of "direction" in read_liberty messages

10 years agoMerged new $mem/$memwr WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 12:15:33 +0000 (14:15 +0200)]
Merged new $mem/$memwr WR_EN interface

10 years agoChanged tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 11:46:27 +0000 (13:46 +0200)]
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface

10 years agoimproved opt_reduce for $mem/$memwr WR_EN multiplexers
Clifford Wolf [Wed, 16 Jul 2014 11:37:41 +0000 (13:37 +0200)]
improved opt_reduce for $mem/$memwr WR_EN multiplexers

10 years agochanges in verilog frontend for new $mem/$memwr WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 10:23:47 +0000 (12:23 +0200)]
changes in verilog frontend for new $mem/$memwr WR_EN interface

10 years agoChanges to "memory" pass for new $memwr/$mem WR_EN interface
Clifford Wolf [Wed, 16 Jul 2014 10:13:13 +0000 (12:13 +0200)]
Changes to "memory" pass for new $memwr/$mem WR_EN interface

10 years agoUpdated simlib to new $mem/$memwr interface
Clifford Wolf [Wed, 16 Jul 2014 09:46:40 +0000 (11:46 +0200)]
Updated simlib to new $mem/$memwr interface

10 years agoChanged the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf [Wed, 16 Jul 2014 09:38:02 +0000 (11:38 +0200)]
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal

10 years agoAdded note to "make test": use git checkout of iverilog
Clifford Wolf [Wed, 16 Jul 2014 08:03:07 +0000 (10:03 +0200)]
Added note to "make test": use git checkout of iverilog

10 years agoAdded passing of various options to vhdl2verilog
Clifford Wolf [Sat, 12 Jul 2014 08:02:39 +0000 (10:02 +0200)]
Added passing of various options to vhdl2verilog

10 years agoUse "verilog -sv" to parse .sv files
Clifford Wolf [Fri, 11 Jul 2014 11:10:51 +0000 (13:10 +0200)]
Use "verilog -sv" to parse .sv files

10 years agoFixed processing of initial values for block-local variables
Clifford Wolf [Fri, 11 Jul 2014 11:05:53 +0000 (13:05 +0200)]
Fixed processing of initial values for block-local variables

10 years agonow ignore init attributes on non-register wires in sat command
Clifford Wolf [Sat, 5 Jul 2014 09:17:40 +0000 (11:17 +0200)]
now ignore init attributes on non-register wires in sat command

10 years agofixed parsing of constant with comment between size and value
Clifford Wolf [Wed, 2 Jul 2014 04:27:04 +0000 (06:27 +0200)]
fixed parsing of constant with comment between size and value

10 years agosmall changes in presentation
Clifford Wolf [Wed, 2 Jul 2014 04:16:31 +0000 (06:16 +0200)]
small changes in presentation

10 years agoTiny fix in presentation
Clifford Wolf [Sun, 29 Jun 2014 07:27:03 +0000 (09:27 +0200)]
Tiny fix in presentation

10 years agoProgress in presentation
Clifford Wolf [Sun, 29 Jun 2014 07:14:49 +0000 (09:14 +0200)]
Progress in presentation

10 years agoAdded links to some liberty files to README
Clifford Wolf [Sat, 28 Jun 2014 10:11:42 +0000 (12:11 +0200)]
Added links to some liberty files to README

10 years agoProgress in presentation
Clifford Wolf [Thu, 26 Jun 2014 20:05:39 +0000 (22:05 +0200)]
Progress in presentation

10 years agoFixed handling of mixed real/int ternary expressions
Clifford Wolf [Wed, 25 Jun 2014 08:05:36 +0000 (10:05 +0200)]
Fixed handling of mixed real/int ternary expressions

10 years agoMore found_real-related fixes to AstNode::detectSignWidthWorker
Clifford Wolf [Tue, 24 Jun 2014 13:08:48 +0000 (15:08 +0200)]
More found_real-related fixes to AstNode::detectSignWidthWorker

10 years agoProgress in presentation
Clifford Wolf [Sun, 22 Jun 2014 10:50:29 +0000 (12:50 +0200)]
Progress in presentation

10 years agoLittle steps in realmath test bench
Clifford Wolf [Sat, 21 Jun 2014 19:43:04 +0000 (21:43 +0200)]
Little steps in realmath test bench

10 years agofixed signdness detection for expressions with reals
Clifford Wolf [Sat, 21 Jun 2014 19:41:13 +0000 (21:41 +0200)]
fixed signdness detection for expressions with reals

10 years agofixed typo
Clifford Wolf [Sat, 21 Jun 2014 19:13:18 +0000 (21:13 +0200)]
fixed typo

10 years agoProgress in presentation
Clifford Wolf [Sat, 21 Jun 2014 14:33:33 +0000 (16:33 +0200)]
Progress in presentation

10 years agoDo not create $dffsr cells with no-op resets in proc_dff
Clifford Wolf [Thu, 19 Jun 2014 10:29:29 +0000 (12:29 +0200)]
Do not create $dffsr cells with no-op resets in proc_dff

10 years agoAdded test case for AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf [Tue, 17 Jun 2014 19:49:59 +0000 (21:49 +0200)]
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS

10 years agoAdded AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf [Tue, 17 Jun 2014 19:39:25 +0000 (21:39 +0200)]
Added AstNode::MEM2REG_FL_CMPLX_LHS

10 years agoImproved handling of relational op of real values
Clifford Wolf [Tue, 17 Jun 2014 10:47:51 +0000 (12:47 +0200)]
Improved handling of relational op of real values

10 years agoLittle steps in realmath test bench
Clifford Wolf [Mon, 16 Jun 2014 13:21:08 +0000 (15:21 +0200)]
Little steps in realmath test bench

10 years agoImproved ternary support for real values
Clifford Wolf [Mon, 16 Jun 2014 13:12:24 +0000 (15:12 +0200)]
Improved ternary support for real values

10 years agoUse undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
Clifford Wolf [Mon, 16 Jun 2014 13:05:37 +0000 (15:05 +0200)]
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012

10 years agoFixed parsing of TOK_INTEGER (implies TOK_SIGNED)
Clifford Wolf [Mon, 16 Jun 2014 13:02:40 +0000 (15:02 +0200)]
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)

10 years agoAdded found_real feature to AstNode::detectSignWidth
Clifford Wolf [Mon, 16 Jun 2014 13:00:57 +0000 (15:00 +0200)]
Added found_real feature to AstNode::detectSignWidth

10 years agoAdded more calls to "hierarchy" to README file
Clifford Wolf [Sun, 15 Jun 2014 09:51:51 +0000 (11:51 +0200)]
Added more calls to "hierarchy" to README file

10 years agoRemoved long running tests from tests/simple/realexpr.v (replaced by tests/realmath)
Clifford Wolf [Sun, 15 Jun 2014 07:39:22 +0000 (09:39 +0200)]
Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)

10 years agoAdded tests/realmath to "make test"
Clifford Wolf [Sun, 15 Jun 2014 07:31:03 +0000 (09:31 +0200)]
Added tests/realmath to "make test"

10 years agoImproved AstNode::realAsConst for large numbers
Clifford Wolf [Sun, 15 Jun 2014 07:27:09 +0000 (09:27 +0200)]
Improved AstNode::realAsConst for large numbers

10 years agoImproved realmath test bench
Clifford Wolf [Sun, 15 Jun 2014 06:48:41 +0000 (08:48 +0200)]
Improved realmath test bench

10 years agoImproved parsing of large integer constants
Clifford Wolf [Sun, 15 Jun 2014 06:48:17 +0000 (08:48 +0200)]
Improved parsing of large integer constants

10 years agoImproved AstNode::asReal for large integers
Clifford Wolf [Sun, 15 Jun 2014 06:38:31 +0000 (08:38 +0200)]
Improved AstNode::asReal for large integers

10 years agoimproved realmath test bench
Clifford Wolf [Sat, 14 Jun 2014 18:38:40 +0000 (20:38 +0200)]
improved realmath test bench

10 years agoimproved (fixed) conversion of real values to bit vectors
Clifford Wolf [Sat, 14 Jun 2014 18:38:05 +0000 (20:38 +0200)]
improved (fixed) conversion of real values to bit vectors

10 years agoprogress in realmath test bench
Clifford Wolf [Sat, 14 Jun 2014 17:56:22 +0000 (19:56 +0200)]
progress in realmath test bench

10 years agoFixed relational operators for const real expressions
Clifford Wolf [Sat, 14 Jun 2014 17:33:58 +0000 (19:33 +0200)]
Fixed relational operators for const real expressions

10 years agoadded first draft of real math testcase generator
Clifford Wolf [Sat, 14 Jun 2014 17:24:01 +0000 (19:24 +0200)]
added first draft of real math testcase generator

10 years agoProgress in presentation
Clifford Wolf [Sat, 14 Jun 2014 14:42:30 +0000 (16:42 +0200)]
Progress in presentation

10 years agoAdded %D and %c select commands
Clifford Wolf [Sat, 14 Jun 2014 14:19:32 +0000 (16:19 +0200)]
Added %D and %c select commands

10 years agoAdded support for math functions
Clifford Wolf [Sat, 14 Jun 2014 11:36:23 +0000 (13:36 +0200)]
Added support for math functions

10 years agoAdded realexpr.v test case
Clifford Wolf [Sat, 14 Jun 2014 10:01:17 +0000 (12:01 +0200)]
Added realexpr.v test case

10 years agoAdded handling of real-valued parameters/localparams
Clifford Wolf [Sat, 14 Jun 2014 10:00:47 +0000 (12:00 +0200)]
Added handling of real-valued parameters/localparams

10 years agoImplemented more real arithmetic
Clifford Wolf [Sat, 14 Jun 2014 09:27:05 +0000 (11:27 +0200)]
Implemented more real arithmetic

10 years agoImplemented basic real arithmetic
Clifford Wolf [Sat, 14 Jun 2014 06:51:22 +0000 (08:51 +0200)]
Implemented basic real arithmetic

10 years agoAdded real->int convertion in ast genrtlil
Clifford Wolf [Sat, 14 Jun 2014 05:44:19 +0000 (07:44 +0200)]
Added real->int convertion in ast genrtlil

10 years agoAdded Verilog lexer and parser support for real values
Clifford Wolf [Fri, 13 Jun 2014 09:29:23 +0000 (11:29 +0200)]
Added Verilog lexer and parser support for real values

10 years agoAdded read_verilog -sv options, added support for bit, logic,
Clifford Wolf [Thu, 12 Jun 2014 09:54:20 +0000 (11:54 +0200)]
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch

10 years agoNow we are in Yoys 0.3.0+ development
Clifford Wolf [Sun, 8 Jun 2014 13:31:27 +0000 (15:31 +0200)]
Now we are in Yoys 0.3.0+ development

10 years agoTagging Yosys 0.3.0 yosys-0.3.0
Clifford Wolf [Sun, 8 Jun 2014 13:28:36 +0000 (15:28 +0200)]
Tagging Yosys 0.3.0

10 years agoUpdated ABC to 7600ffb9340c
Clifford Wolf [Sun, 8 Jun 2014 08:12:39 +0000 (10:12 +0200)]
Updated ABC to 7600ffb9340c

10 years agoadded tests for new verilog features
Clifford Wolf [Sat, 7 Jun 2014 10:18:00 +0000 (12:18 +0200)]
added tests for new verilog features

10 years agofixed cell array handling of positional arguments
Clifford Wolf [Sat, 7 Jun 2014 10:17:06 +0000 (12:17 +0200)]
fixed cell array handling of positional arguments